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Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.3.2 Subject: Re: [PATCH v6 19/21] riscv: dts: starfive: Add initial StarFive JH7110 device tree Content-Language: en-US To: Conor Dooley , Conor Dooley CC: , , , Stephen Boyd , "Michael Turquette" , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou , Ben Dooks , Daniel Lezcano , Thomas Gleixner , Marc Zyngier , "Emil Renner Berthing" , References: <20230320103750.60295-1-hal.feng@starfivetech.com> <20230320103750.60295-20-hal.feng@starfivetech.com> <60359574-8bce-40f2-99db-6d81f6e6c5c3@spud> <6ce5b897-f1c2-4b58-9353-9d9e881ad237@spud> From: Hal Feng In-Reply-To: <6ce5b897-f1c2-4b58-9353-9d9e881ad237@spud> X-Originating-IP: [113.72.145.117] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX172.cuchost.com (172.16.6.92) X-YovoleRuleAgent: yovoleflag X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230324_000405_787190_FF530E82 X-CRM114-Status: GOOD ( 16.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, 23 Mar 2023 09:03:23 +0000, Conor Dooley wrote: > On Wed, Mar 22, 2023 at 10:02:40PM +0000, Conor Dooley wrote: >> On Mon, Mar 20, 2023 at 06:37:48PM +0800, Hal Feng wrote: >> > From: Emil Renner Berthing >> > >> > Add initial device tree for the JH7110 RISC-V SoC by StarFive >> > Technology Ltd. >> > >> > Tested-by: Tommaso Merciai >> > Reviewed-by: Conor Dooley >> > Signed-off-by: Emil Renner Berthing >> > Co-developed-by: Jianlong Huang >> > Signed-off-by: Jianlong Huang >> > Co-developed-by: Hal Feng >> > Signed-off-by: Hal Feng >> > --- >> >> > + S7_0: cpu@0 { >> > + compatible = "sifive,s7", "riscv"; >> > + reg = <0>; >> > + d-cache-block-size = <64>; >> > + d-cache-sets = <64>; >> > + d-cache-size = <8192>; >> > + d-tlb-sets = <1>; >> > + d-tlb-size = <40>; >> > + device_type = "cpu"; >> > + i-cache-block-size = <64>; >> > + i-cache-sets = <64>; >> > + i-cache-size = <16384>; >> > + i-tlb-sets = <1>; >> > + i-tlb-size = <40>; >> > + mmu-type = "riscv,sv39"; >> > + next-level-cache = <&ccache>; >> > + riscv,isa = "rv64imac_zba_zbb"; >> > + tlb-split; >> > + status = "disabled"; >> >> Jess pointed out on IRC that this S7 entry looks wrong as it is claiming >> that the S7 has an mmu. I didn't go looking back in the history of >> u74-mc core complex manuals, but the latest version does not show an mmu >> for the S7. > > BTW Hal, if the dt-binding stuff is okay with Emil, I can just remove > the mmu here if you confirm it is a mistake rather than you needing to > resubmit to remove it. I confirm that the S7 core has no L1 data cache and MMU, so some properties should be deleted. I have submitted a new patch for the correction. https://lore.kernel.org/all/20230324064651.84670-1-hal.feng@starfivetech.com/ Best regards, Hal _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv