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Thu, 8 Apr 2021 19:01:02 +0000 (UTC) Received: from llong.remote.csb (ovpn-119-36.rdu2.redhat.com [10.10.119.36]) by smtp.corp.redhat.com (Postfix) with ESMTP id 12A63101F501; Thu, 8 Apr 2021 19:00:59 +0000 (UTC) Subject: Re: [OpenRISC] [PATCH v6 1/9] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 To: Stafford Horne , Boqun Feng Cc: guoren@kernel.org, linux-arch@vger.kernel.org, linux-xtensa@linux-xtensa.org, Guo Ren , Arnd Bergmann , Peter Zijlstra , Will Deacon , linux-kernel@vger.kernel.org, linux-csky@vger.kernel.org, openrisc@lists.librecores.org, Anup Patel , sparclinux@vger.kernel.org, linux-riscv@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Ingo Molnar References: <1617201040-83905-1-git-send-email-guoren@kernel.org> <1617201040-83905-2-git-send-email-guoren@kernel.org> <20210406235208.GG3288043@lianli.shorne-pla.net> From: Waiman Long Organization: Red Hat Message-ID: <1199af5f-275a-5812-fc73-f1d33449036b@redhat.com> Date: Thu, 8 Apr 2021 15:00:59 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.0 MIME-Version: 1.0 In-Reply-To: <20210406235208.GG3288043@lianli.shorne-pla.net> Content-Language: en-US X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210408_200109_877337_4D34AC0D X-CRM114-Status: GOOD ( 16.25 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 4/6/21 7:52 PM, Stafford Horne wrote: > > For OpenRISC I did ack the patch to convert to > CONFIG_ARCH_USE_QUEUED_SPINLOCKS_XCHG32=y. But I think you are right, the > generic code in xchg_tail and the xchg16 emulation code in produced by OpenRISC > using xchg32 would produce very similar code. I have not compared instructions, > but it does seem like duplicate functionality. > > Why doesn't RISC-V add the xchg16 emulation code similar to OpenRISC? For > OpenRISC we added xchg16 and xchg8 emulation code to enable qspinlocks. So > one thought is with CONFIG_ARCH_USE_QUEUED_SPINLOCKS_XCHG32=y, can we remove our > xchg16/xchg8 emulation code? For the record, the latest qspinlock code doesn't use xchg8 anymore. It still need xchg16, though. Cheers, Longman _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv