From: Atish Patra <atish.patra@wdc.com>
To: linux-kernel@vger.kernel.org
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Damien Le Moal <Damien.LeMoal@wdc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Dmitriy Cherkasov <dmitriy@oss-tech.org>,
Anup Patel <anup@brainfault.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Christoph Hellwig <hch@infradead.org>,
Atish Patra <atish.patra@wdc.com>,
Rob Herring <robh+dt@kernel.org>,
Palmer Dabbelt <palmer@sifive.com>,
linux-riscv@lists.infradead.org,
Thomas Gleixner <tglx@linutronix.de>
Subject: [PATCH v2 0/4] Timer code cleanup.
Date: Thu, 13 Dec 2018 15:14:25 -0800 [thread overview]
Message-ID: <1544742869-19980-1-git-send-email-atish.patra@wdc.com> (raw)
This patch series provides an assorted timer cleanups in RISC-V.
Changes from v1->v2:
1. Updated commit text in 1/4.
2. Added a timebase check for each cpu.
3. Added a warning for invalid hartid 4/4.
Atish Patra (3):
RISC-V: Support per-hart timebase-frequency
RISC-V: Remove per cpu clocksource
RISC-V: Fix non-smp kernel boot on SMP systems
Palmer Dabbelt (1):
dt-bindings: Correct RISC-V's timebase-frequency
Documentation/devicetree/bindings/riscv/cpus.txt | 4 +-
arch/riscv/kernel/time.c | 9 +----
drivers/clocksource/riscv_timer.c | 51 +++++++++++++++++++++---
3 files changed, 49 insertions(+), 15 deletions(-)
--
2.7.4
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next reply other threads:[~2018-12-13 23:15 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-13 23:14 Atish Patra [this message]
2018-12-13 23:14 ` [PATCH v2 1/4] dt-bindings: Correct RISC-V's timebase-frequency Atish Patra
2018-12-14 9:17 ` Daniel Lezcano
2019-01-04 0:36 ` Palmer Dabbelt
2019-01-07 8:56 ` Daniel Lezcano
2018-12-13 23:14 ` [PATCH v2 2/4] RISC-V: Support per-hart timebase-frequency Atish Patra
2018-12-14 9:24 ` Daniel Lezcano
2018-12-13 23:14 ` [PATCH v2 3/4] RISC-V: Remove per cpu clocksource Atish Patra
2018-12-13 23:14 ` [PATCH v2 4/4] RISC-V: Fix non-smp kernel boot on SMP systems Atish Patra
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