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Mon, 06 May 2019 03:49:06 -0700 (PDT) From: Yash Shah To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, palmer@sifive.com Subject: [PATCH v3 0/2] L2 cache controller support for SiFive FU540 Date: Mon, 6 May 2019 16:18:38 +0530 Message-Id: <1557139720-12384-1-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190506_034912_087654_08B93981 X-CRM114-Status: GOOD ( 12.55 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org, afd@ti.com, sachin.ghadi@sifive.com, Yash Shah , robh+dt@kernel.org, paul.walmsley@sifive.com MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org This patch series adds an L2 cache controller driver with DT documentation for SiFive FU540-C000. These two patches were initially part of the patch series: 'L2 cache controller and EDAC support for SiFive SoCs' https://lkml.org/lkml/2019/4/15/320 In order to merge L2 cache controller driver without any dependency on EDAC, the L2 cache controller patches are re-posted separately in this series. The patchset is based on Linux 5.1-rc2 and tested on HiFive Unleashed board with additional board related patches needed for testing can be found at dev/yashs/L2_cache_controller branch of: https://github.com/yashshah7/riscv-linux.git Changes since v2 - Add a header file to expose Macros and extern functions - Remove all single line functions Changes since v1 - Mention the valid values for cache properties in DT documentation - Remove the unnecessary property 'reg-names' - Add "cache" to supported compatible string property - Remove conditional checks from debugfs functions in sifive_l2_cache.c Yash Shah (2): RISC-V: Add DT documentation for SiFive L2 Cache Controller RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs .../devicetree/bindings/riscv/sifive-l2-cache.txt | 51 ++++++ arch/riscv/include/asm/sifive_l2_cache.h | 16 ++ arch/riscv/mm/Makefile | 1 + arch/riscv/mm/sifive_l2_cache.c | 175 +++++++++++++++++++++ 4 files changed, 243 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt create mode 100644 arch/riscv/include/asm/sifive_l2_cache.h create mode 100644 arch/riscv/mm/sifive_l2_cache.c -- 1.9.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv