From: Yash Shah <yash.shah@sifive.com>
To: linux-pwm@vger.kernel.org, linux-riscv@lists.infradead.org,
thierry.reding@gmail.com
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
aou@eecs.berkeley.edu, palmer@sifive.com,
linux-kernel@vger.kernel.org, sachin.ghadi@sifive.com,
Yash Shah <yash.shah@sifive.com>,
robh+dt@kernel.org, paul.walmsley@sifive.com
Subject: [PATCH v12 1/2] pwm: sifive: Add DT documentation for SiFive PWM Controller
Date: Mon, 13 May 2019 17:06:19 +0530 [thread overview]
Message-ID: <1557747380-12257-2-git-send-email-yash.shah@sifive.com> (raw)
In-Reply-To: <1557747380-12257-1-git-send-email-yash.shah@sifive.com>
DT documentation for PWM controller added.
Signed-off-by: Wesley W. Terpstra <wesley@sifive.com>
[Atish: Compatible string update]
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/pwm/pwm-sifive.txt | 33 ++++++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt
diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
new file mode 100644
index 0000000..36447e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
@@ -0,0 +1,33 @@
+SiFive PWM controller
+
+Unlike most other PWM controllers, the SiFive PWM controller currently only
+supports one period for all channels in the PWM. All PWMs need to run at
+the same period. The period also has significant restrictions on the values
+it can achieve, which the driver rounds to the nearest achievable period.
+PWM RTL that corresponds to the IP block version numbers can be found
+here:
+
+https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
+
+Required properties:
+- compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>".
+ Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive
+ PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
+ SiFive PWM v0 IP block with no chip integration tweaks.
+ Please refer to sifive-blocks-ip-versioning.txt for details.
+- reg: physical base address and length of the controller's registers
+- clocks: Should contain a clock identifier for the PWM's parent clock.
+- #pwm-cells: Should be 3. See pwm.txt in this directory
+ for a description of the cell format.
+- interrupts: one interrupt per PWM channel
+
+Examples:
+
+pwm: pwm@10020000 {
+ compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x10020000 0x0 0x1000>;
+ clocks = <&tlclk>;
+ interrupt-parent = <&plic>;
+ interrupts = <42 43 44 45>;
+ #pwm-cells = <3>;
+};
--
1.9.1
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next prev parent reply other threads:[~2019-05-13 11:36 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-13 11:36 [PATCH v12 0/2] PWM support for HiFive Unleashed Yash Shah
2019-05-13 11:36 ` Yash Shah [this message]
2019-05-13 11:36 ` [PATCH v12 2/2] pwm: sifive: Add a driver for SiFive SoC PWM Yash Shah
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