From: Yash Shah <yash.shah@sifive.com>
To: robh+dt@kernel.org, mark.rutland@arm.com, paul.walmsley@sifive.com
Cc: devicetree@vger.kernel.org, aou@eecs.berkeley.edu,
atish.patra@wdc.com, gregkh@linuxfoundation.org,
linux-kernel@vger.kernel.org, alexios.zavras@intel.com,
Yash Shah <yash.shah@sifive.com>,
palmer@dabbelt.com, tglx@linutronix.de, bmeng.cn@gmail.com,
linux-riscv@lists.infradead.org, allison@lohutok.net
Subject: [PATCH 0/2] L2 ccache DT and cacheinfo support to read no. of L2 cache ways enabled
Date: Mon, 9 Dec 2019 16:55:04 +0530 [thread overview]
Message-ID: <1575890706-36162-1-git-send-email-yash.shah@sifive.com> (raw)
The patchset includes the patch to implement a private attribute named
"number_of_ways_enabled" in the cacheinfo framework. Reading this
attribute returns the number of L2 cache ways enabled at runtime,
The patchset also include the patch to add DT node for SiFive L2 cache
controller.
This patchset is based on Linux v5.4 and tested on HiFive Unleashed
board. The cacheinfo patch depends on Christoph Hellwig's patch:
"riscv: move sifive_l2_cache.c to drivers/soc"
Yash Shah (2):
riscv: dts: Add DT support for SiFive L2 cache controller
riscv: cacheinfo: Add support to determine no. of L2 cache way enabled
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 26 +++++++++++++++++++++++++
arch/riscv/include/asm/sifive_l2_cache.h | 2 ++
arch/riscv/kernel/cacheinfo.c | 31 ++++++++++++++++++++++++++++++
drivers/soc/sifive/sifive_l2_cache.c | 5 +++++
4 files changed, 64 insertions(+)
--
2.7.4
next reply other threads:[~2019-12-09 11:25 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-09 11:25 Yash Shah [this message]
2019-12-09 11:25 ` [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller Yash Shah
2019-12-09 11:25 ` [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2 cache way enabled Yash Shah
2019-12-14 2:12 ` Palmer Dabbelt
2019-12-15 19:56 ` Paul Walmsley
2019-12-23 8:53 ` Yash Shah
2019-12-14 2:13 ` [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller Palmer Dabbelt
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1575890706-36162-1-git-send-email-yash.shah@sifive.com \
--to=yash.shah@sifive.com \
--cc=alexios.zavras@intel.com \
--cc=allison@lohutok.net \
--cc=aou@eecs.berkeley.edu \
--cc=atish.patra@wdc.com \
--cc=bmeng.cn@gmail.com \
--cc=devicetree@vger.kernel.org \
--cc=gregkh@linuxfoundation.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=mark.rutland@arm.com \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).