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* [PATCH 0/2] L2 ccache DT and cacheinfo support to read no. of L2 cache ways enabled
@ 2019-12-09 11:25 Yash Shah
  2019-12-09 11:25 ` [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller Yash Shah
                   ` (3 more replies)
  0 siblings, 4 replies; 7+ messages in thread
From: Yash Shah @ 2019-12-09 11:25 UTC (permalink / raw)
  To: robh+dt, mark.rutland, paul.walmsley
  Cc: devicetree, aou, atish.patra, gregkh, linux-kernel,
	alexios.zavras, Yash Shah, palmer, tglx, bmeng.cn, linux-riscv,
	allison

The patchset includes the patch to implement a private attribute named
"number_of_ways_enabled" in the cacheinfo framework. Reading this
attribute returns the number of L2 cache ways enabled at runtime,
The patchset also include the patch to add DT node for SiFive L2 cache
controller.

This patchset is based on Linux v5.4 and tested on HiFive Unleashed
board. The cacheinfo patch depends on Christoph Hellwig's patch:
"riscv: move sifive_l2_cache.c to drivers/soc"

Yash Shah (2):
  riscv: dts: Add DT support for SiFive L2 cache controller
  riscv: cacheinfo: Add support to determine no. of L2 cache way enabled

 arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 26 +++++++++++++++++++++++++
 arch/riscv/include/asm/sifive_l2_cache.h   |  2 ++
 arch/riscv/kernel/cacheinfo.c              | 31 ++++++++++++++++++++++++++++++
 drivers/soc/sifive/sifive_l2_cache.c       |  5 +++++
 4 files changed, 64 insertions(+)

-- 
2.7.4



^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller
  2019-12-09 11:25 [PATCH 0/2] L2 ccache DT and cacheinfo support to read no. of L2 cache ways enabled Yash Shah
@ 2019-12-09 11:25 ` Yash Shah
  2019-12-09 11:25 ` [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2 cache way enabled Yash Shah
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 7+ messages in thread
From: Yash Shah @ 2019-12-09 11:25 UTC (permalink / raw)
  To: robh+dt, mark.rutland, paul.walmsley
  Cc: devicetree, aou, atish.patra, gregkh, linux-kernel,
	alexios.zavras, Yash Shah, palmer, tglx, bmeng.cn, linux-riscv,
	allison

Add the L2 cache controller DT node in SiFive FU540 soc-specific DT file

Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index afa43c7..812db02 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -19,6 +19,16 @@
 	chosen {
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		l2_lim: lim@0x8000000 {
+			reg = <0x0 0x8000000 0x0 0x2000000>;
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -54,6 +64,7 @@
 			reg = <1>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
+			next-level-cache = <&l2cache>;
 			cpu1_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
@@ -77,6 +88,7 @@
 			reg = <2>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
+			next-level-cache = <&l2cache>;
 			cpu2_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
@@ -100,6 +112,7 @@
 			reg = <3>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
+			next-level-cache = <&l2cache>;
 			cpu3_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
@@ -123,6 +136,7 @@
 			reg = <4>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
+			next-level-cache = <&l2cache>;
 			cpu4_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				compatible = "riscv,cpu-intc";
@@ -246,6 +260,18 @@
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
+		l2cache: cache-controller@2010000 {
+			compatible = "sifive,fu540-c000-ccache", "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <1024>;
+			cache-size = <2097152>;
+			cache-unified;
+			interrupt-parent = <&plic0>;
+			interrupts = <1 2 3>;
+			reg = <0x0 0x2010000 0x0 0x1000>;
+			memory-region = <&l2_lim>;
+		};
 
 	};
 };
-- 
2.7.4



^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2 cache way enabled
  2019-12-09 11:25 [PATCH 0/2] L2 ccache DT and cacheinfo support to read no. of L2 cache ways enabled Yash Shah
  2019-12-09 11:25 ` [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller Yash Shah
@ 2019-12-09 11:25 ` Yash Shah
  2019-12-14  2:12 ` Palmer Dabbelt
  2019-12-14  2:13 ` [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller Palmer Dabbelt
  3 siblings, 0 replies; 7+ messages in thread
From: Yash Shah @ 2019-12-09 11:25 UTC (permalink / raw)
  To: robh+dt, mark.rutland, paul.walmsley
  Cc: devicetree, aou, atish.patra, gregkh, linux-kernel,
	alexios.zavras, Yash Shah, palmer, tglx, bmeng.cn, linux-riscv,
	allison

In order to determine the number of L2 cache ways enabled at runtime,
implement a private attribute using cache_get_priv_group() in cacheinfo
framework. Reading this attribute ("number_of_ways_enabled") will return
the number of enabled L2 cache ways at runtime.

Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
 arch/riscv/include/asm/sifive_l2_cache.h |  2 ++
 arch/riscv/kernel/cacheinfo.c            | 31 +++++++++++++++++++++++++++++++
 drivers/soc/sifive/sifive_l2_cache.c     |  5 +++++
 3 files changed, 38 insertions(+)

diff --git a/arch/riscv/include/asm/sifive_l2_cache.h b/arch/riscv/include/asm/sifive_l2_cache.h
index 04f6748..217a42f 100644
--- a/arch/riscv/include/asm/sifive_l2_cache.h
+++ b/arch/riscv/include/asm/sifive_l2_cache.h
@@ -10,6 +10,8 @@
 extern int register_sifive_l2_error_notifier(struct notifier_block *nb);
 extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb);
 
+int sifive_l2_largest_wayenabled(void);
+
 #define SIFIVE_L2_ERR_TYPE_CE 0
 #define SIFIVE_L2_ERR_TYPE_UE 1
 
diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
index 4c90c07..29bdb21 100644
--- a/arch/riscv/kernel/cacheinfo.c
+++ b/arch/riscv/kernel/cacheinfo.c
@@ -7,6 +7,7 @@
 #include <linux/cpu.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <asm/sifive_l2_cache.h>
 
 static void ci_leaf_init(struct cacheinfo *this_leaf,
 			 struct device_node *node,
@@ -16,6 +17,36 @@ static void ci_leaf_init(struct cacheinfo *this_leaf,
 	this_leaf->type = type;
 }
 
+#ifdef CONFIG_SIFIVE_L2
+static ssize_t number_of_ways_enabled_show(struct device *dev,
+					   struct device_attribute *attr,
+					   char *buf)
+{
+	return sprintf(buf, "%u\n", sifive_l2_largest_wayenabled());
+}
+
+static DEVICE_ATTR_RO(number_of_ways_enabled);
+
+static struct attribute *priv_attrs[] = {
+	&dev_attr_number_of_ways_enabled.attr,
+	NULL,
+};
+
+static const struct attribute_group priv_attr_group = {
+	.attrs = priv_attrs,
+};
+
+const struct attribute_group *
+cache_get_priv_group(struct cacheinfo *this_leaf)
+{
+	/* We want to use private group for L2 cache only */
+	if (this_leaf->level == 2)
+		return &priv_attr_group;
+	else
+		return NULL;
+}
+#endif /* CONFIG_SIFIVE_L2 */
+
 static int __init_cache_level(unsigned int cpu)
 {
 	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
index a9ffff3..f1a5f2c 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -107,6 +107,11 @@ int unregister_sifive_l2_error_notifier(struct notifier_block *nb)
 }
 EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier);
 
+int sifive_l2_largest_wayenabled(void)
+{
+	return readl(l2_base + SIFIVE_L2_WAYENABLE);
+}
+
 static irqreturn_t l2_int_handler(int irq, void *device)
 {
 	unsigned int add_h, add_l;
-- 
2.7.4



^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2 cache way enabled
  2019-12-09 11:25 [PATCH 0/2] L2 ccache DT and cacheinfo support to read no. of L2 cache ways enabled Yash Shah
  2019-12-09 11:25 ` [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller Yash Shah
  2019-12-09 11:25 ` [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2 cache way enabled Yash Shah
@ 2019-12-14  2:12 ` Palmer Dabbelt
  2019-12-15 19:56   ` Paul Walmsley
  2019-12-23  8:53   ` Yash Shah
  2019-12-14  2:13 ` [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller Palmer Dabbelt
  3 siblings, 2 replies; 7+ messages in thread
From: Palmer Dabbelt @ 2019-12-14  2:12 UTC (permalink / raw)
  To: yash.shah
  Cc: mark.rutland, devicetree, aou, Atish Patra, Greg KH,
	linux-kernel, alexios.zavras, yash.shah, robh+dt, Paul Walmsley,
	tglx, bmeng.cn, linux-riscv, allison

On Mon, 09 Dec 2019 03:25:06 PST (-0800), yash.shah@sifive.com wrote:
> In order to determine the number of L2 cache ways enabled at runtime,
> implement a private attribute using cache_get_priv_group() in cacheinfo
> framework. Reading this attribute ("number_of_ways_enabled") will return
> the number of enabled L2 cache ways at runtime.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
>  arch/riscv/include/asm/sifive_l2_cache.h |  2 ++
>  arch/riscv/kernel/cacheinfo.c            | 31 +++++++++++++++++++++++++++++++
>  drivers/soc/sifive/sifive_l2_cache.c     |  5 +++++
>  3 files changed, 38 insertions(+)
>
> diff --git a/arch/riscv/include/asm/sifive_l2_cache.h b/arch/riscv/include/asm/sifive_l2_cache.h
> index 04f6748..217a42f 100644
> --- a/arch/riscv/include/asm/sifive_l2_cache.h
> +++ b/arch/riscv/include/asm/sifive_l2_cache.h
> @@ -10,6 +10,8 @@
>  extern int register_sifive_l2_error_notifier(struct notifier_block *nb);
>  extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb);
>
> +int sifive_l2_largest_wayenabled(void);

I thought the plan was to get this stuff out of arch/riscv?  It looks like it
only got half-way done.

> +
>  #define SIFIVE_L2_ERR_TYPE_CE 0
>  #define SIFIVE_L2_ERR_TYPE_UE 1
>
> diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
> index 4c90c07..29bdb21 100644
> --- a/arch/riscv/kernel/cacheinfo.c
> +++ b/arch/riscv/kernel/cacheinfo.c
> @@ -7,6 +7,7 @@
>  #include <linux/cpu.h>
>  #include <linux/of.h>
>  #include <linux/of_device.h>
> +#include <asm/sifive_l2_cache.h>
>
>  static void ci_leaf_init(struct cacheinfo *this_leaf,
>  			 struct device_node *node,
> @@ -16,6 +17,36 @@ static void ci_leaf_init(struct cacheinfo *this_leaf,
>  	this_leaf->type = type;
>  }
>
> +#ifdef CONFIG_SIFIVE_L2
> +static ssize_t number_of_ways_enabled_show(struct device *dev,
> +					   struct device_attribute *attr,
> +					   char *buf)
> +{
> +	return sprintf(buf, "%u\n", sifive_l2_largest_wayenabled());
> +}
> +
> +static DEVICE_ATTR_RO(number_of_ways_enabled);
> +
> +static struct attribute *priv_attrs[] = {
> +	&dev_attr_number_of_ways_enabled.attr,
> +	NULL,
> +};
> +
> +static const struct attribute_group priv_attr_group = {
> +	.attrs = priv_attrs,
> +};
> +
> +const struct attribute_group *
> +cache_get_priv_group(struct cacheinfo *this_leaf)
> +{
> +	/* We want to use private group for L2 cache only */
> +	if (this_leaf->level == 2)
> +		return &priv_attr_group;
> +	else
> +		return NULL;
> +}
> +#endif /* CONFIG_SIFIVE_L2 */
> +
>  static int __init_cache_level(unsigned int cpu)
>  {
>  	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
> diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
> index a9ffff3..f1a5f2c 100644
> --- a/drivers/soc/sifive/sifive_l2_cache.c
> +++ b/drivers/soc/sifive/sifive_l2_cache.c
> @@ -107,6 +107,11 @@ int unregister_sifive_l2_error_notifier(struct notifier_block *nb)
>  }
>  EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier);
>
> +int sifive_l2_largest_wayenabled(void)
> +{
> +	return readl(l2_base + SIFIVE_L2_WAYENABLE);
> +}
> +
>  static irqreturn_t l2_int_handler(int irq, void *device)
>  {
>  	unsigned int add_h, add_l;


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller
  2019-12-09 11:25 [PATCH 0/2] L2 ccache DT and cacheinfo support to read no. of L2 cache ways enabled Yash Shah
                   ` (2 preceding siblings ...)
  2019-12-14  2:12 ` Palmer Dabbelt
@ 2019-12-14  2:13 ` Palmer Dabbelt
  3 siblings, 0 replies; 7+ messages in thread
From: Palmer Dabbelt @ 2019-12-14  2:13 UTC (permalink / raw)
  To: yash.shah
  Cc: mark.rutland, devicetree, aou, Atish Patra, Greg KH,
	linux-kernel, alexios.zavras, yash.shah, robh+dt, Paul Walmsley,
	tglx, bmeng.cn, linux-riscv, allison

On Mon, 09 Dec 2019 03:25:05 PST (-0800), yash.shah@sifive.com wrote:
> Add the L2 cache controller DT node in SiFive FU540 soc-specific DT file
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
>  arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> index afa43c7..812db02 100644
> --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> @@ -19,6 +19,16 @@
>  	chosen {
>  	};
>
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		l2_lim: lim@0x8000000 {
> +			reg = <0x0 0x8000000 0x0 0x2000000>;
> +		};
> +	};
> +
>  	cpus {
>  		#address-cells = <1>;
>  		#size-cells = <0>;
> @@ -54,6 +64,7 @@
>  			reg = <1>;
>  			riscv,isa = "rv64imafdc";
>  			tlb-split;
> +			next-level-cache = <&l2cache>;
>  			cpu1_intc: interrupt-controller {
>  				#interrupt-cells = <1>;
>  				compatible = "riscv,cpu-intc";
> @@ -77,6 +88,7 @@
>  			reg = <2>;
>  			riscv,isa = "rv64imafdc";
>  			tlb-split;
> +			next-level-cache = <&l2cache>;
>  			cpu2_intc: interrupt-controller {
>  				#interrupt-cells = <1>;
>  				compatible = "riscv,cpu-intc";
> @@ -100,6 +112,7 @@
>  			reg = <3>;
>  			riscv,isa = "rv64imafdc";
>  			tlb-split;
> +			next-level-cache = <&l2cache>;
>  			cpu3_intc: interrupt-controller {
>  				#interrupt-cells = <1>;
>  				compatible = "riscv,cpu-intc";
> @@ -123,6 +136,7 @@
>  			reg = <4>;
>  			riscv,isa = "rv64imafdc";
>  			tlb-split;
> +			next-level-cache = <&l2cache>;
>  			cpu4_intc: interrupt-controller {
>  				#interrupt-cells = <1>;
>  				compatible = "riscv,cpu-intc";
> @@ -246,6 +260,18 @@
>  			#pwm-cells = <3>;
>  			status = "disabled";
>  		};
> +		l2cache: cache-controller@2010000 {
> +			compatible = "sifive,fu540-c000-ccache", "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-sets = <1024>;
> +			cache-size = <2097152>;
> +			cache-unified;
> +			interrupt-parent = <&plic0>;
> +			interrupts = <1 2 3>;
> +			reg = <0x0 0x2010000 0x0 0x1000>;
> +			memory-region = <&l2_lim>;
> +		};
>
>  	};
>  };

Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2 cache way enabled
  2019-12-14  2:12 ` Palmer Dabbelt
@ 2019-12-15 19:56   ` Paul Walmsley
  2019-12-23  8:53   ` Yash Shah
  1 sibling, 0 replies; 7+ messages in thread
From: Paul Walmsley @ 2019-12-15 19:56 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: mark.rutland, devicetree, aou, Atish Patra, Greg KH,
	linux-kernel, alexios.zavras, yash.shah, robh+dt, tglx, bmeng.cn,
	linux-riscv, allison

On Fri, 13 Dec 2019, Palmer Dabbelt wrote:

> I thought the plan was to get this stuff out of arch/riscv?  It looks like it
> only got half-way done.

That's still the plan.  Will probably send that one upstream in v5.5-rc.  

Am not a huge fan of moving it to drivers/soc, for a few different 
reasons, but some people seem to feel very passionately about it.


- Paul


^ permalink raw reply	[flat|nested] 7+ messages in thread

* RE: [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2 cache way enabled
  2019-12-14  2:12 ` Palmer Dabbelt
  2019-12-15 19:56   ` Paul Walmsley
@ 2019-12-23  8:53   ` Yash Shah
  1 sibling, 0 replies; 7+ messages in thread
From: Yash Shah @ 2019-12-23  8:53 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: mark.rutland, devicetree, aou, Atish Patra, Greg KH,
	linux-kernel, alexios.zavras, robh+dt, Paul Walmsley \( Sifive\),
	tglx, bmeng.cn, linux-riscv, allison

> -----Original Message-----
> From: Palmer Dabbelt <palmerdabbelt@google.com>
> Sent: 14 December 2019 07:43
> To: Yash Shah <yash.shah@sifive.com>
> Cc: robh+dt@kernel.org; mark.rutland@arm.com; Paul Walmsley ( Sifive)
> <paul.walmsley@sifive.com>; aou@eecs.berkeley.edu;
> bmeng.cn@gmail.com; allison@lohutok.net; alexios.zavras@intel.com; Atish
> Patra <Atish.Patra@wdc.com>; tglx@linutronix.de; Greg KH
> <gregkh@linuxfoundation.org>; devicetree@vger.kernel.org; linux-
> riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Yash Shah
> <yash.shah@sifive.com>
> Subject: Re: [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2
> cache way enabled
> 
> On Mon, 09 Dec 2019 03:25:06 PST (-0800), yash.shah@sifive.com wrote:
> > In order to determine the number of L2 cache ways enabled at runtime,
> > implement a private attribute using cache_get_priv_group() in
> > cacheinfo framework. Reading this attribute
> ("number_of_ways_enabled")
> > will return the number of enabled L2 cache ways at runtime.
> >
> > Signed-off-by: Yash Shah <yash.shah@sifive.com>
> > ---
> >  arch/riscv/include/asm/sifive_l2_cache.h |  2 ++
> >  arch/riscv/kernel/cacheinfo.c            | 31
> +++++++++++++++++++++++++++++++
> >  drivers/soc/sifive/sifive_l2_cache.c     |  5 +++++
> >  3 files changed, 38 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/sifive_l2_cache.h
> > b/arch/riscv/include/asm/sifive_l2_cache.h
> > index 04f6748..217a42f 100644
> > --- a/arch/riscv/include/asm/sifive_l2_cache.h
> > +++ b/arch/riscv/include/asm/sifive_l2_cache.h
> > @@ -10,6 +10,8 @@
> >  extern int register_sifive_l2_error_notifier(struct notifier_block
> > *nb);  extern int unregister_sifive_l2_error_notifier(struct
> > notifier_block *nb);
> >
> > +int sifive_l2_largest_wayenabled(void);
> 
> I thought the plan was to get this stuff out of arch/riscv?  It looks like it only
> got half-way done.

Are you suggesting to move this header file out of "/arch/riscv/include/asm/" to maybe "include/soc/sifive/"?

- Yash


^ permalink raw reply	[flat|nested] 7+ messages in thread

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Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2019-12-09 11:25 [PATCH 0/2] L2 ccache DT and cacheinfo support to read no. of L2 cache ways enabled Yash Shah
2019-12-09 11:25 ` [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller Yash Shah
2019-12-09 11:25 ` [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2 cache way enabled Yash Shah
2019-12-14  2:12 ` Palmer Dabbelt
2019-12-15 19:56   ` Paul Walmsley
2019-12-23  8:53   ` Yash Shah
2019-12-14  2:13 ` [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller Palmer Dabbelt

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