* [PATCH v3 0/2] cacheinfo support to read no. of L2 cache ways enabled
@ 2020-01-13 6:38 Yash Shah
2020-01-13 6:38 ` [PATCH v3 1/2] riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure Yash Shah
2020-01-13 6:38 ` [PATCH v3 2/2] riscv: Add support to determine no. of L2 cache way enabled Yash Shah
0 siblings, 2 replies; 6+ messages in thread
From: Yash Shah @ 2020-01-13 6:38 UTC (permalink / raw)
To: paul.walmsley, palmer
Cc: aou, sachin.ghadi, gregkh, linux-kernel, alexios.zavras,
Yash Shah, anup, tglx, bp, linux-riscv, allison
The patchset includes 2 patches. Patch 1 implements cache_get_priv_group
which make use of a generic ops structure to return a private attribute
group for custom cacheinfo. Patch 2 implements a private attribute named
"number_of_ways_enabled" in the cacheinfo framework. Reading this
attribute returns the number of L2 cache ways enabled at runtime,
This patchset is based on Linux v5.5-rc6 and tested on HiFive Unleashed
board.
v3 vs v2:
- As per Anup Patel's suggestion[0], implement a new approach which uses
generic ops structure. Hence addition of patch 1 to this series and
corresponding changes to patch 2.
- Dropped "riscv: dts: Add DT support for SiFive L2 cache controller"
patch since it is already merged
- Rebased on Linux v5.5-rc6
Changes in v2:
- Rebase the series on v5.5-rc3
- Remove the reserved-memory node from DT
[0]: https://lore.kernel.org/linux-riscv/CAAhSdy0CXde5s_ya=4YvmA4UQ5f5gLU-Z_FaOr8LPni+s_615Q@mail.gmail.com/
Yash Shah (2):
riscv: cacheinfo: Implement cache_get_priv_group with a generic ops
structure
riscv: Add support to determine no. of L2 cache way enabled
arch/riscv/include/asm/cacheinfo.h | 15 ++++++++++++++
arch/riscv/kernel/cacheinfo.c | 17 ++++++++++++++++
drivers/soc/sifive/sifive_l2_cache.c | 38 ++++++++++++++++++++++++++++++++++++
include/soc/sifive/sifive_l2_cache.h | 2 ++
4 files changed, 72 insertions(+)
create mode 100644 arch/riscv/include/asm/cacheinfo.h
--
2.7.4
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v3 1/2] riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure 2020-01-13 6:38 [PATCH v3 0/2] cacheinfo support to read no. of L2 cache ways enabled Yash Shah @ 2020-01-13 6:38 ` Yash Shah 2020-01-14 4:52 ` Anup Patel 2020-01-13 6:38 ` [PATCH v3 2/2] riscv: Add support to determine no. of L2 cache way enabled Yash Shah 1 sibling, 1 reply; 6+ messages in thread From: Yash Shah @ 2020-01-13 6:38 UTC (permalink / raw) To: paul.walmsley, palmer Cc: aou, sachin.ghadi, gregkh, linux-kernel, alexios.zavras, Yash Shah, anup, tglx, bp, linux-riscv, allison Implement cache_get_priv_group() that will make use of a generic ops structure to return a private attribute group for custom cache info. Using riscv_set_cacheinfo_ops() users can hook their own custom function to return the private attribute group for cacheinfo. In future we can add more ops to this generic ops structure for SOC specific cacheinfo. Signed-off-by: Yash Shah <yash.shah@sifive.com> --- arch/riscv/include/asm/cacheinfo.h | 15 +++++++++++++++ arch/riscv/kernel/cacheinfo.c | 17 +++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 arch/riscv/include/asm/cacheinfo.h diff --git a/arch/riscv/include/asm/cacheinfo.h b/arch/riscv/include/asm/cacheinfo.h new file mode 100644 index 0000000..5d9662e --- /dev/null +++ b/arch/riscv/include/asm/cacheinfo.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _ASM_RISCV_CACHEINFO_H +#define _ASM_RISCV_CACHEINFO_H + +#include <linux/cacheinfo.h> + +struct riscv_cacheinfo_ops { + const struct attribute_group * (*get_priv_group)(struct cacheinfo + *this_leaf); +}; + +void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops); + +#endif /* _ASM_RISCV_CACHEINFO_H */ diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c index 4c90c07..bd0f122 100644 --- a/arch/riscv/kernel/cacheinfo.c +++ b/arch/riscv/kernel/cacheinfo.c @@ -7,6 +7,23 @@ #include <linux/cpu.h> #include <linux/of.h> #include <linux/of_device.h> +#include <asm/cacheinfo.h> + +static struct riscv_cacheinfo_ops *rv_cache_ops; + +void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops) +{ + rv_cache_ops = ops; +} +EXPORT_SYMBOL_GPL(riscv_set_cacheinfo_ops); + +const struct attribute_group * +cache_get_priv_group(struct cacheinfo *this_leaf) +{ + if (rv_cache_ops && rv_cache_ops->get_priv_group) + return rv_cache_ops->get_priv_group(this_leaf); + return NULL; +} static void ci_leaf_init(struct cacheinfo *this_leaf, struct device_node *node, -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3 1/2] riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure 2020-01-13 6:38 ` [PATCH v3 1/2] riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure Yash Shah @ 2020-01-14 4:52 ` Anup Patel 0 siblings, 0 replies; 6+ messages in thread From: Anup Patel @ 2020-01-14 4:52 UTC (permalink / raw) To: Yash Shah Cc: Albert Ou, Sachin Ghadi, Greg Kroah-Hartman, linux-kernel@vger.kernel.org List, Alexios Zavras, Palmer Dabbelt, Paul Walmsley, Thomas Gleixner, bp, linux-riscv, Allison Randal On Mon, Jan 13, 2020 at 12:09 PM Yash Shah <yash.shah@sifive.com> wrote: > > Implement cache_get_priv_group() that will make use of a generic ops > structure to return a private attribute group for custom cache info. > > Using riscv_set_cacheinfo_ops() users can hook their own custom function > to return the private attribute group for cacheinfo. In future we can > add more ops to this generic ops structure for SOC specific cacheinfo. > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > --- > arch/riscv/include/asm/cacheinfo.h | 15 +++++++++++++++ > arch/riscv/kernel/cacheinfo.c | 17 +++++++++++++++++ > 2 files changed, 32 insertions(+) > create mode 100644 arch/riscv/include/asm/cacheinfo.h > > diff --git a/arch/riscv/include/asm/cacheinfo.h b/arch/riscv/include/asm/cacheinfo.h > new file mode 100644 > index 0000000..5d9662e > --- /dev/null > +++ b/arch/riscv/include/asm/cacheinfo.h > @@ -0,0 +1,15 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > + > +#ifndef _ASM_RISCV_CACHEINFO_H > +#define _ASM_RISCV_CACHEINFO_H > + > +#include <linux/cacheinfo.h> > + > +struct riscv_cacheinfo_ops { > + const struct attribute_group * (*get_priv_group)(struct cacheinfo > + *this_leaf); > +}; > + > +void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops); > + > +#endif /* _ASM_RISCV_CACHEINFO_H */ > diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c > index 4c90c07..bd0f122 100644 > --- a/arch/riscv/kernel/cacheinfo.c > +++ b/arch/riscv/kernel/cacheinfo.c > @@ -7,6 +7,23 @@ > #include <linux/cpu.h> > #include <linux/of.h> > #include <linux/of_device.h> > +#include <asm/cacheinfo.h> > + > +static struct riscv_cacheinfo_ops *rv_cache_ops; > + > +void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops) > +{ > + rv_cache_ops = ops; > +} > +EXPORT_SYMBOL_GPL(riscv_set_cacheinfo_ops); > + > +const struct attribute_group * > +cache_get_priv_group(struct cacheinfo *this_leaf) > +{ > + if (rv_cache_ops && rv_cache_ops->get_priv_group) > + return rv_cache_ops->get_priv_group(this_leaf); > + return NULL; > +} > > static void ci_leaf_init(struct cacheinfo *this_leaf, > struct device_node *node, > -- > 2.7.4 > LGTM. Reviewed-by: Anup Patel <anup@brainfault.org> Regards, Anup ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 2/2] riscv: Add support to determine no. of L2 cache way enabled 2020-01-13 6:38 [PATCH v3 0/2] cacheinfo support to read no. of L2 cache ways enabled Yash Shah 2020-01-13 6:38 ` [PATCH v3 1/2] riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure Yash Shah @ 2020-01-13 6:38 ` Yash Shah 2020-01-14 5:00 ` Anup Patel 1 sibling, 1 reply; 6+ messages in thread From: Yash Shah @ 2020-01-13 6:38 UTC (permalink / raw) To: paul.walmsley, palmer Cc: aou, sachin.ghadi, gregkh, linux-kernel, alexios.zavras, Yash Shah, anup, tglx, bp, linux-riscv, allison In order to determine the number of L2 cache ways enabled at runtime, implement a private attribute ("number_of_ways_enabled"). Reading this attribute returns the number of enabled L2 cache ways at runtime. Using riscv_set_cacheinfo_ops() hook a custom function, that returns this private attribute, to the generic ops structure which is used by cache_get_priv_group() in cacheinfo framework. Signed-off-by: Yash Shah <yash.shah@sifive.com> --- drivers/soc/sifive/sifive_l2_cache.c | 38 ++++++++++++++++++++++++++++++++++++ include/soc/sifive/sifive_l2_cache.h | 2 ++ 2 files changed, 40 insertions(+) diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c index a506939..8741885 100644 --- a/drivers/soc/sifive/sifive_l2_cache.c +++ b/drivers/soc/sifive/sifive_l2_cache.c @@ -9,6 +9,8 @@ #include <linux/interrupt.h> #include <linux/of_irq.h> #include <linux/of_address.h> +#include <linux/device.h> +#include <asm/cacheinfo.h> #include <soc/sifive/sifive_l2_cache.h> #define SIFIVE_L2_DIRECCFIX_LOW 0x100 @@ -31,6 +33,7 @@ static void __iomem *l2_base; static int g_irq[SIFIVE_L2_MAX_ECCINTR]; +static struct riscv_cacheinfo_ops l2_cache_ops; enum { DIR_CORR = 0, @@ -107,6 +110,38 @@ int unregister_sifive_l2_error_notifier(struct notifier_block *nb) } EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier); +int sifive_l2_largest_wayenabled(void) +{ + return readl(l2_base + SIFIVE_L2_WAYENABLE); +} + +static ssize_t number_of_ways_enabled_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%u\n", sifive_l2_largest_wayenabled()); +} + +static DEVICE_ATTR_RO(number_of_ways_enabled); + +static struct attribute *priv_attrs[] = { + &dev_attr_number_of_ways_enabled.attr, + NULL, +}; + +static const struct attribute_group priv_attr_group = { + .attrs = priv_attrs, +}; + +const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf) +{ + /* We want to use private group for L2 cache only */ + if (this_leaf->level == 2) + return &priv_attr_group; + else + return NULL; +} + static irqreturn_t l2_int_handler(int irq, void *device) { unsigned int add_h, add_l; @@ -170,6 +205,9 @@ static int __init sifive_l2_init(void) l2_config_read(); + l2_cache_ops.get_priv_group = l2_get_priv_group; + riscv_set_cacheinfo_ops(&l2_cache_ops); + #ifdef CONFIG_DEBUG_FS setup_sifive_debug(); #endif diff --git a/include/soc/sifive/sifive_l2_cache.h b/include/soc/sifive/sifive_l2_cache.h index 92ade10..55feff5 100644 --- a/include/soc/sifive/sifive_l2_cache.h +++ b/include/soc/sifive/sifive_l2_cache.h @@ -10,6 +10,8 @@ extern int register_sifive_l2_error_notifier(struct notifier_block *nb); extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb); +int sifive_l2_largest_wayenabled(void); + #define SIFIVE_L2_ERR_TYPE_CE 0 #define SIFIVE_L2_ERR_TYPE_UE 1 -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3 2/2] riscv: Add support to determine no. of L2 cache way enabled 2020-01-13 6:38 ` [PATCH v3 2/2] riscv: Add support to determine no. of L2 cache way enabled Yash Shah @ 2020-01-14 5:00 ` Anup Patel 2020-01-14 7:00 ` Yash Shah 0 siblings, 1 reply; 6+ messages in thread From: Anup Patel @ 2020-01-14 5:00 UTC (permalink / raw) To: Yash Shah Cc: Albert Ou, Sachin Ghadi, Greg Kroah-Hartman, linux-kernel@vger.kernel.org List, Alexios Zavras, Palmer Dabbelt, Paul Walmsley, Thomas Gleixner, bp, linux-riscv, Allison Randal On Mon, Jan 13, 2020 at 12:09 PM Yash Shah <yash.shah@sifive.com> wrote: > > In order to determine the number of L2 cache ways enabled at runtime, > implement a private attribute ("number_of_ways_enabled"). Reading this > attribute returns the number of enabled L2 cache ways at runtime. > > Using riscv_set_cacheinfo_ops() hook a custom function, that returns > this private attribute, to the generic ops structure which is used by > cache_get_priv_group() in cacheinfo framework. > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > --- > drivers/soc/sifive/sifive_l2_cache.c | 38 ++++++++++++++++++++++++++++++++++++ > include/soc/sifive/sifive_l2_cache.h | 2 ++ > 2 files changed, 40 insertions(+) > > diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c > index a506939..8741885 100644 > --- a/drivers/soc/sifive/sifive_l2_cache.c > +++ b/drivers/soc/sifive/sifive_l2_cache.c > @@ -9,6 +9,8 @@ > #include <linux/interrupt.h> > #include <linux/of_irq.h> > #include <linux/of_address.h> > +#include <linux/device.h> > +#include <asm/cacheinfo.h> > #include <soc/sifive/sifive_l2_cache.h> > > #define SIFIVE_L2_DIRECCFIX_LOW 0x100 > @@ -31,6 +33,7 @@ > > static void __iomem *l2_base; > static int g_irq[SIFIVE_L2_MAX_ECCINTR]; > +static struct riscv_cacheinfo_ops l2_cache_ops; > > enum { > DIR_CORR = 0, > @@ -107,6 +110,38 @@ int unregister_sifive_l2_error_notifier(struct notifier_block *nb) > } > EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier); > > +int sifive_l2_largest_wayenabled(void) > +{ > + return readl(l2_base + SIFIVE_L2_WAYENABLE); > +} The sifine_l2_largest_wayenabled() is not called from anywhere else so make it static and rename it to l2_largest_wayenabled(). > + > +static ssize_t number_of_ways_enabled_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + return sprintf(buf, "%u\n", sifive_l2_largest_wayenabled()); > +} > + > +static DEVICE_ATTR_RO(number_of_ways_enabled); > + > +static struct attribute *priv_attrs[] = { > + &dev_attr_number_of_ways_enabled.attr, > + NULL, > +}; > + > +static const struct attribute_group priv_attr_group = { > + .attrs = priv_attrs, > +}; > + > +const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf) > +{ > + /* We want to use private group for L2 cache only */ > + if (this_leaf->level == 2) > + return &priv_attr_group; > + else > + return NULL; > +} > + > static irqreturn_t l2_int_handler(int irq, void *device) > { > unsigned int add_h, add_l; > @@ -170,6 +205,9 @@ static int __init sifive_l2_init(void) > > l2_config_read(); > > + l2_cache_ops.get_priv_group = l2_get_priv_group; > + riscv_set_cacheinfo_ops(&l2_cache_ops); > + > #ifdef CONFIG_DEBUG_FS > setup_sifive_debug(); > #endif > diff --git a/include/soc/sifive/sifive_l2_cache.h b/include/soc/sifive/sifive_l2_cache.h > index 92ade10..55feff5 100644 > --- a/include/soc/sifive/sifive_l2_cache.h > +++ b/include/soc/sifive/sifive_l2_cache.h > @@ -10,6 +10,8 @@ > extern int register_sifive_l2_error_notifier(struct notifier_block *nb); > extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb); > > +int sifive_l2_largest_wayenabled(void); > + You can drop the sifive_l2_largest_wayenabled() declaration from here. > #define SIFIVE_L2_ERR_TYPE_CE 0 > #define SIFIVE_L2_ERR_TYPE_UE 1 > > -- > 2.7.4 > Apart from above it looks good. Reviewed-by: Anup Patel <anup@brainfault.org> Regards, Anup ^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v3 2/2] riscv: Add support to determine no. of L2 cache way enabled 2020-01-14 5:00 ` Anup Patel @ 2020-01-14 7:00 ` Yash Shah 0 siblings, 0 replies; 6+ messages in thread From: Yash Shah @ 2020-01-14 7:00 UTC (permalink / raw) To: Anup Patel Cc: Albert Ou, Sachin Ghadi, Greg Kroah-Hartman, linux-kernel@vger.kernel.org List, Alexios Zavras, Palmer Dabbelt, Paul Walmsley ( Sifive), Thomas Gleixner, bp, linux-riscv, Allison Randal > -----Original Message----- > From: Anup Patel <anup@brainfault.org> > Sent: 14 January 2020 10:30 > To: Yash Shah <yash.shah@sifive.com> > Cc: Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; Palmer Dabbelt > <palmer@dabbelt.com>; Albert Ou <aou@eecs.berkeley.edu>; Allison > Randal <allison@lohutok.net>; Alexios Zavras <alexios.zavras@intel.com>; > Greg Kroah-Hartman <gregkh@linuxfoundation.org>; Thomas Gleixner > <tglx@linutronix.de>; bp@suse.de; linux-riscv <linux- > riscv@lists.infradead.org>; linux-kernel@vger.kernel.org List <linux- > kernel@vger.kernel.org>; Sachin Ghadi <sachin.ghadi@sifive.com> > Subject: Re: [PATCH v3 2/2] riscv: Add support to determine no. of L2 cache > way enabled > > On Mon, Jan 13, 2020 at 12:09 PM Yash Shah <yash.shah@sifive.com> wrote: > > > > In order to determine the number of L2 cache ways enabled at runtime, > > implement a private attribute ("number_of_ways_enabled"). Reading this > > attribute returns the number of enabled L2 cache ways at runtime. > > > > Using riscv_set_cacheinfo_ops() hook a custom function, that returns > > this private attribute, to the generic ops structure which is used by > > cache_get_priv_group() in cacheinfo framework. > > > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > --- > > drivers/soc/sifive/sifive_l2_cache.c | 38 > > ++++++++++++++++++++++++++++++++++++ > > include/soc/sifive/sifive_l2_cache.h | 2 ++ > > 2 files changed, 40 insertions(+) > > > > diff --git a/drivers/soc/sifive/sifive_l2_cache.c > > b/drivers/soc/sifive/sifive_l2_cache.c > > index a506939..8741885 100644 > > --- a/drivers/soc/sifive/sifive_l2_cache.c > > +++ b/drivers/soc/sifive/sifive_l2_cache.c > > @@ -9,6 +9,8 @@ > > #include <linux/interrupt.h> > > #include <linux/of_irq.h> > > #include <linux/of_address.h> > > +#include <linux/device.h> > > +#include <asm/cacheinfo.h> > > #include <soc/sifive/sifive_l2_cache.h> > > > > #define SIFIVE_L2_DIRECCFIX_LOW 0x100 @@ -31,6 +33,7 @@ > > > > static void __iomem *l2_base; > > static int g_irq[SIFIVE_L2_MAX_ECCINTR]; > > +static struct riscv_cacheinfo_ops l2_cache_ops; > > > > enum { > > DIR_CORR = 0, > > @@ -107,6 +110,38 @@ int unregister_sifive_l2_error_notifier(struct > > notifier_block *nb) } > > EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier); > > > > +int sifive_l2_largest_wayenabled(void) > > +{ > > + return readl(l2_base + SIFIVE_L2_WAYENABLE); } > > The sifine_l2_largest_wayenabled() is not called from anywhere else so > make it static and rename it to l2_largest_wayenabled(). Sure will do that in v4 > > > + > > +static ssize_t number_of_ways_enabled_show(struct device *dev, > > + struct device_attribute *attr, > > + char *buf) { > > + return sprintf(buf, "%u\n", sifive_l2_largest_wayenabled()); } > > + > > +static DEVICE_ATTR_RO(number_of_ways_enabled); > > + > > +static struct attribute *priv_attrs[] = { > > + &dev_attr_number_of_ways_enabled.attr, > > + NULL, > > +}; > > + > > +static const struct attribute_group priv_attr_group = { > > + .attrs = priv_attrs, > > +}; > > + > > +const struct attribute_group *l2_get_priv_group(struct cacheinfo > > +*this_leaf) { > > + /* We want to use private group for L2 cache only */ > > + if (this_leaf->level == 2) > > + return &priv_attr_group; > > + else > > + return NULL; > > +} > > + > > static irqreturn_t l2_int_handler(int irq, void *device) { > > unsigned int add_h, add_l; > > @@ -170,6 +205,9 @@ static int __init sifive_l2_init(void) > > > > l2_config_read(); > > > > + l2_cache_ops.get_priv_group = l2_get_priv_group; > > + riscv_set_cacheinfo_ops(&l2_cache_ops); > > + > > #ifdef CONFIG_DEBUG_FS > > setup_sifive_debug(); > > #endif > > diff --git a/include/soc/sifive/sifive_l2_cache.h > > b/include/soc/sifive/sifive_l2_cache.h > > index 92ade10..55feff5 100644 > > --- a/include/soc/sifive/sifive_l2_cache.h > > +++ b/include/soc/sifive/sifive_l2_cache.h > > @@ -10,6 +10,8 @@ > > extern int register_sifive_l2_error_notifier(struct notifier_block > > *nb); extern int unregister_sifive_l2_error_notifier(struct > > notifier_block *nb); > > > > +int sifive_l2_largest_wayenabled(void); > > + > > You can drop the sifive_l2_largest_wayenabled() declaration from here. > > > #define SIFIVE_L2_ERR_TYPE_CE 0 > > #define SIFIVE_L2_ERR_TYPE_UE 1 > > > > -- > > 2.7.4 > > > > Apart from above it looks good. > > Reviewed-by: Anup Patel <anup@brainfault.org> Thanks. - Yash > > Regards, > Anup ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-01-14 7:00 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-01-13 6:38 [PATCH v3 0/2] cacheinfo support to read no. of L2 cache ways enabled Yash Shah 2020-01-13 6:38 ` [PATCH v3 1/2] riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure Yash Shah 2020-01-14 4:52 ` Anup Patel 2020-01-13 6:38 ` [PATCH v3 2/2] riscv: Add support to determine no. of L2 cache way enabled Yash Shah 2020-01-14 5:00 ` Anup Patel 2020-01-14 7:00 ` Yash Shah
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