From: Vincent Chen <vincent.chen@sifive.com>
To: paul.walmsley@sifive.com, palmer@dabbelt.com
Cc: Vincent Chen <vincent.chen@sifive.com>,
linux-riscv@lists.infradead.org, deanbo422@gmail.com
Subject: [PATCH V2 2/2] riscv: Change code model of module to medany to improve data accessing
Date: Fri, 21 Feb 2020 10:47:55 +0800 [thread overview]
Message-ID: <1582253275-28181-3-git-send-email-vincent.chen@sifive.com> (raw)
In-Reply-To: <1582253275-28181-1-git-send-email-vincent.chen@sifive.com>
All the loaded module locates in the region [&_end-2G,VMALLOC_END] at
runtime, so the distance from the module start to the end of the kernel
image does not exceed 2GB. Hence, the code model of the kernel module can
be changed to medany to improve the performance data access.
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
---
arch/riscv/Makefile | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 33a1d7cbf775..a6abe5847e42 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -13,8 +13,10 @@ LDFLAGS_vmlinux :=
ifeq ($(CONFIG_DYNAMIC_FTRACE),y)
LDFLAGS_vmlinux := --no-relax
endif
-KBUILD_AFLAGS_MODULE += -fPIC
-KBUILD_CFLAGS_MODULE += -fPIC
+
+ifeq ($(CONFIG_64BIT)$(CONFIG_CMODEL_MEDLOW),yy)
+KBUILD_CFLAGS_MODULE += -mcmodel=medany
+endif
export BITS
ifeq ($(CONFIG_ARCH_RV64I),y)
--
2.7.4
next prev parent reply other threads:[~2020-02-21 2:48 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-21 2:47 [PATCH 0/2] solve static percpu symbol issue in module and refine code model of module Vincent Chen
2020-02-21 2:47 ` [PATCH V2 1/2] riscv: avoid the PIC offset of static percpu data in module beyond 2G limits Vincent Chen
2020-02-21 2:47 ` Vincent Chen [this message]
2020-02-27 22:30 ` [PATCH 0/2] solve static percpu symbol issue in module and refine code model of module Palmer Dabbelt
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