From: Yash Shah <yash.shah@sifive.com>
To: paul.walmsley@sifive.com, palmer@dabbelt.com, robh+dt@kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, sachin.ghadi@sifive.com
Cc: aou@eecs.berkeley.edu, anup@brainfault.org,
lollivier@baylibre.com, green.wan@sifive.com,
atish.patra@wdc.com, Yash Shah <yash.shah@sifive.com>,
alistair.francis@wdc.com, deepa.kernel@gmail.com,
bmeng.cn@gmail.com
Subject: [PATCH 2/3] riscv: dts: fu540-c000: define hart clocks
Date: Tue, 16 Jun 2020 17:31:03 +0530 [thread overview]
Message-ID: <1592308864-30205-3-git-send-email-yash.shah@sifive.com> (raw)
In-Reply-To: <1592308864-30205-1-git-send-email-yash.shah@sifive.com>
Declare that each hart defined in the FU540 DT data is clocked by the
COREPLL. This is in preparation for enabling CPUFreq for the
FU540-C000 SoC on the HiFive Unleashed board.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 7db8610..735e102 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -30,6 +30,7 @@
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ clocks = <&prci PRCI_CLK_COREPLL>;
status = "disabled";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -55,6 +56,7 @@
riscv,isa = "rv64imafdc";
tlb-split;
next-level-cache = <&l2cache>;
+ clocks = <&prci PRCI_CLK_COREPLL>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -79,6 +81,7 @@
riscv,isa = "rv64imafdc";
tlb-split;
next-level-cache = <&l2cache>;
+ clocks = <&prci PRCI_CLK_COREPLL>;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -103,6 +106,7 @@
riscv,isa = "rv64imafdc";
tlb-split;
next-level-cache = <&l2cache>;
+ clocks = <&prci PRCI_CLK_COREPLL>;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -127,6 +131,7 @@
riscv,isa = "rv64imafdc";
tlb-split;
next-level-cache = <&l2cache>;
+ clocks = <&prci PRCI_CLK_COREPLL>;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
--
2.7.4
next prev parent reply other threads:[~2020-06-16 12:01 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-16 12:01 [PATCH 0/3] Dynamic CPU frequency switching for the HiFive Yash Shah
2020-06-16 12:01 ` [PATCH 1/3] riscv: defconfig, Kconfig: enable CPU power management Yash Shah
2020-06-16 12:01 ` Yash Shah [this message]
2021-06-16 3:16 ` [PATCH 2/3] riscv: dts: fu540-c000: define hart clocks Bin Meng
2021-06-16 15:13 ` David Abdurachmanov
2021-06-16 22:56 ` Bin Meng
2020-06-16 12:01 ` [PATCH 3/3] riscv: dts: HiFive Unleashed: define a default set of CPU OPPs Yash Shah
2020-06-29 9:30 ` [PATCH 0/3] Dynamic CPU frequency switching for the HiFive Greentime Hu
2020-07-01 10:40 ` Andreas Schwab
2020-07-01 12:04 ` David Abdurachmanov
2020-07-03 5:53 ` Yash Shah
2020-07-06 8:15 ` Andreas Schwab
2020-07-09 20:48 ` Palmer Dabbelt
2020-07-08 12:06 ` Yash Shah
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