From: Heiko Stuebner <heiko@sntech.de>
To: Guo Ren <guoren@kernel.org>
Cc: Anup Patel <anup@brainfault.org>,
Atish Patra <atish.patra@wdc.com>, Marc Zyngier <maz@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Palmer Dabbelt <palmer@dabbelt.com>,
Rob Herring <robh@kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
Guo Ren <guoren@linux.alibaba.com>,
Palmer Dabbelt <palmerdabbelt@google.com>
Subject: Re: [PATCH V4 2/3] dt-bindings: update riscv plic compatible string
Date: Sat, 16 Oct 2021 18:31:47 +0200 [thread overview]
Message-ID: <1708236.01x493v0YS@phil> (raw)
In-Reply-To: <CAJF2gTQKc1DGcCy_sFjSs8p+VMNGHFrjO2uLZrHnjdD1pZ2RZg@mail.gmail.com>
Am Samstag, 16. Oktober 2021, 14:56:51 CEST schrieb Guo Ren:
> On Sat, Oct 16, 2021 at 6:35 PM Heiko Stuebner <heiko@sntech.de> wrote:
> >
> > Hi Guo,
> >
> > Am Samstag, 16. Oktober 2021, 05:21:59 CEST schrieb guoren@kernel.org:
> > > From: Guo Ren <guoren@linux.alibaba.com>
> > >
> > > Add the compatible string "thead,c900-plic" to the riscv plic
> > > bindings to support allwinner d1 SOC which contains c906 core.
> >
> > The compatible strings sound good now, but some things below
> >
> > >
> > > Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> > > Cc: Rob Herring <robh@kernel.org>
> > > Cc: Palmer Dabbelt <palmerdabbelt@google.com>
> > > Cc: Anup Patel <anup@brainfault.org>
> > > Cc: Atish Patra <atish.patra@wdc.com>
> > >
> > > ---
> > >
> > > Changes since V4:
> > > - Update description in errata style
> > > - Update enum suggested by Anup, Heiko, Samuel
> > >
> > > Changes since V3:
> > > - Rename "c9xx" to "c900"
> > > - Add thead,c900-plic in the description section
> > > ---
> > > .../interrupt-controller/sifive,plic-1.0.0.yaml | 11 ++++++++++-
> > > 1 file changed, 10 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > > index 08d5a57ce00f..272f29540135 100644
> > > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > > @@ -35,6 +35,12 @@ description:
> > > contains a specific memory layout, which is documented in chapter 8 of the
> > > SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
> > >
> > > + The C9xx PLIC does not comply with the interrupt claim/completion process defined
> > > + by the RISC-V PLIC specification because C9xx PLIC will mask an IRQ when it is
> > > + claimed by PLIC driver (i.e. readl(claim) and the IRQ will be unmasked upon
> > > + completion by PLIC driver (i.e. writel(claim). This behaviour breaks the handling
> > > + of IRQS_ONESHOT by the generic handle_fasteoi_irq() used in the PLIC driver.
> > > +
> > > maintainers:
> > > - Sagar Kadam <sagar.kadam@sifive.com>
> > > - Paul Walmsley <paul.walmsley@sifive.com>
> > > @@ -46,7 +52,10 @@ properties:
> > > - enum:
> > > - sifive,fu540-c000-plic
> > > - canaan,k210-plic
> > > - - const: sifive,plic-1.0.0
> > > + - enmu:
> >
> > ^ spelling enum
> >
> > > + - sifive,plic-1.0.0
> > > + - thead,c900-plic
> > > + - allwinner,sun20i-d1-plic
> >
> > but in general I'd think that you want something like
> >
> > compatible:
> > oneOf:
> > - items:
> > - enum:
> > - sifive,fu540-c000-plic
> > - canaan,k210-plic
> > - const: sifive,plic-1.0.0
> > - items:
> > - enum:
> > - allwinner,sun20i-d1-plic
> > - const: thead,c900-plic
> >
> > Having only one item list would allow as valid combinations like
> > "sifive,fu540-c000-plic", "thead,c900-plic" when checking the schema.
> >
> > With the oneOf and separate lists we can make sure that such
> > "illegal" combinations get flagged by the dtbs_check
> >
> > [the enum with the single allwinner entry already leaves
> > room for later addition to the c900-plic variant]
> Thx, I'll fix it in the next version.
>
> another question: Is the allwinner_sun20i_d1_plic needed to IRQCHIP_DECLARE?
>
> +IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", thead_c900_plic_init);
> +IRQCHIP_DECLARE(allwinner_sun20i_d1_plic, "allwinner,sun20i-d1-plic",
> thead_c900_plic_init);
Doing
IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", thead_c900_plic_init);
should be enough for now.
Compatible-parsing happens from left to right, from most-specific to
most-generic. So having the allwinner-d1 compatible in there is sort of a
safeguard.
If at some _later point in time_ , some specific new quirk of the D1
implementation comes to light, we can _then_ just add a
IRQCHIP_DECLARE(allwinner_d1_plic, "allwinner,sun20i-d1-plic", allwinner_d1_plic_init);
Devicetrees should be stable and newer kernels should work with old
devicetrees, so having the soc-specific compatible in there just makes it
future proof :-)
Heiko
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-10-16 16:32 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-16 3:21 [PATCH V4 0/3] irqchip: riscv: Add thead,c900-plic support guoren
2021-10-16 3:21 ` [PATCH V4 1/3] irqchip/sifive-plic: " guoren
2021-10-18 5:17 ` Samuel Holland
2021-10-18 5:40 ` Anup Patel
2021-10-18 7:05 ` Guo Ren
2021-10-18 7:21 ` Marc Zyngier
2021-10-19 9:33 ` Guo Ren
2021-10-19 10:18 ` Marc Zyngier
2021-10-19 13:27 ` Guo Ren
2021-10-20 13:34 ` Marc Zyngier
2021-10-20 14:19 ` Guo Ren
2021-10-20 14:59 ` Darius Rad
2021-10-20 16:18 ` Anup Patel
2021-10-20 18:01 ` Darius Rad
2021-10-21 8:47 ` Anup Patel
2021-10-20 14:33 ` Anup Patel
2021-10-20 15:08 ` Marc Zyngier
2021-10-20 16:08 ` Anup Patel
2021-10-20 16:48 ` Marc Zyngier
2021-10-21 8:52 ` Anup Patel
2021-10-21 1:46 ` Guo Ren
2021-10-21 2:00 ` Guo Ren
2021-10-21 8:33 ` Marc Zyngier
2021-10-21 9:43 ` Guo Ren
2021-10-16 3:21 ` [PATCH V4 2/3] dt-bindings: update riscv plic compatible string guoren
2021-10-16 7:07 ` Andreas Schwab
2021-10-16 9:16 ` Guo Ren
2021-10-16 10:34 ` Heiko Stuebner
2021-10-16 12:56 ` Guo Ren
2021-10-16 16:31 ` Heiko Stuebner [this message]
2021-10-20 12:15 ` Guo Ren
2021-10-18 12:02 ` Rob Herring
2021-10-19 0:55 ` Guo Ren
2021-10-16 3:22 ` [PATCH V4 3/3] dt-bindings: vendor-prefixes: add T-Head Semiconductor guoren
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1708236.01x493v0YS@phil \
--to=heiko@sntech.de \
--cc=anup@brainfault.org \
--cc=atish.patra@wdc.com \
--cc=guoren@kernel.org \
--cc=guoren@linux.alibaba.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=maz@kernel.org \
--cc=palmer@dabbelt.com \
--cc=palmerdabbelt@google.com \
--cc=robh@kernel.org \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).