* RISC-V Open source Supervisor Binary Interface (OpenSBI) Version 0.1 Released
@ 2019-01-31 19:25 Atish Patra
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From: Atish Patra @ 2019-01-31 19:25 UTC (permalink / raw)
To: linux-riscv, U-Boot Mailing List, qemu-devel, sw-dev
Cc: Damien Le Moal, Palmer Dabbelt, olof.johansson,
David.Abdurachmanov, Anup Patel, Alexander Graf,
Christoph Hellwig, rminnich, Alistair Francis, paul.walmsley,
Jorge Campello De Souza, Bin Meng
OpenSBI version 0.1 is now publicly available in GitHub at
OpenSBI is an open source implementation of the RISC-V Supervisor Binary
Interface (SBI). RISC-V SBI specifications are maintained as an
independent project by the RISC-V Foundation in [Github].
This initial release of OpenSBI provides an implementation of the RISC-V
SBI specifications version 0.1. These specifications define the legacy
SBI interface currently in use by various products as well as by RISC-V
QEMU virtual machines.
OpenSBI also implements SBI compliant early boot firmwares capable of
handling various boot flows and payloads on various environments.
OpenSBI firmwares have been tested with payloads such as U-Boot and
Linux kernel, showing that these open firmwares can fully replace the
legacy non-standard BBL intermediate boot loader.
The platforms supported with this first release are as follows.
* Sifive HiFive Unleashed board
* RISC-V QEMU *virt* and *sifive_u* virtual machines
* Kendryte K210 SoC based boards.
OpenSBI implementation can be easily extended by RISC-V platform vendors
and System-on-Chip vendors to fit new hardware configurations.
As SBI specifications evolve and extend beyond the current base legacy
features, OpenSBI will be modified to provide a reference implementation
for new SBI specifications.
More information on OpenSBI capabilities as well as a contribution
guideline are available in OpenSBI documentation included with the
source code in GitHub.
linux-riscv mailing list
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2019-01-31 19:25 RISC-V Open source Supervisor Binary Interface (OpenSBI) Version 0.1 Released Atish Patra
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