From mboxrd@z Thu Jan 1 00:00:00 1970 From: paul.walmsley@sifive.com (Paul Walmsley) Date: Sat, 20 Oct 2018 06:38:21 -0700 Subject: [PATCH 0/3] clk: add driver for the SiFive FU540 PRCI and PLLs it controls Message-ID: <20181020133823.27103-1-paul.walmsley@sifive.com> To: linux-riscv@lists.infradead.org List-Id: linux-riscv.lists.infradead.org Add a driver for the SiFive FU540 PRCI IP block, which handles clock and some device reset control for the SiFive FU540 chip. Also add a driver- independent library for the Analog Bits Wide-Range PLL (WRPLL), used by the PRCI driver to monitor and control the WRPLL instances on the FU540 chip. It's been a long time since I've worked on Linux clock code, so Mike & Stephen, I'd appreciate a close look at the PRCI driver to make sure what it's doing makes sense. Boot-tested on a SiFive HiFive Unleashed board. COREPLL rate changes and notification were also tested on the same board. This patch series is also available at: https://github.com/sifive/riscv-linux/tree/dev/paulw/prci-v4.19-rc7 Paul Walmsley (3): clk: analogbits: add Wide-Range PLL library dt-bindings: clk: add documentation for the SiFive PRCI driver clk: sifive: add a driver for the SiFive FU540 PRCI IP block .../bindings/clock/sifive/fu540-prci.txt | 40 ++ MAINTAINERS | 6 + drivers/clk/Kconfig | 2 + drivers/clk/Makefile | 2 + drivers/clk/analogbits/Kconfig | 3 + drivers/clk/analogbits/Makefile | 2 + drivers/clk/analogbits/wrpll-cln28hpc.c | 387 +++++++++++ drivers/clk/sifive/Kconfig | 18 + drivers/clk/sifive/Makefile | 1 + drivers/clk/sifive/fu540-prci.c | 634 ++++++++++++++++++ include/linux/clk/analogbits-wrpll-cln28hpc.h | 99 +++ include/linux/clk/sifive-fu540-prci.h | 27 + 12 files changed, 1221 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt create mode 100644 drivers/clk/analogbits/Kconfig create mode 100644 drivers/clk/analogbits/Makefile create mode 100644 drivers/clk/analogbits/wrpll-cln28hpc.c create mode 100644 drivers/clk/sifive/Kconfig create mode 100644 drivers/clk/sifive/Makefile create mode 100644 drivers/clk/sifive/fu540-prci.c create mode 100644 include/linux/clk/analogbits-wrpll-cln28hpc.h create mode 100644 include/linux/clk/sifive-fu540-prci.h Cc: Michael Turquette Cc: Stephen Boyd Cc: Albert Ou Cc: Wesley W. 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Sat, 20 Oct 2018 06:38:37 -0700 (PDT) Received: from viisi.sifive.com ([37.152.39.96]) by smtp.gmail.com with ESMTPSA id f1-v6sm5227207wme.23.2018.10.20.06.38.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 20 Oct 2018 06:38:36 -0700 (PDT) From: Paul Walmsley To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 0/3] clk: add driver for the SiFive FU540 PRCI and PLLs it controls Date: Sat, 20 Oct 2018 06:38:21 -0700 Message-Id: <20181020133823.27103-1-paul.walmsley@sifive.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181020_063850_118468_C847B779 X-CRM114-Status: GOOD ( 13.33 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Albert Ou , Stephen Boyd , "Wesley W . Terpstra" , Michael Turquette , Palmer Dabbelt , linux-kernel@vger.kernel.org, Megan Wachs , Rob Herring , Paul Walmsley , linux-riscv@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org Message-ID: <20181020133821.dBiN1_WSe6Y9ZwuPYdRJUqgEDmaZKfSy0tk_yPKRg0I@z> Add a driver for the SiFive FU540 PRCI IP block, which handles clock and some device reset control for the SiFive FU540 chip. Also add a driver- independent library for the Analog Bits Wide-Range PLL (WRPLL), used by the PRCI driver to monitor and control the WRPLL instances on the FU540 chip. It's been a long time since I've worked on Linux clock code, so Mike & Stephen, I'd appreciate a close look at the PRCI driver to make sure what it's doing makes sense. Boot-tested on a SiFive HiFive Unleashed board. COREPLL rate changes and notification were also tested on the same board. This patch series is also available at: https://github.com/sifive/riscv-linux/tree/dev/paulw/prci-v4.19-rc7 Paul Walmsley (3): clk: analogbits: add Wide-Range PLL library dt-bindings: clk: add documentation for the SiFive PRCI driver clk: sifive: add a driver for the SiFive FU540 PRCI IP block .../bindings/clock/sifive/fu540-prci.txt | 40 ++ MAINTAINERS | 6 + drivers/clk/Kconfig | 2 + drivers/clk/Makefile | 2 + drivers/clk/analogbits/Kconfig | 3 + drivers/clk/analogbits/Makefile | 2 + drivers/clk/analogbits/wrpll-cln28hpc.c | 387 +++++++++++ drivers/clk/sifive/Kconfig | 18 + drivers/clk/sifive/Makefile | 1 + drivers/clk/sifive/fu540-prci.c | 634 ++++++++++++++++++ include/linux/clk/analogbits-wrpll-cln28hpc.h | 99 +++ include/linux/clk/sifive-fu540-prci.h | 27 + 12 files changed, 1221 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt create mode 100644 drivers/clk/analogbits/Kconfig create mode 100644 drivers/clk/analogbits/Makefile create mode 100644 drivers/clk/analogbits/wrpll-cln28hpc.c create mode 100644 drivers/clk/sifive/Kconfig create mode 100644 drivers/clk/sifive/Makefile create mode 100644 drivers/clk/sifive/fu540-prci.c create mode 100644 include/linux/clk/analogbits-wrpll-cln28hpc.h create mode 100644 include/linux/clk/sifive-fu540-prci.h Cc: Michael Turquette Cc: Stephen Boyd Cc: Albert Ou Cc: Wesley W. Terpstra Cc: Palmer Dabbelt Cc: Megan Wachs Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-clk@vger.kernel.org -- 2.19.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv