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08 Nov 2018 17:33:43 -0800 Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 08 Nov 2018 17:50:10 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [RFC 0/3] Unify CPU topology across ARM64 & RISC-V Date: Thu, 8 Nov 2018 17:50:06 -0800 Message-Id: <1541728209-3224-1-git-send-email-atish.patra@wdc.com> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181109_015024_559797_430A72B4 X-CRM114-Status: GOOD ( 14.82 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Damien.LeMoal@wdc.com, juri.lelli@arm.com, anup@brainfault.org, palmer@sifive.com, jeremy.linton@arm.com, atish.patra@wdc.com, robh+dt@kernel.org, sudeep.holla@arm.com, mick@ics.forth.gr, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org Message-ID: <20181109015006.mPKfMT5CmxYGJTd3NEbAWVgkrGxNndcUwbH7kc4rtHM@z> The cpu-map DT entry in ARM64 can describe the CPU topology in much better way compared to other existing approaches. RISC-V can easily adopt this binding to represent it's own CPU topology. Thus, both cpu-map DT binding and topology parsing code can be moved to a common location so that RISC-V or any other architecture can leverage that. The relevant discussion regarding unifying cpu topology can be found in [1]. arch_topology seems to be a perfect place to move the common code. I have not introduced any functional changes in the moved to code. The only downside in this approach is that the capacity code will be executed for RISC-V as well. But, it will exit immediately after not able to find the appropriate DT node. If the overhead is considered too much, we can always compile out capacity related functions under a different config for the architectures that do not support them. The patches have been tested for RISC-V and compile tested for ARM64. The socket changes[2] can be merged on top of this series or vice versa. [1] https://lkml.org/lkml/2018/11/6/19 [2] https://lkml.org/lkml/2018/11/7/918 Atish Patra (3): dt-binding: cpu-topology: Move cpu-map to a common binding. cpu-topology: Move cpu topology code to common code. RISC-V: Parse cpu topology during boot. Documentation/devicetree/bindings/arm/topology.txt | 475 ------------------- .../devicetree/bindings/cpu/cpu-topology.txt | 526 +++++++++++++++++++++ arch/arm64/include/asm/topology.h | 23 +- arch/arm64/kernel/topology.c | 305 +----------- arch/riscv/Kconfig | 1 + arch/riscv/kernel/smpboot.c | 6 +- drivers/base/arch_topology.c | 303 ++++++++++++ include/linux/arch_topology.h | 23 + include/linux/topology.h | 1 + 9 files changed, 864 insertions(+), 799 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/topology.txt create mode 100644 Documentation/devicetree/bindings/cpu/cpu-topology.txt -- 2.7.4 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv