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From: mhiramat@kernel.org (Masami Hiramatsu)
To: linux-riscv@lists.infradead.org
Subject: [RFC/RFT 2/2] RISC-V: kprobes/kretprobe support
Date: Wed, 14 Nov 2018 07:49:51 -0800
Message-ID: <20181114074951.0902699286fdf8652f2878a4@kernel.org> (raw)
In-Reply-To: <20181114003730.06f810517a270070734df4ce@kernel.org>

On Wed, 14 Nov 2018 00:37:30 -0800
Masami Hiramatsu <mhiramat@kernel.org> wrote:

> > +
> > +static int __kprobes patch_text(kprobe_opcode_t *addr, u32 opcode)
> > +{
> > +	if (is_compressed_insn(opcode))
> > +		*(u16 *)addr = cpu_to_le16(opcode);
> > +	else
> > +		*addr = cpu_to_le32(opcode);
> > +

BTW, don't RISC-V need any i-cache flush and per-core serialization
for patching the text area? (and no text_mutex protection?)

> > diff --git a/arch/riscv/kernel/probes/kprobes_trampoline.S b/arch/riscv/kernel/probes/kprobes_trampoline.S
> > new file mode 100644
> > index 000000000000..c7ceda9556a3
> > --- /dev/null
> > +++ b/arch/riscv/kernel/probes/kprobes_trampoline.S
> > @@ -0,0 +1,91 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +
> > +#include <linux/linkage.h>
> > +
> > +#include <asm/asm.h>
> > +#include <asm/asm-offsets.h>
> > +
> > +	.text
> > +	.altmacro
> > +
> > +	.macro save_all_base_regs
> > +	REG_S x1,  PT_RA(sp)
> > +	REG_S x3,  PT_GP(sp)
> > +	REG_S x4,  PT_TP(sp)
> > +	REG_S x5,  PT_T0(sp)
> > +	REG_S x6,  PT_T1(sp)
> > +	REG_S x7,  PT_T2(sp)
> > +	REG_S x8,  PT_S0(sp)
> > +	REG_S x9,  PT_S1(sp)
> > +	REG_S x10, PT_A0(sp)
> > +	REG_S x11, PT_A1(sp)
> > +	REG_S x12, PT_A2(sp)
> > +	REG_S x13, PT_A3(sp)
> > +	REG_S x14, PT_A4(sp)
> > +	REG_S x15, PT_A5(sp)
> > +	REG_S x16, PT_A6(sp)
> > +	REG_S x17, PT_A7(sp)
> > +	REG_S x18, PT_S2(sp)
> > +	REG_S x19, PT_S3(sp)
> > +	REG_S x20, PT_S4(sp)
> > +	REG_S x21, PT_S5(sp)
> > +	REG_S x22, PT_S6(sp)
> > +	REG_S x23, PT_S7(sp)
> > +	REG_S x24, PT_S8(sp)
> > +	REG_S x25, PT_S9(sp)
> > +	REG_S x26, PT_S10(sp)
> > +	REG_S x27, PT_S11(sp)
> > +	REG_S x28, PT_T3(sp)
> > +	REG_S x29, PT_T4(sp)
> > +	REG_S x30, PT_T5(sp)
> > +	REG_S x31, PT_T6(sp)
> > +	.endm
> > +
> > +	.macro restore_all_base_regs
> > +	REG_L x3,  PT_GP(sp)
> > +	REG_L x4,  PT_TP(sp)
> > +	REG_L x5,  PT_T0(sp)
> > +	REG_L x6,  PT_T1(sp)
> > +	REG_L x7,  PT_T2(sp)
> > +	REG_L x8,  PT_S0(sp)
> > +	REG_L x9,  PT_S1(sp)
> > +	REG_L x10, PT_A0(sp)
> > +	REG_L x11, PT_A1(sp)
> > +	REG_L x12, PT_A2(sp)
> > +	REG_L x13, PT_A3(sp)
> > +	REG_L x14, PT_A4(sp)
> > +	REG_L x15, PT_A5(sp)
> > +	REG_L x16, PT_A6(sp)
> > +	REG_L x17, PT_A7(sp)
> > +	REG_L x18, PT_S2(sp)
> > +	REG_L x19, PT_S3(sp)
> > +	REG_L x20, PT_S4(sp)
> > +	REG_L x21, PT_S5(sp)
> > +	REG_L x22, PT_S6(sp)
> > +	REG_L x23, PT_S7(sp)
> > +	REG_L x24, PT_S8(sp)
> > +	REG_L x25, PT_S9(sp)
> > +	REG_L x26, PT_S10(sp)
> > +	REG_L x27, PT_S11(sp)
> > +	REG_L x28, PT_T3(sp)
> > +	REG_L x29, PT_T4(sp)
> > +	REG_L x30, PT_T5(sp)
> > +	REG_L x31, PT_T6(sp)
> > +	.endm


It seems thses macros can be (partially?) shared with entry.S

Thank you,

-- 
Masami Hiramatsu <mhiramat@kernel.org>

From: Masami Hiramatsu <mhiramat@kernel.org>
To: Masami Hiramatsu <mhiramat@kernel.org>
Cc: "Patrick Stählin" <me@packi.ch>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Anders Roxell" <anders.roxell@linaro.org>,
	"Andrew Morton" <akpm@linux-foundation.org>,
	"Alan Kao" <alankao@andestech.com>,
	"Catalin Marinas" <catalin.marinas@arm.com>,
	"Palmer Dabbelt" <palmer@sifive.com>,
	"Will Deacon" <will.deacon@arm.com>,
	linux-kernel@vger.kernel.org, "Al Viro" <viro@zeniv.linux.org.uk>,
	"Souptick Joarder" <jrdr.linux@gmail.com>,
	"Zong Li" <zong@andestech.com>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Eric W. Biederman" <ebiederm@xmission.com>,
	linux-riscv@lists.infradead.org,
	"zhong jiang" <zhongjiang@huawei.com>,
	"Ingo Molnar" <mingo@kernel.org>,
	"Luc Van Oostenryck" <luc.vanoostenryck@gmail.com>,
	"Jim Wilson" <jimw@sifive.com>
Subject: Re: [RFC/RFT 2/2] RISC-V: kprobes/kretprobe support
Date: Wed, 14 Nov 2018 07:49:51 -0800
Message-ID: <20181114074951.0902699286fdf8652f2878a4@kernel.org> (raw)
Message-ID: <20181114154951.kNxX0Ag2FPeWuipiX83al49tHNgjvYBa03NedwH0qak@z> (raw)
In-Reply-To: <20181114003730.06f810517a270070734df4ce@kernel.org>

On Wed, 14 Nov 2018 00:37:30 -0800
Masami Hiramatsu <mhiramat@kernel.org> wrote:

> > +
> > +static int __kprobes patch_text(kprobe_opcode_t *addr, u32 opcode)
> > +{
> > +	if (is_compressed_insn(opcode))
> > +		*(u16 *)addr = cpu_to_le16(opcode);
> > +	else
> > +		*addr = cpu_to_le32(opcode);
> > +

BTW, don't RISC-V need any i-cache flush and per-core serialization
for patching the text area? (and no text_mutex protection?)

> > diff --git a/arch/riscv/kernel/probes/kprobes_trampoline.S b/arch/riscv/kernel/probes/kprobes_trampoline.S
> > new file mode 100644
> > index 000000000000..c7ceda9556a3
> > --- /dev/null
> > +++ b/arch/riscv/kernel/probes/kprobes_trampoline.S
> > @@ -0,0 +1,91 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +
> > +#include <linux/linkage.h>
> > +
> > +#include <asm/asm.h>
> > +#include <asm/asm-offsets.h>
> > +
> > +	.text
> > +	.altmacro
> > +
> > +	.macro save_all_base_regs
> > +	REG_S x1,  PT_RA(sp)
> > +	REG_S x3,  PT_GP(sp)
> > +	REG_S x4,  PT_TP(sp)
> > +	REG_S x5,  PT_T0(sp)
> > +	REG_S x6,  PT_T1(sp)
> > +	REG_S x7,  PT_T2(sp)
> > +	REG_S x8,  PT_S0(sp)
> > +	REG_S x9,  PT_S1(sp)
> > +	REG_S x10, PT_A0(sp)
> > +	REG_S x11, PT_A1(sp)
> > +	REG_S x12, PT_A2(sp)
> > +	REG_S x13, PT_A3(sp)
> > +	REG_S x14, PT_A4(sp)
> > +	REG_S x15, PT_A5(sp)
> > +	REG_S x16, PT_A6(sp)
> > +	REG_S x17, PT_A7(sp)
> > +	REG_S x18, PT_S2(sp)
> > +	REG_S x19, PT_S3(sp)
> > +	REG_S x20, PT_S4(sp)
> > +	REG_S x21, PT_S5(sp)
> > +	REG_S x22, PT_S6(sp)
> > +	REG_S x23, PT_S7(sp)
> > +	REG_S x24, PT_S8(sp)
> > +	REG_S x25, PT_S9(sp)
> > +	REG_S x26, PT_S10(sp)
> > +	REG_S x27, PT_S11(sp)
> > +	REG_S x28, PT_T3(sp)
> > +	REG_S x29, PT_T4(sp)
> > +	REG_S x30, PT_T5(sp)
> > +	REG_S x31, PT_T6(sp)
> > +	.endm
> > +
> > +	.macro restore_all_base_regs
> > +	REG_L x3,  PT_GP(sp)
> > +	REG_L x4,  PT_TP(sp)
> > +	REG_L x5,  PT_T0(sp)
> > +	REG_L x6,  PT_T1(sp)
> > +	REG_L x7,  PT_T2(sp)
> > +	REG_L x8,  PT_S0(sp)
> > +	REG_L x9,  PT_S1(sp)
> > +	REG_L x10, PT_A0(sp)
> > +	REG_L x11, PT_A1(sp)
> > +	REG_L x12, PT_A2(sp)
> > +	REG_L x13, PT_A3(sp)
> > +	REG_L x14, PT_A4(sp)
> > +	REG_L x15, PT_A5(sp)
> > +	REG_L x16, PT_A6(sp)
> > +	REG_L x17, PT_A7(sp)
> > +	REG_L x18, PT_S2(sp)
> > +	REG_L x19, PT_S3(sp)
> > +	REG_L x20, PT_S4(sp)
> > +	REG_L x21, PT_S5(sp)
> > +	REG_L x22, PT_S6(sp)
> > +	REG_L x23, PT_S7(sp)
> > +	REG_L x24, PT_S8(sp)
> > +	REG_L x25, PT_S9(sp)
> > +	REG_L x26, PT_S10(sp)
> > +	REG_L x27, PT_S11(sp)
> > +	REG_L x28, PT_T3(sp)
> > +	REG_L x29, PT_T4(sp)
> > +	REG_L x30, PT_T5(sp)
> > +	REG_L x31, PT_T6(sp)
> > +	.endm


It seems thses macros can be (partially?) shared with entry.S

Thank you,

-- 
Masami Hiramatsu <mhiramat@kernel.org>

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linux-riscv mailing list
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http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply index

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-13 19:58 [RFC/RFT 0/2] " me
2018-11-13 19:58 ` Patrick Stählin
2018-11-13 19:58 ` [RFC/RFT 1/2] RISC-V: Implement ptrace regs and stack API me
2018-11-13 19:58   ` Patrick Stählin
2018-11-13 19:58 ` [RFC/RFT 2/2] RISC-V: kprobes/kretprobe support me
2018-11-13 19:58   ` Patrick Stählin
2018-11-14  8:37   ` mhiramat
2018-11-14  8:37     ` Masami Hiramatsu
2018-11-14 15:49     ` mhiramat [this message]
2018-11-14 15:49       ` Masami Hiramatsu
2018-11-14 21:10       ` me
2018-11-14 21:10         ` Patrick Staehlin
2018-11-15  7:50         ` mhiramat
2018-11-15  7:50           ` Masami Hiramatsu
2018-11-14 20:52     ` me
2018-11-14 20:52       ` Patrick Staehlin
2018-11-15  8:41       ` mhiramat
2018-11-15  8:41         ` Masami Hiramatsu

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