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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id e81sm7036415oig.8.2018.12.11.18.21.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 11 Dec 2018 18:21:13 -0800 (PST) Date: Tue, 11 Dec 2018 20:21:12 -0600 From: Rob Herring To: Atish Patra Subject: Re: [RFT PATCH v1 2/4] dt-binding: cpu-topology: Move cpu-map to a common binding. Message-ID: <20181212022112.GA14213@bogus> References: <1543534100-3654-1-git-send-email-atish.patra@wdc.com> <1543534100-3654-3-git-send-email-atish.patra@wdc.com> <20181203165521.GB17883@e107155-lin> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181211_182125_344918_54658B37 X-CRM114-Status: GOOD ( 21.63 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , "devicetree@vger.kernel.org" , Albert Ou , Thomas Gleixner , Juri Lelli , Ard Biesheuvel , Dmitriy Cherkasov , Anup Patel , Sudeep Holla , Palmer Dabbelt , "linux-kernel@vger.kernel.org" , Jeremy Linton , Morten Rasmussen , "Peter Zijlstra \(Intel\)" , Greg Kroah-Hartman , Will Deacon , Catalin Marinas , "Rafael J. Wysocki" , "linux-riscv@lists.infradead.org" , Ingo Molnar , "moderated list:ARM64 PORT \(AARCH64 ARCHITECTURE\)" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Dec 03, 2018 at 09:23:42AM -0800, Atish Patra wrote: > On 12/3/18 8:55 AM, Sudeep Holla wrote: > > On Thu, Nov 29, 2018 at 03:28:18PM -0800, Atish Patra wrote: > > > cpu-map binding can be used to described cpu topology for both > > > RISC-V & ARM. It makes more sense to move the binding to document > > > to a common place. > > > > > > The relevant discussion can be found here. > > > https://lkml.org/lkml/2018/11/6/19 > > > > > > > Looks good to me apart from a minor query below in the example. > > > > Reviewed-by: Sudeep Holla > > > > > Signed-off-by: Atish Patra > > > --- > > > .../{arm/topology.txt => cpu/cpu-topology.txt} | 81 ++++++++++++++++++---- > > > 1 file changed, 67 insertions(+), 14 deletions(-) > > > rename Documentation/devicetree/bindings/{arm/topology.txt => cpu/cpu-topology.txt} (86%) > > > > > > diff --git a/Documentation/devicetree/bindings/arm/topology.txt b/Documentation/devicetree/bindings/cpu/cpu-topology.txt > > > similarity index 86% > > > rename from Documentation/devicetree/bindings/arm/topology.txt > > > rename to Documentation/devicetree/bindings/cpu/cpu-topology.txt > > > index 66848355..1de6fbce 100644 > > > --- a/Documentation/devicetree/bindings/arm/topology.txt > > > +++ b/Documentation/devicetree/bindings/cpu/cpu-topology.txt > > > > [...] > > > > > +Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system) > > > + > > > +cpus { > > > + #address-cells = <2>; > > > + #size-cells = <2>; > > > + compatible = "sifive,fu540g", "sifive,fu500"; > > > + model = "sifive,hifive-unleashed-a00"; > > > + > > > + ... > > > + > > > + cpu-map { > > > + cluster0 { > > > + core0 { > > > + cpu = <&L12>; > > > + }; > > > + core1 { > > > + cpu = <&L15>; > > > + }; > > > + core2 { > > > + cpu0 = <&L18>; > > > + }; > > > + core3 { > > > + cpu0 = <&L21>; > > > + }; > > > + }; > > > + }; > > > + > > > + L12: cpu@1 { > > > + device_type = "cpu"; > > > + compatible = "sifive,rocket0", "riscv"; > > > + reg = <0x1>; > > > + } > > > + > > > + L15: cpu@2 { > > > + device_type = "cpu"; > > > + compatible = "sifive,rocket0", "riscv"; > > > + reg = <0x2>; > > > + } > > > + L18: cpu@3 { > > > + device_type = "cpu"; > > > + compatible = "sifive,rocket0", "riscv"; > > > + reg = <0x3>; > > > + } > > > + L21: cpu@4 { > > > + device_type = "cpu"; > > > + compatible = "sifive,rocket0", "riscv"; > > > + reg = <0x4>; > > > + } > > > +}; > > > > The labels for the CPUs drew my attention. Is it intentionally random > > (or even specific) or just chosen to show anything can be used as labels ? > > SiFive generates the device tree from RTL directly. So I am not sure if they > assign random numbers or a particular algorithm chooses the label. I tried > to put the exact ones that is available publicly. > > https://github.com/riscv/riscv-device-tree-doc/blob/master/examples/sifive-hifive_unleashed-microsemi.dts Oh, that's really terrible. I wouldn't care as this was just source level stuff, but labels are part of the ABI with overlays. Rob _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv