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From: Christoph Hellwig <hch@infradead.org>
To: Anup Patel <anup@brainfault.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
	Jason Cooper <jason@lakedaemon.net>,
	Marc Zyngier <marc.zyngier@arm.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	linux-kernel@vger.kernel.org,
	Christoph Hellwig <hch@infradead.org>,
	Atish Patra <atish.patra@wdc.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Thomas Gleixner <tglx@linutronix.de>,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH v3 6/6] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host
Date: Mon, 17 Dec 2018 10:32:20 -0800
Message-ID: <20181217183220.GE7086@infradead.org> (raw)
In-Reply-To: <20181130080207.20505-7-anup@brainfault.org>

On Fri, Nov 30, 2018 at 01:32:07PM +0530, Anup Patel wrote:
> This patch provides irq_set_affinity() implementation for PLIC driver.
> It also updates irq_enable() such that PLIC interrupts are only enabled
> for one of CPUs specified in IRQ affinity mask.

But normally our affinity masks are that - masks of CPUs that can take
it.  It seems a bit odd to then just pick the first one, as this means
with default all-CPU masks we'll have all interrupts handled by the
first CPU only.


> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -106,14 +106,42 @@ static void plic_irq_toggle(const struct cpumask *mask, int hwirq, int enable)
>  
>  static void plic_irq_enable(struct irq_data *d)
>  {
> -	plic_irq_toggle(irq_data_get_affinity_mask(d), d->hwirq, 1);
> +	unsigned int cpu = cpumask_any_and(irq_data_get_affinity_mask(d),
> +					   cpu_online_mask);
> +	WARN_ON(cpu >= nr_cpu_ids);

I think this should be WARN_ON_ONCE and actually return instead of then
proceeding using the invalid cpu index. 

> +#ifdef CONFIG_SMP
static int plic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
> +			    bool force)
> +{
> +	unsigned int cpu;
> +
> +	if (!force)
> +		cpu = cpumask_any_and(mask_val, cpu_online_mask);
> +	else
> +		cpu = cpumask_first(mask_val);

maybe swap the two branches around to avoid the inversion of the force
flag?

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Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-30  8:02 [PATCH v3 0/6] IRQ affinity support in PLIC driver Anup Patel
2018-11-30  8:02 ` [PATCH v3 1/6] irqchip: sifive-plic: Pre-compute context hart base and enable base Anup Patel
2018-12-17 18:25   ` Christoph Hellwig
2018-12-18  8:30     ` Anup Patel
2018-11-30  8:02 ` [PATCH v3 2/6] irqchip: sifive-plic: Add struct plic_hw for global PLIC HW details Anup Patel
2018-12-17 18:24   ` Christoph Hellwig
2018-12-18  8:25     ` Anup Patel
2018-11-30  8:02 ` [PATCH v3 3/6] irqchip: sifive-plic: More flexible plic_irq_toggle() Anup Patel
2018-12-17 18:27   ` Christoph Hellwig
2018-12-18  8:50     ` Anup Patel
2018-12-19 16:28       ` Christoph Hellwig
2018-12-27  5:27         ` Anup Patel
2018-11-30  8:02 ` [PATCH v3 4/6] irqchip: sifive-plic: Add warning in plic_init() if handler already present Anup Patel
2018-12-17 18:28   ` Christoph Hellwig
2018-12-18  8:36     ` Anup Patel
2018-11-30  8:02 ` [PATCH v3 5/6] irqchip: sifive-plic: Differentiate between PLIC handler and context Anup Patel
2018-11-30  8:02 ` [PATCH v3 6/6] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host Anup Patel
2018-12-17 18:32   ` Christoph Hellwig [this message]
2018-12-18 10:32     ` Anup Patel
2018-12-17  9:37 ` [PATCH v3 0/6] IRQ affinity support in PLIC driver Anup Patel
2018-12-20 20:40   ` Palmer Dabbelt

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