From: Rob Herring <robh@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, Paul Walmsley <paul@pwsan.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@sifive.com>,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH 3/7] dt-bindings: riscv: cpus: add E51 cores to the list of documented CPUs
Date: Thu, 20 Dec 2018 15:01:41 -0600 [thread overview]
Message-ID: <20181220210141.GA17198@bogus> (raw)
In-Reply-To: <20181215052154.24347-4-paul.walmsley@sifive.com>
On Fri, Dec 14, 2018 at 09:21:50PM -0800, Paul Walmsley wrote:
> Add compatible strings for the SiFive E51 family of CPU cores to the
> RISC-V CPU compatible string documentation. The E51 CPU core is
> described in:
>
> https://static.dev.sifive.com/FU540-C000-v1.0.pdf
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> Cc: devicetree@vger.kernel.org
> Cc: linux-riscv@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.txt | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt
> index adf7b7af5dc3..fb9d4f86f41f 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.txt
> +++ b/Documentation/devicetree/bindings/riscv/cpus.txt
> @@ -68,8 +68,9 @@ described below.
> - compatible:
> Usage: required
> Value type: <stringlist>
> - Definition: must contain "riscv", may contain one of
> - "sifive,rocket0"
> + Definition: must contain "riscv", may contain one or
> + more of "sifive,rocket0", "sifive,e51",
> + "sifive,e5"
I can't really tell what are valid combinations from this. It reads that
I could list every string here and that would be valid. It is basically
'riscv' plus any other combinations of strings.
Rob
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next prev parent reply other threads:[~2018-12-20 21:02 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-15 5:21 [PATCH 0/7] arch: riscv: add DT file support, starting with the SiFive HiFive-U Paul Walmsley
2018-12-15 5:21 ` [PATCH 1/7] arch: riscv: add support for building DTB files from DT source data Paul Walmsley
2018-12-15 5:21 ` [PATCH 2/7] dt-bindings: riscv: sifive: add documentation for the SiFive FU540 Paul Walmsley
2018-12-20 20:57 ` Rob Herring
2018-12-15 5:21 ` [PATCH 3/7] dt-bindings: riscv: cpus: add E51 cores to the list of documented CPUs Paul Walmsley
2018-12-20 21:01 ` Rob Herring [this message]
2019-01-04 22:46 ` Palmer Dabbelt
2019-01-05 1:10 ` Rob Herring
2018-12-15 5:21 ` [PATCH 4/7] dt-bindings: riscv: cpus: add U54 " Paul Walmsley
2018-12-15 5:21 ` [PATCH 5/7] riscv: dts: add initial support for the SiFive FU540-C000 SoC Paul Walmsley
2018-12-16 3:12 ` kbuild test robot
2019-01-21 14:10 ` Johan Hovold
2018-12-15 5:21 ` [PATCH 6/7] dt-binding: riscv: sifive: add documentation for FU540-based boards Paul Walmsley
2018-12-20 21:04 ` Rob Herring
2018-12-15 5:21 ` [PATCH 7/7] riscv: dts: add initial board data for the SiFive HiFive Unleashed Paul Walmsley
2018-12-20 21:31 ` Rob Herring
2019-04-06 23:14 ` Paul Walmsley
2018-12-16 23:35 ` [PATCH 0/7] arch: riscv: add DT file support, starting with the SiFive HiFive-U Paul Walmsley
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