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From: Christoph Hellwig <hch@infradead.org>
To: "Björn Töpel" <bjorn.topel@gmail.com>
Cc: netdev@vger.kernel.org, linux-riscv@lists.infradead.org,
	palmer@sifive.com, daniel@iogearbox.net, davidlee@sifive.com
Subject: Re: [RFC PATCH 1/3] riscv: set HAVE_EFFICIENT_UNALIGNED_ACCESS
Date: Tue, 15 Jan 2019 07:39:31 -0800	[thread overview]
Message-ID: <20190115153931.GF26443@infradead.org> (raw)
In-Reply-To: <20190115083518.10149-2-bjorn.topel@gmail.com>

Hmm, while the RISC-V spec requires misaligned load/store support,
who says they are efficient?  Maybe add a little comment that says
on which cpus they are efficient.

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  reply	other threads:[~2019-01-15 15:40 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-15  8:35 [RFC PATCH 0/3] RV64G eBPF JIT Björn Töpel
2019-01-15  8:35 ` [RFC PATCH 1/3] riscv: set HAVE_EFFICIENT_UNALIGNED_ACCESS Björn Töpel
2019-01-15 15:39   ` Christoph Hellwig [this message]
2019-01-15 16:06     ` Björn Töpel
2019-01-25 20:21       ` Palmer Dabbelt
2019-01-26  1:33         ` Jim Wilson
2019-01-29  2:43           ` Palmer Dabbelt
2019-01-15  8:35 ` [RFC PATCH 2/3] riscv: add build infra for JIT compiler Björn Töpel
2019-01-15 15:43   ` Christoph Hellwig
2019-01-15 16:09     ` Björn Töpel
2019-01-15  8:35 ` [RFC PATCH 3/3] bpf, riscv: added eBPF JIT for RV64G Björn Töpel
2019-01-15 23:49   ` Daniel Borkmann
2019-01-16  7:23     ` Björn Töpel
2019-01-16 15:41       ` Daniel Borkmann
2019-01-16 19:06         ` Björn Töpel
2019-01-15 15:40 ` [RFC PATCH 0/3] RV64G eBPF JIT Christoph Hellwig
2019-01-15 16:03   ` Björn Töpel
2019-01-25 19:02     ` Palmer Dabbelt
2019-01-25 19:54 ` Paul Walmsley
2019-01-27 12:28   ` Björn Töpel
2019-01-30  2:02 ` Palmer Dabbelt

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