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Fri, 18 Jan 2019 21:56:39 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH v5 0/5] IRQ affinity support in PLIC driver Date: Sat, 19 Jan 2019 11:26:20 +0530 Message-Id: <20190119055625.100054-1-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190118_215641_991634_D12F9D43 X-CRM114-Status: GOOD ( 11.13 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christoph Hellwig , Atish Patra , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org This patchset primarily adds IRQ affinity support in PLIC driver and other improvements. It gives mechanism for explicitly route external interrupts to particular CPUs using smp_affinity attribute of each Linux IRQs. Also, we can now use IRQ balancer from kernel-space or user-space. The patchset is tested on QEMU virt machine. It is based on Linux-4.20 and can be found at riscv_plic_irq_affinity_v4 branch of: https://github.com/avpatel/linux.git Changes since v4: - Use "if (force)" instead of "if (!force)" in PATCH5 Changes since v3: - Dropped PATCH2 - Added PATCH to not inline plic_toggle() and plic_irq_toggle() - Moved PATCH3 changes to PATCH6 - Used WARN_ON_ONCE() instead of WARN_ON() in PATCH5 Changes since v2: - Fixed incorrect address of enable registers using sizeof(u32) in PATCH1 - Retained comment about need for locking in PATCH1 - Split PATCH2 into two patches - Split PATCH3 into two patches - Minor fix in commit description of PATCH4 Changes since v1: - Removed few whitspace changes from PATCH1 - Keep use of DEFINE_PER_CPU() as it is Anup Patel (5): irqchip: sifive-plic: Pre-compute context hart base and enable base irqchip: sifive-plic: Don't inline plic_toggle() and plic_irq_toggle() irqchip: sifive-plic: Add warning in plic_init() if handler already present irqchip: sifive-plic: Differentiate between PLIC handler and context irqchip: sifive-plic: Implement irq_set_affinity() for SMP host drivers/irqchip/irq-sifive-plic.c | 110 +++++++++++++++++++----------- 1 file changed, 71 insertions(+), 39 deletions(-) -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv