From: Anup Patel <anup@brainfault.org>
To: Palmer Dabbelt <palmer@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoph Hellwig <hch@infradead.org>,
Atish Patra <atish.patra@wdc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Anup Patel <anup@brainfault.org>
Subject: [PATCH v6 0/4] IRQ affinity support in PLIC driver
Date: Tue, 12 Feb 2019 18:22:42 +0530 [thread overview]
Message-ID: <20190212125246.69239-1-anup@brainfault.org> (raw)
This patchset primarily adds IRQ affinity support in PLIC driver and
other improvements.
It gives mechanism for explicitly route external interrupts to particular
CPUs using smp_affinity attribute of each Linux IRQs. Also, we can now
use IRQ balancer from kernel-space or user-space.
The patchset is tested on QEMU virt machine. It is based on Linux-5.0-rc6
and can be found at riscv_plic_irq_affinity_v6 branch of:
https://github.com/avpatel/linux.git
Changes since v5:
- Dropped PATCH2 based on discussion with Christoph
Changes since v4:
- Use "if (force)" instead of "if (!force)" in PATCH5
Changes since v3:
- Dropped PATCH2
- Added PATCH to not inline plic_toggle() and plic_irq_toggle()
- Moved PATCH3 changes to PATCH6
- Used WARN_ON_ONCE() instead of WARN_ON() in PATCH5
Changes since v2:
- Fixed incorrect address of enable registers using sizeof(u32) in PATCH1
- Retained comment about need for locking in PATCH1
- Split PATCH2 into two patches
- Split PATCH3 into two patches
- Minor fix in commit description of PATCH4
Changes since v1:
- Removed few whitspace changes from PATCH1
- Keep use of DEFINE_PER_CPU() as it is
Anup Patel (4):
irqchip: sifive-plic: Pre-compute context hart base and enable base
irqchip: sifive-plic: Add warning in plic_init() if handler already
present
irqchip: sifive-plic: Differentiate between PLIC handler and context
irqchip: sifive-plic: Implement irq_set_affinity() for SMP host
drivers/irqchip/irq-sifive-plic.c | 111 +++++++++++++++++++-----------
1 file changed, 72 insertions(+), 39 deletions(-)
--
2.17.1
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next reply other threads:[~2019-02-12 12:53 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-12 12:52 Anup Patel [this message]
2019-02-12 12:52 ` [PATCH v6 1/4] irqchip: sifive-plic: Pre-compute context hart base and enable base Anup Patel
2019-02-12 12:52 ` [PATCH v6 2/4] irqchip: sifive-plic: Add warning in plic_init() if handler already present Anup Patel
2019-02-12 12:52 ` [PATCH v6 3/4] irqchip: sifive-plic: Differentiate between PLIC handler and context Anup Patel
2019-02-12 12:52 ` [PATCH v6 4/4] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host Anup Patel
2019-02-14 12:33 ` [PATCH v6 0/4] IRQ affinity support in PLIC driver Marc Zyngier
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