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[217.229.29.45]) by smtp.gmail.com with ESMTPSA id b2sm12814914wrp.94.2019.02.13.04.37.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 13 Feb 2019 04:37:04 -0800 (PST) Date: Wed, 13 Feb 2019 13:37:03 +0100 From: Thierry Reding To: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= Subject: Re: [PATCH v5 2/2] pwm: sifive: Add a driver for SiFive SoC PWM Message-ID: <20190213123703.GE647@ulmo> References: <1548762199-7065-1-git-send-email-yash.shah@sifive.com> <1548762199-7065-3-git-send-email-yash.shah@sifive.com> <20190207101657.rfzcq6xdv6ocvubg@pengutronix.de> MIME-Version: 1.0 In-Reply-To: <20190207101657.rfzcq6xdv6ocvubg@pengutronix.de> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190213_043709_881044_923E6B71 X-CRM114-Status: GOOD ( 13.03 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, palmer@sifive.com, linux-kernel@vger.kernel.org, sachin.ghadi@sifive.com, Yash Shah , robh+dt@kernel.org, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org Content-Type: multipart/mixed; boundary="===============4424139838302361519==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org --===============4424139838302361519== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="zjcmjzIkjQU2rmur" Content-Disposition: inline --zjcmjzIkjQU2rmur Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Feb 07, 2019 at 11:16:57AM +0100, Uwe Kleine-K=C3=B6nig wrote: > On Tue, Jan 29, 2019 at 05:13:19PM +0530, Yash Shah wrote: [...] > > diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c [...] > > + writel(val, pwm->regs + PWM_SIFIVE_PWMCFG); > > + > > + writel(frac, pwm->regs + PWM_SIFIVE_PWMCMP0 + dev->hwpwm * SIZE_PWMCM= P); > > + > > + val &=3D ~(1 << PWM_SIFIVE_PWMCFG_DEGLITCH); > > + writel(val, pwm->regs + PWM_SIFIVE_PWMCFG); > > + > > + pwm_sifive_get_state(chip, dev, state); >=20 > Thierry: This changes the pwm_state. Is this how this should be done? Yes, I think that's fine. The PWM state should always reflect the current hardware state. If the configuration that we program does not reflect the state that was requested, that should be reflected in the PWM state. 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