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From: Atish Patra <atish.patra@wdc.com>
To: linux-kernel@vger.kernel.org
Cc: Christoph Hellwig <hch@infradead.org>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Thomas Gleixner <tglx@linutronix.de>,
	Kees Cook <keescook@chromium.org>,
	Changbin Du <changbin.du@intel.com>,
	Anup Patel <anup@brainfault.org>,
	Palmer Dabbelt <palmer@sifive.com>,
	"maintainer:X86 ARCHITECTURE 32-BIT AND 64-BIT" <x86@kernel.org>,
	linux-mm@kvack.org, Atish Patra <atish.patra@wdc.com>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	Vlastimil Babka <vbabka@suse.cz>, Gary Guo <gary@garyguo.net>,
	"H. Peter Anvin" <hpa@zytor.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	linux-riscv@lists.infradead.org,
	Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
Subject: [PATCH v2 2/3] RISC-V: Enable TLBFLUSH counters for debug kernel.
Date: Mon, 29 Apr 2019 12:57:58 -0700	[thread overview]
Message-ID: <20190429195759.18330-3-atish.patra@wdc.com> (raw)
In-Reply-To: <20190429195759.18330-1-atish.patra@wdc.com>

The TLB flush counters under vmstat seems to be very helpful while
debugging TLB flush performance in RISC-V.

Add the Kconfig option only for debug kernels.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
 arch/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index eb56c82d8aa1..c1ee876d1e7f 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -49,6 +49,7 @@ config RISCV
 	select GENERIC_IRQ_MULTI_HANDLER
 	select ARCH_HAS_PTE_SPECIAL
 	select HAVE_EBPF_JIT if 64BIT
+	select HAVE_ARCH_DEBUG_TLBFLUSH if DEBUG_KERNEL
 
 config MMU
 	def_bool y
-- 
2.21.0


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  parent reply	other threads:[~2019-04-29 19:58 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-29 19:57 [PATCH v2 0/3] TLB flush counters Atish Patra
2019-04-29 19:57 ` [PATCH v2 1/3] x86: Move DEBUG_TLBFLUSH option Atish Patra
2019-04-29 20:05   ` Ingo Molnar
2019-04-29 21:29     ` Atish Patra
2019-04-29 19:57 ` Atish Patra [this message]
2019-04-29 19:57 ` [PATCH v2 3/3] RISC-V: Update tlb flush counters Atish Patra

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