From: Christoph Hellwig <hch@lst.de> To: Palmer Dabbelt <palmer@sifive.com> Cc: linux-mm@kvack.org, Damien Le Moal <damien.lemoal@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, uclinux-dev@uclinux.org Subject: [PATCH 10/17] riscv: provide a flat entry loader Date: Tue, 11 Jun 2019 00:16:14 +0200 Message-ID: <20190610221621.10938-11-hch@lst.de> (raw) In-Reply-To: <20190610221621.10938-1-hch@lst.de> This allows just loading the kernel at a pre-set address without qemu going bonkers trying to map the ELF file. Signed-off-by: Christoph Hellwig <hch@lst.de> --- arch/riscv/Makefile | 13 +++++++++---- arch/riscv/boot/Makefile | 7 ++++++- arch/riscv/boot/loader.S | 8 ++++++++ arch/riscv/boot/loader.lds | 14 ++++++++++++++ 4 files changed, 37 insertions(+), 5 deletions(-) create mode 100644 arch/riscv/boot/loader.S create mode 100644 arch/riscv/boot/loader.lds diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 6b0741c9f348..69dbb6cb72f3 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -84,13 +84,18 @@ PHONY += vdso_install vdso_install: $(Q)$(MAKE) $(build)=arch/riscv/kernel/vdso $@ -all: Image.gz +ifeq ($(CONFIG_M_MODE),y) +KBUILD_IMAGE := $(boot)/loader +else +KBUILD_IMAGE := $(boot)/Image.gz +endif +BOOT_TARGETS := Image Image.gz loader -Image: vmlinux - $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ +all: $(notdir $(KBUILD_IMAGE)) -Image.%: Image +$(BOOT_TARGETS): vmlinux $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ + @$(kecho) ' Kernel: $(boot)/$@ is ready' zinstall install: $(Q)$(MAKE) $(build)=$(boot) $@ diff --git a/arch/riscv/boot/Makefile b/arch/riscv/boot/Makefile index 0990a9fdbe5d..32d2addeddba 100644 --- a/arch/riscv/boot/Makefile +++ b/arch/riscv/boot/Makefile @@ -16,7 +16,7 @@ OBJCOPYFLAGS_Image :=-O binary -R .note -R .note.gnu.build-id -R .comment -S -targets := Image +targets := Image loader $(obj)/Image: vmlinux FORCE $(call if_changed,objcopy) @@ -24,6 +24,11 @@ $(obj)/Image: vmlinux FORCE $(obj)/Image.gz: $(obj)/Image FORCE $(call if_changed,gzip) +loader.o: $(src)/loader.S $(obj)/Image + +$(obj)/loader: $(obj)/loader.o $(obj)/Image FORCE + $(Q)$(LD) -T $(src)/loader.lds -o $@ $(obj)/loader.o + install: $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ $(obj)/Image System.map "$(INSTALL_PATH)" diff --git a/arch/riscv/boot/loader.S b/arch/riscv/boot/loader.S new file mode 100644 index 000000000000..5586e2610dbb --- /dev/null +++ b/arch/riscv/boot/loader.S @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 + + .align 4 + .section .payload, "ax", %progbits + .globl _start +_start: + .incbin "arch/riscv/boot/Image" + diff --git a/arch/riscv/boot/loader.lds b/arch/riscv/boot/loader.lds new file mode 100644 index 000000000000..da9efd57bf44 --- /dev/null +++ b/arch/riscv/boot/loader.lds @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +OUTPUT_ARCH(riscv) +ENTRY(_start) + +SECTIONS +{ + . = 0x80000000; + + .payload : { + *(.payload) + . = ALIGN(8); + } +} -- 2.20.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply index Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-06-10 22:16 RISC-V nommu support Christoph Hellwig 2019-06-10 22:16 ` [PATCH 01/17] mm: provide a print_vma_addr stub for !CONFIG_MMU Christoph Hellwig 2019-06-11 10:11 ` Vladimir Murzin 2019-06-10 22:16 ` [PATCH 02/17] mm: stub out all of swapops.h " Christoph Hellwig 2019-06-11 10:15 ` Vladimir Murzin 2019-06-11 14:18 ` Christoph Hellwig 2019-06-11 14:36 ` Vladimir Murzin 2019-06-14 9:48 ` Christoph Hellwig 2019-06-10 22:16 ` [PATCH 03/17] mm/nommu: fix the MAP_UNINITIALIZED flag Christoph Hellwig 2019-06-11 10:19 ` Vladimir Murzin 2019-06-10 22:16 ` [PATCH 04/17] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig 2019-06-10 22:16 ` [PATCH 05/17] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm Christoph Hellwig 2019-06-10 22:16 ` [PATCH 06/17] riscv: clear the instruction cache and all registers when booting Christoph Hellwig 2019-06-10 22:16 ` [PATCH 07/17] riscv: refactor the IPI code Christoph Hellwig 2019-06-10 22:16 ` [PATCH 08/17] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig 2019-06-10 22:16 ` [PATCH 09/17] riscv: improve the default power off implementation Christoph Hellwig 2019-06-10 22:16 ` Christoph Hellwig [this message] 2019-06-10 22:16 ` [PATCH 11/17] riscv: read hart ID from mhartid on boot Christoph Hellwig 2019-06-10 22:16 ` [PATCH 12/17] riscv: provide native clint access for M-mode Christoph Hellwig 2019-06-10 22:16 ` [PATCH 13/17] riscv: implement remote sfence.i natively " Christoph Hellwig 2019-06-10 22:16 ` [PATCH 14/17] riscv: poison SBI calls " Christoph Hellwig 2019-06-10 22:16 ` [PATCH 15/17] riscv: don't allow selecting SBI-based drivers " Christoph Hellwig 2019-06-10 22:16 ` [PATCH 16/17] riscv: use the correct interrupt levels " Christoph Hellwig 2019-06-10 22:16 ` [PATCH 17/17] riscv: add nommu support Christoph Hellwig 2019-06-11 10:32 ` Vladimir Murzin 2019-06-11 12:44 ` David Hildenbrand
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