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From: Christoph Hellwig <hch@lst.de>
To: Palmer Dabbelt <palmer@sifive.com>
Cc: linux-mm@kvack.org, Damien Le Moal <damien.lemoal@wdc.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	uclinux-dev@uclinux.org
Subject: [PATCH 12/17] riscv: provide native clint access for M-mode
Date: Tue, 11 Jun 2019 00:16:16 +0200
Message-ID: <20190610221621.10938-13-hch@lst.de> (raw)
In-Reply-To: <20190610221621.10938-1-hch@lst.de>

RISC-V has the concept of a cpu level interrupt controller.  Part of it
is expose as bits in the status registers, and 2 new CSRs per privilege
level in the instruction set, but the machanisms to trigger IPIs and
timer events, as well as reading the actual timer value are not
specified in the RISC-V spec but usually delegated to a block of MMIO
registers.  This patch adds support for those MMIO registers in the
timer and IPI code.  For now only the SiFive layout also supported by
a few other implementations is supported, but the code should be
easily extensible to others in the future.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/riscv/include/asm/clint.h    | 17 +++++++++++
 arch/riscv/include/asm/timex.h    | 22 ++++++++++++++
 arch/riscv/kernel/Makefile        |  1 +
 arch/riscv/kernel/clint.c         | 50 +++++++++++++++++++++++++++++++
 arch/riscv/kernel/setup.c         |  2 ++
 arch/riscv/kernel/smp.c           | 24 +++++++++++++++
 arch/riscv/kernel/smpboot.c       |  3 ++
 drivers/clocksource/timer-riscv.c | 11 ++++++-
 8 files changed, 129 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/include/asm/clint.h
 create mode 100644 arch/riscv/kernel/clint.c

diff --git a/arch/riscv/include/asm/clint.h b/arch/riscv/include/asm/clint.h
new file mode 100644
index 000000000000..77559d07db33
--- /dev/null
+++ b/arch/riscv/include/asm/clint.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+#ifndef _ASM_CLINT_H
+#define _ASM_CLINT_H 1
+
+#ifdef CONFIG_M_MODE
+extern u32 __iomem *clint_ipi_base;
+extern u64 __iomem *clint_time_val;
+extern u64 __iomem *clint_time_cmp;
+
+void clint_init_one(void);
+void clint_init_boot_cpu(void);
+#else
+#define clint_init_one()	do { } while (0)
+#define clint_init_boot_cpu()	do { } while (0)
+#endif /* CONFIG_M_MODE */
+
+#endif /* _ASM_CLINT_H */
diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h
index 6a703ec9d796..2a95adf8bba0 100644
--- a/arch/riscv/include/asm/timex.h
+++ b/arch/riscv/include/asm/timex.h
@@ -10,6 +10,27 @@
 
 typedef unsigned long cycles_t;
 
+#ifdef CONFIG_M_MODE
+
+#include <linux/io-64-nonatomic-lo-hi.h>
+#include <asm/clint.h>
+
+static inline uint64_t get_cycles64(void)
+{
+	return readq_relaxed(clint_time_val);
+}
+
+#ifdef CONFIG_64BIT
+#define get_cycles	get_cycles64
+#else
+static inline cycles_t get_cycles(void)
+{
+	return readl_relaxed(clint_time_val);
+}
+#define get_cycles	get_cycles
+#endif /* CONFIG_64BIT */
+
+#else /* CONFIG_M_MODE */
 static inline cycles_t get_cycles_inline(void)
 {
 	cycles_t n;
@@ -40,6 +61,7 @@ static inline uint64_t get_cycles64(void)
 	return ((u64)hi << 32) | lo;
 }
 #endif
+#endif /* CONFIG_M_MODE */
 
 #define ARCH_HAS_READ_CURRENT_TIMER
 
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index 2420d37d96de..f933c04f89db 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -29,6 +29,7 @@ obj-y	+= vdso.o
 obj-y	+= cacheinfo.o
 obj-y	+= vdso/
 
+obj-$(CONFIG_M_MODE)		+= clint.o
 obj-$(CONFIG_FPU)		+= fpu.o
 obj-$(CONFIG_SMP)		+= smpboot.o
 obj-$(CONFIG_SMP)		+= smp.o
diff --git a/arch/riscv/kernel/clint.c b/arch/riscv/kernel/clint.c
new file mode 100644
index 000000000000..a1089ccab9e3
--- /dev/null
+++ b/arch/riscv/kernel/clint.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 Christoph Hellwig.
+ */
+
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/types.h>
+#include <asm/csr.h>
+#include <asm/irq.h>
+#include <asm/timex.h>
+
+/*
+ * This is the layout used by the SiFive clint, which is also shared by the qemu
+ * virt platform, and the Kendryte KD210 at least.
+ */
+#define CLINT_IPI_OFF		0
+#define CLINT_TIME_VAL_OFF	0xbff8
+#define CLINT_TIME_CMP_OFF	0x4000;
+
+u32 __iomem *clint_ipi_base;
+u64 __iomem *clint_time_val;
+u64 __iomem *clint_time_cmp;
+
+void clint_init_one(void)
+{
+	writel(0, clint_ipi_base + csr_read(mhartid));
+}
+
+void clint_init_boot_cpu(void)
+{
+	struct device_node *np;
+	void __iomem *base;
+
+	np = of_find_compatible_node(NULL, NULL, "riscv,clint0");
+	if (!np) {
+		panic("clint not found");
+		return;
+	}
+
+	base = of_iomap(np, 0);
+	if (!base)
+		panic("could not map CLINT");
+
+	clint_ipi_base = base + CLINT_IPI_OFF;
+	clint_time_val = base + CLINT_TIME_VAL_OFF;
+	clint_time_cmp = base + CLINT_TIME_CMP_OFF;
+
+	clint_init_one();
+}
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index b92e6831d1ec..2892d82f474c 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -17,6 +17,7 @@
 #include <linux/sched/task.h>
 #include <linux/swiotlb.h>
 
+#include <asm/clint.h>
 #include <asm/setup.h>
 #include <asm/sections.h>
 #include <asm/pgtable.h>
@@ -67,6 +68,7 @@ void __init setup_arch(char **cmdline_p)
 	setup_bootmem();
 	paging_init();
 	unflatten_device_tree();
+	clint_init_boot_cpu();
 
 #ifdef CONFIG_SWIOTLB
 	swiotlb_init(1);
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index 91164204496c..e498a5e1615c 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -24,7 +24,9 @@
 #include <linux/sched.h>
 #include <linux/seq_file.h>
 #include <linux/delay.h>
+#include <linux/io.h>
 
+#include <asm/clint.h>
 #include <asm/sbi.h>
 #include <asm/tlbflush.h>
 #include <asm/cacheflush.h>
@@ -89,6 +91,27 @@ static void ipi_stop(void)
 		wait_for_interrupt();
 }
 
+#ifdef CONFIG_M_MODE
+static inline void send_ipi_single(int cpu, enum ipi_message_type op)
+{
+	set_bit(op, &ipi_data[cpu].bits);
+	writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu));
+}
+
+static inline void send_ipi_mask(const struct cpumask *mask,
+		enum ipi_message_type op)
+{
+	int cpu;
+
+	for_each_cpu(cpu, mask)
+		send_ipi_single(cpu, op);
+}
+
+static inline void clear_ipi(void)
+{
+	writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id()));
+}
+#else /* CONFIG_M_MODE */
 static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op)
 {
 	int cpuid, hartid;
@@ -114,6 +137,7 @@ static inline void clear_ipi(void)
 {
 	csr_clear(CSR_SIP, SIE_SSIE);
 }
+#endif /* CONFIG_M_MODE */
 
 void riscv_software_interrupt(void)
 {
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 7462a44304fe..5737c8e9c97d 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -23,6 +23,7 @@
 #include <linux/of.h>
 #include <linux/sched/task_stack.h>
 #include <linux/sched/mm.h>
+#include <asm/clint.h>
 #include <asm/irq.h>
 #include <asm/mmu_context.h>
 #include <asm/tlbflush.h>
@@ -132,6 +133,8 @@ asmlinkage void __init smp_callin(void)
 {
 	struct mm_struct *mm = &init_mm;
 
+	clint_init_one();
+
 	/* All kernel threads share the same mm context.  */
 	mmgrab(mm);
 	current->active_mm = mm;
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index 2e2d363faabf..281915c3e6f2 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -24,7 +24,15 @@
  * operations on the current hart.  There is guaranteed to be exactly one timer
  * per hart on all RISC-V systems.
  */
-
+#ifdef CONFIG_M_MODE
+static int riscv_clock_next_event(unsigned long delta,
+		struct clock_event_device *ce)
+{
+	csr_set(CSR_XIE, XIE_XTIE);
+	writeq(get_cycles64() + delta, clint_time_cmp + csr_read(mhartid));
+	return 0;
+}
+#else
 static int riscv_clock_next_event(unsigned long delta,
 		struct clock_event_device *ce)
 {
@@ -32,6 +40,7 @@ static int riscv_clock_next_event(unsigned long delta,
 	sbi_set_timer(get_cycles64() + delta);
 	return 0;
 }
+#endif /* #ifdef CONFIG_M_MODE */
 
 static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
 	.name			= "riscv_timer_clockevent",
-- 
2.20.1


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  parent reply index

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-10 22:16 RISC-V nommu support Christoph Hellwig
2019-06-10 22:16 ` [PATCH 01/17] mm: provide a print_vma_addr stub for !CONFIG_MMU Christoph Hellwig
2019-06-11 10:11   ` Vladimir Murzin
2019-06-10 22:16 ` [PATCH 02/17] mm: stub out all of swapops.h " Christoph Hellwig
2019-06-11 10:15   ` Vladimir Murzin
2019-06-11 14:18     ` Christoph Hellwig
2019-06-11 14:36       ` Vladimir Murzin
2019-06-14  9:48         ` Christoph Hellwig
2019-06-10 22:16 ` [PATCH 03/17] mm/nommu: fix the MAP_UNINITIALIZED flag Christoph Hellwig
2019-06-11 10:19   ` Vladimir Murzin
2019-06-10 22:16 ` [PATCH 04/17] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig
2019-06-10 22:16 ` [PATCH 05/17] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm Christoph Hellwig
2019-06-10 22:16 ` [PATCH 06/17] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-06-10 22:16 ` [PATCH 07/17] riscv: refactor the IPI code Christoph Hellwig
2019-06-10 22:16 ` [PATCH 08/17] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-06-10 22:16 ` [PATCH 09/17] riscv: improve the default power off implementation Christoph Hellwig
2019-06-10 22:16 ` [PATCH 10/17] riscv: provide a flat entry loader Christoph Hellwig
2019-06-10 22:16 ` [PATCH 11/17] riscv: read hart ID from mhartid on boot Christoph Hellwig
2019-06-10 22:16 ` Christoph Hellwig [this message]
2019-06-10 22:16 ` [PATCH 13/17] riscv: implement remote sfence.i natively for M-mode Christoph Hellwig
2019-06-10 22:16 ` [PATCH 14/17] riscv: poison SBI calls " Christoph Hellwig
2019-06-10 22:16 ` [PATCH 15/17] riscv: don't allow selecting SBI-based drivers " Christoph Hellwig
2019-06-10 22:16 ` [PATCH 16/17] riscv: use the correct interrupt levels " Christoph Hellwig
2019-06-10 22:16 ` [PATCH 17/17] riscv: add nommu support Christoph Hellwig
2019-06-11 10:32   ` Vladimir Murzin
2019-06-11 12:44   ` David Hildenbrand

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