From: Christoph Hellwig <hch@lst.de> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com> Cc: linux-mm@kvack.org, Damien Le Moal <Damien.LeMoal@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/17] riscv: read the hart ID from mhartid on boot Date: Mon, 24 Jun 2019 07:43:04 +0200 Message-ID: <20190624054311.30256-11-hch@lst.de> (raw) In-Reply-To: <20190624054311.30256-1-hch@lst.de> From: Damien Le Moal <Damien.LeMoal@wdc.com> When in M-Mode, we can use the mhartid CSR to get the ID of the running HART. Doing so, direct M-Mode boot without firmware is possible. Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Signed-off-by: Christoph Hellwig <hch@lst.de> --- arch/riscv/kernel/head.S | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index e5fa5481aa99..a4c170e41a34 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -18,6 +18,14 @@ ENTRY(_start) csrw CSR_XIE, zero csrw CSR_XIP, zero +#ifdef CONFIG_M_MODE + /* + * The hartid in a0 is expected later on, and we have no firmware + * to hand it to us. + */ + csrr a0, mhartid +#endif + /* Load the global pointer */ .option push .option norelax -- 2.20.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply index Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-06-24 5:42 RISC-V nommu support v2 Christoph Hellwig 2019-06-24 5:42 ` [PATCH 01/17] mm: provide a print_vma_addr stub for !CONFIG_MMU Christoph Hellwig 2019-06-24 5:42 ` [PATCH 02/17] mm: stub out all of swapops.h " Christoph Hellwig 2019-06-24 5:42 ` [PATCH 03/17] mm/nommu: fix the MAP_UNINITIALIZED flag Christoph Hellwig 2019-06-24 5:42 ` [PATCH 04/17] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig 2019-06-24 5:42 ` [PATCH 05/17] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm Christoph Hellwig 2019-07-01 18:53 ` Atish Patra 2019-06-24 5:43 ` [PATCH 06/17] riscv: refactor the IPI code Christoph Hellwig 2019-06-24 5:43 ` [PATCH 07/17] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig 2019-07-01 18:37 ` Atish Patra 2019-06-24 5:43 ` [PATCH 08/17] riscv: improve the default power off implementation Christoph Hellwig 2019-07-01 21:07 ` Atish Patra 2019-06-24 5:43 ` [PATCH 09/17] riscv: provide a flat entry loader Christoph Hellwig 2019-06-24 5:43 ` Christoph Hellwig [this message] 2019-07-01 21:15 ` [PATCH 10/17] riscv: read the hart ID from mhartid on boot Atish Patra 2019-06-24 5:43 ` [PATCH 11/17] riscv: provide native clint access for M-mode Christoph Hellwig 2019-06-24 5:43 ` [PATCH 12/17] riscv: implement remote sfence.i natively " Christoph Hellwig 2019-06-24 5:43 ` [PATCH 13/17] riscv: poison SBI calls " Christoph Hellwig 2019-06-24 5:43 ` [PATCH 14/17] riscv: don't allow selecting SBI-based drivers " Christoph Hellwig 2019-06-24 5:43 ` [PATCH 15/17] riscv: use the correct interrupt levels " Christoph Hellwig 2019-06-24 5:43 ` [PATCH 16/17] riscv: clear the instruction cache and all registers when booting Christoph Hellwig 2019-07-01 21:26 ` Atish Patra 2019-07-08 8:26 ` Palmer Dabbelt 2019-08-13 15:40 ` Christoph Hellwig 2019-08-13 15:37 ` hch 2019-06-24 5:43 ` [PATCH 17/17] riscv: add nommu support Christoph Hellwig 2019-07-12 14:52 ` Vladimir Murzin 2019-06-24 11:47 ` RISC-V nommu support v2 Vladimir Murzin 2019-06-24 11:54 ` Christoph Hellwig 2019-06-24 13:08 ` Vladimir Murzin 2019-06-24 13:16 ` Christoph Hellwig 2019-06-25 7:31 ` Palmer Dabbelt 2019-06-25 12:37 ` Vladimir Murzin 2019-07-01 6:56 ` Christoph Hellwig 2019-07-01 16:06 ` Paul Walmsley
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