From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23AAFC76188 for ; Mon, 22 Jul 2019 08:18:53 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ECE1921E70 for ; Mon, 22 Jul 2019 08:18:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="kJnypPPf" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ECE1921E70 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=C+Gm+Rod2pUvJZYx2BiNlKhv3sZHzpdnRFD/l8dq/YA=; b=kJnypPPfMUyrEK A03hWpidD98D7NQJN5gxYam3hAqtLHwoW08PsYCxmijUAtannVlK/lFriiKlH3185VcQeNvLhK/Dc oYor6L+WMvRnxI1Gqq6kGi6kRgN+/x/KIaeXSWGx4g4I/Be+Me8QZifjdZDWfieHn14J1/ABzy54K cVr+oI8wotWVtDhXHyjdRcvT8YA7JRNvqrni2hIzKXsfq325ssUheyf56UPZpdHCBJAmy7LRYP2Gd RrQkSgJ70DJ09OZ6uZYfCaFzOuIMQMQiM3Tmc40LCIwlAeR8TwHKAUhaXeQp2U5h8SIfY52kvh2HP CxNa7XkejP+QTtxpsFfQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hpTWy-0007gb-LX; Mon, 22 Jul 2019 08:18:48 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hpTWu-0007fu-4t for linux-riscv@lists.infradead.org; Mon, 22 Jul 2019 08:18:47 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 614A3344; Mon, 22 Jul 2019 01:18:40 -0700 (PDT) Received: from blommer (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5DE3A3F71F; Mon, 22 Jul 2019 01:18:36 -0700 (PDT) Date: Mon, 22 Jul 2019 09:18:30 +0100 From: Mark Rutland To: Bin Meng Subject: Re: [PATCH] riscv: dts: fu540-c000: Add "status" property to cpu node Message-ID: <20190722081157.rojxwc6qrsplpduo@salmiak> References: <1562298766-25066-1-git-send-email-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.11.1+11 (2f07cb52) (2018-12-01) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190722_011844_249054_22C80DEF X-CRM114-Status: GOOD ( 13.19 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree , Albert Ou , Anup Patel , Yash Shah , Rob Herring , Palmer Dabbelt , Paul Walmsley , linux-riscv Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Jul 05, 2019 at 01:11:01PM +0800, Bin Meng wrote: > On Fri, Jul 5, 2019 at 11:59 AM Anup Patel wrote: > > > > > > > > > -----Original Message----- > > > From: linux-riscv On Behalf Of Bin > > > Meng > > > Sent: Friday, July 5, 2019 9:23 AM > > > To: linux-riscv ; devicetree > > > ; Rob Herring ; Mark > > > Rutland ; Albert Ou ; > > > Paul Walmsley ; Palmer Dabbelt > > > ; Yash Shah > > > Subject: [PATCH] riscv: dts: fu540-c000: Add "status" property to cpu node > > > > > > Per device tree spec, the "status" property property shall be present for > > > nodes representing CPUs in a SMP configuration. This property is currently > > > missing in cpu 1/2/3/4 node in the fu540-c000.dtsi. > > > > We don't need explicit "status = okay" for SOC internal devices > > (such as PLIC, INTC, etc) which are always enabled by default. > > > > Yes, that's fine because those device bindings do not require them. > > > Absence of "status" DT prop is treated as enabled by default. > > > > But per current device tree spec, "status" in cpu node is mandatory. > (spec uses "shall"). Missing it is a spec violation. I think this is a spec bug (or at least misleading wording in the spec). IEEE 1275 says (for status as a generic property): The absence of this property menas that the operational status is unknown or okay. ... and I think it's fine to treat that the same as an explicit "okay" here, as we do generically in Linux. Thanks, Mark. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv