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26 Jul 2019 12:46:47 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [PATCH 2/4] RISC-V: Add riscv_isa reprensenting ISA features common across CPUs Date: Fri, 26 Jul 2019 12:46:36 -0700 Message-Id: <20190726194638.8068-2-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190726194638.8068-1-atish.patra@wdc.com> References: <20190726194638.8068-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190726_124655_202197_12B52E15 X-CRM114-Status: GOOD ( 13.66 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Albert Ou , Alan Kao , Greg Kroah-Hartman , Daniel Lezcano , Johan Hovold , Atish Patra , Anup Patel , Palmer Dabbelt , Paul Walmsley , linux-riscv@lists.infradead.org, Thomas Gleixner , Allison Randal Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org From: Anup Patel This patch adds riscv_isa integer to represent ISA features common across all CPUs. The riscv_isa is not same as elf_hwcap because elf_hwcap will only have ISA features relevant for user-space apps whereas riscv_isa will have ISA features relevant to both kernel and user-space apps. One of the use case is KVM hypervisor where riscv_isa will be used to do following operations: 1. Check whether hypervisor extension is available 2. Find ISA features that need to be virtualized (e.g. floating point support, vector extension, etc.) Signed-off-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/hwcap.h | 25 ++++++++++++++++++++++ arch/riscv/kernel/cpufeature.c | 39 +++++++++++++++++++++++++++++++--- 2 files changed, 61 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 7ecb7c6a57b1..e069f60ad5d2 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -22,5 +22,30 @@ enum { }; extern unsigned long elf_hwcap; + +#define RISCV_ISA_EXT_A (1UL << ('A' - 'A')) +#define RISCV_ISA_EXT_a RISCV_ISA_EXT_A +#define RISCV_ISA_EXT_C (1UL << ('C' - 'A')) +#define RISCV_ISA_EXT_c RISCV_ISA_EXT_C +#define RISCV_ISA_EXT_D (1UL << ('D' - 'A')) +#define RISCV_ISA_EXT_d RISCV_ISA_EXT_D +#define RISCV_ISA_EXT_F (1UL << ('F' - 'A')) +#define RISCV_ISA_EXT_f RISCV_ISA_EXT_F +#define RISCV_ISA_EXT_H (1UL << ('H' - 'A')) +#define RISCV_ISA_EXT_h RISCV_ISA_EXT_H +#define RISCV_ISA_EXT_I (1UL << ('I' - 'A')) +#define RISCV_ISA_EXT_i RISCV_ISA_EXT_I +#define RISCV_ISA_EXT_M (1UL << ('M' - 'A')) +#define RISCV_ISA_EXT_m RISCV_ISA_EXT_M +#define RISCV_ISA_EXT_S (1UL << ('S' - 'A')) +#define RISCV_ISA_EXT_s RISCV_ISA_EXT_S +#define RISCV_ISA_EXT_U (1UL << ('U' - 'A')) +#define RISCV_ISA_EXT_u RISCV_ISA_EXT_U + +extern unsigned long riscv_isa; + +#define riscv_isa_extension_available(ext_char) \ + (riscv_isa & RISCV_ISA_EXT_##ext_char) + #endif #endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b1ade9a49347..d76c806b4fc9 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -12,6 +12,7 @@ #include unsigned long elf_hwcap __read_mostly; +unsigned long riscv_isa __read_mostly; #ifdef CONFIG_FPU bool has_fpu __read_mostly; #endif @@ -20,7 +21,8 @@ void riscv_fill_hwcap(void) { struct device_node *node; const char *isa; - size_t i; + char print_str[BITS_PER_LONG+1]; + size_t i, j, isa_len; static unsigned long isa2hwcap[256] = {0}; isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I; @@ -31,9 +33,11 @@ void riscv_fill_hwcap(void) isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C; elf_hwcap = 0; + riscv_isa = 0; for_each_of_cpu_node(node) { unsigned long this_hwcap = 0; + unsigned long this_isa = 0; if (riscv_of_processor_hartid(node) < 0) continue; @@ -43,8 +47,22 @@ void riscv_fill_hwcap(void) continue; } - for (i = 0; i < strlen(isa); ++i) + i = 0; + isa_len = strlen(isa); +#if defined(CONFIG_32BIT) + if (strncasecmp(isa, "rv32", 4) != 0) + i += 4; +#elif defined(CONFIG_64BIT) + if (strncasecmp(isa, "rv64", 4) != 0) + i += 4; +#endif + for (; i < isa_len; ++i) { this_hwcap |= isa2hwcap[(unsigned char)(isa[i])]; + if ('a' <= isa[i] && isa[i] <= 'z') + this_isa |= (1UL << (isa[i] - 'a')); + if ('A' <= isa[i] && isa[i] <= 'Z') + this_isa |= (1UL << (isa[i] - 'A')); + } /* * All "okay" hart should have same isa. Set HWCAP based on @@ -55,6 +73,11 @@ void riscv_fill_hwcap(void) elf_hwcap &= this_hwcap; else elf_hwcap = this_hwcap; + + if (riscv_isa) + riscv_isa &= this_isa; + else + riscv_isa = this_isa; } /* We don't support systems with F but without D, so mask those out @@ -64,7 +87,17 @@ void riscv_fill_hwcap(void) elf_hwcap &= ~COMPAT_HWCAP_ISA_F; } - pr_info("elf_hwcap is 0x%lx\n", elf_hwcap); + memset(print_str, 0, sizeof(print_str)); + for (i = 0, j = 0; i < BITS_PER_LONG; i++) + if (riscv_isa & (1UL << i)) + print_str[j++] = (char)('A' + i); + pr_info("riscv: ISA extensions %s\n", print_str); + + memset(print_str, 0, sizeof(print_str)); + for (i = 0, j = 0; i < BITS_PER_LONG; i++) + if (elf_hwcap & (1UL << i)) + print_str[j++] = (char)('A' + i); + pr_info("riscv: ELF capabilities %s\n", print_str); #ifdef CONFIG_FPU if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) -- 2.21.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv