From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D71D6C433FF for ; Wed, 7 Aug 2019 12:29:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AA82621E6C for ; Wed, 7 Aug 2019 12:29:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="fF0Urt7H"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=wdc.com header.i=@wdc.com header.b="qRxifE56"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="fM0YkRuj" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AA82621E6C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ofZjD+ZTPAdt8zw34Tg5MFIgPvCwwkPLvhgtc7AOm2w=; b=fF0Urt7Hgw0FhK Bd55SZbAey2SqY4LEVzqwwkS5Fzpmv1Jw8pex8b1RQlMPqW15GH7jccq1KblEZ5+5uhilef+Yjvu+ 8lDhlzvujUCJi7aFN1hiNGtjnxC44gxepNEVhEBaHqhbI07ZPdGxz4LEoV8NtmnoN+GChksk4C38u VcWatDJyMzKXilBO6z5c6CHmt6QGH59nTPxpr9YD0o3YuaHNJiIAxL1AMxLfz40f3G+o0lPw2I1Fi 6xiymMLTq1pLAAEdHokkX1gjYWI6wi/Pg6rik9Emv7O56SY8ybYwyR81trSsPjo/vMkwO2uwFf/Au rpuczsYZZzikj/xxv2Sw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hvL4K-0005dn-M3; Wed, 07 Aug 2019 12:29:28 +0000 Received: from esa3.hgst.iphmx.com ([216.71.153.141]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hvL4H-0005Wh-3D for linux-riscv@lists.infradead.org; Wed, 07 Aug 2019 12:29:27 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1565180965; x=1596716965; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=/XOUQWD16sqYtuaYetjo1zRdyVnVF6zL50+E7Lajg1k=; b=qRxifE56sVFRz9LIoiwXMzbKHl3KULrP7Alv1ItGVk470z720+VJYyJY HTvh1L6GCvQbVYoUA9CpSgLYtkJkLTZoZD2I7iOqaOBdEpJUe45gRcqFf ah2JvCAExVfad6SuAcsRWqYbMXXaeuuNQcMOBV5yGRONMIw85z8Efsmxo hSVeJJxSBDxgnmcRNXAKLmwyHJRcSORKPKGq2oGf31aOwpmveNk16VX1M EJaqcIrki8lRNkXnfo12TkIj7zDp3111YTm5MRMnbZWIDalGlERUA9YD3 XvdOE2NlCy8grqbnxeMedFZwz8n72GyYd3ubzL8x4oA+HXRwnjm/O+uis A==; IronPort-SDR: Zx7vPbVXYaKFo8NhG/hVP0x52JHVllUsvdf5zF5MwBvmRwapLmzOE/jaTcKGUMA4Phjf4ZTz6U UJuVtlaTt1wybFu0aBq1beqIK7DbPVATxTm9+m5i5G+C6AzOOuTIPfQuPJPVAWgxuP/Iox1Us3 uGYIPlqv63tMbwAPvVLyDsZeR8Gp2rNrRsiIXErD8PfVHPwF/wUVcJ/NRathNFTY9JAgdvvhgP nyEv5mojLKVKdV6EcLOGE+v+L69qqQBm1vkJ3m8BHjlvBOLnL7C3Rtkoc+qDgRdQ16zM+FEGEW dlM= X-IronPort-AV: E=Sophos;i="5.64,357,1559491200"; d="scan'208";a="119865577" Received: from mail-dm3nam03lp2054.outbound.protection.outlook.com (HELO NAM03-DM3-obe.outbound.protection.outlook.com) ([104.47.41.54]) by ob1.hgst.iphmx.com with ESMTP; 07 Aug 2019 20:29:24 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=YsAgJsQo8bHxzShOJtv6iN/h4zyGL7jtzPb4cBVCE3/Dr9fmwdp2l3SvgeSb+/frizH9WQ+XgStK9BDVEmvBZRQUYEY6ElCC1ynxDsrLKH5DFSzwJvwl+wmsf6HTbEgz4SbggVvevv3gEe59AQbm95FRPGO/So/iFD6LHLYJ+IOEowZh8uRO6o6zh6lZ1uCF4KsemAsaPs6ehLUIw4G2UPnhuouY3rTNtRDGZJDkPDS4JbP278iPPDRriKneB+KPWGaoea6We7pI8U71QsX4NntGzH8EsNlLEXm8BqoXnKV9TKE1iwl4LTWDp55ouqEkJ6GF+JdZ5AYCSa3dNBg6oA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=DtFShNa3RasnBd+yOfZgOgJ2kRQNtdMk2ugPJytVeIQ=; b=BYyH20Ra/EjecpQmiRYmrVuijP3tvNtaWiEi8vbJTHpGzVGBNl6VAb+xaR6sMvaECOWjWOWP/4akbUp/gk949Sg8aNO8cD8+RjGPdeDke9HxdK+Vl0XAzfoI2ktgqpas6Wz2s0KnH17QUusshCOgWs/Gu/MINTJU3y9KeuZst/68ZemfNcp8+557UX8RlFRx0famYkTrg3Ogd9KZELkSel55BMLF7jzXD4FrJHFX1PzoUma8KA6o6aoCTgVkffWVkc1BZbvM8zx8tm40je4+X48c4z6g+jOlE2YR8YuONtM5BzA+w6aWonWohFlR+hUDu/1ENmdmtNNaJkXN/AcExw== ARC-Authentication-Results: i=1; mx.microsoft.com 1;spf=pass smtp.mailfrom=wdc.com;dmarc=pass action=none header.from=wdc.com;dkim=pass header.d=wdc.com;arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector2-sharedspace-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=DtFShNa3RasnBd+yOfZgOgJ2kRQNtdMk2ugPJytVeIQ=; b=fM0YkRujGcTXOfTAc7n58HdemGIpTTEb6Da6QxYSI+TubDWN3Cu3ADqLVOlxXjP4Me+GxppvUnAI+jckAVZpy6uxKfqFxXPc3GyBxImzkIiKYj+Xjcn8a3Qsy3BhkmlyOf6AMNb/8RFYKppfM4daqkOaYorv5kZNWWrg/esNW1g= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB5821.namprd04.prod.outlook.com (20.179.22.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2136.17; Wed, 7 Aug 2019 12:29:22 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::a815:e61a:b4aa:60c8]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::a815:e61a:b4aa:60c8%7]) with mapi id 15.20.2157.015; Wed, 7 Aug 2019 12:29:22 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Paolo Bonzini , Radim K Subject: [PATCH v4 15/20] RISC-V: KVM: Add timer functionality Thread-Topic: [PATCH v4 15/20] RISC-V: KVM: Add timer functionality Thread-Index: AQHVTRu+cV0DIEntdk+KaD7G9p+4rA== Date: Wed, 7 Aug 2019 12:29:22 +0000 Message-ID: <20190807122726.81544-16-anup.patel@wdc.com> References: <20190807122726.81544-1-anup.patel@wdc.com> In-Reply-To: <20190807122726.81544-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: PN1PR01CA0097.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00::13) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [49.207.52.255] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: c7163ae8-3833-4d13-ef08-08d71b32e075 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020); SRVR:MN2PR04MB5821; x-ms-traffictypediagnostic: MN2PR04MB5821: x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:6108; x-forefront-prvs: 01221E3973 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(4636009)(346002)(366004)(39860400002)(396003)(136003)(376002)(199004)(189003)(110136005)(1076003)(71190400001)(6486002)(71200400001)(50226002)(186003)(53936002)(2906002)(25786009)(66066001)(8676002)(36756003)(54906003)(81156014)(7736002)(81166006)(6436002)(316002)(6512007)(8936002)(26005)(4326008)(305945005)(66446008)(6506007)(64756008)(66556008)(66476007)(66946007)(11346002)(68736007)(478600001)(2616005)(86362001)(476003)(55236004)(102836004)(486006)(446003)(76176011)(14454004)(14444005)(52116002)(3846002)(6116002)(256004)(5660300002)(7416002)(44832011)(386003)(99286004); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB5821; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: TCe+gktSVhrUfGGnMDb0Mk07O2TZMXfaws8tTm9CHMdTNz+IiH/H0mdSBhsFqXGFJVO0pSzfbAyGu/877A90ZadoyYrEMUiCHDiNGDRIRNiuntXhWE3dtMK7PqFegJSwFhEJnutnyEeu+enFbLM183n9C7iE/Z2TKpRLVSbiWVMTZNe7j3VmfhsMtcVffLMZunK5dm2Z2fCmrOCWES16MT9Z1+AgwC8lbh6NSND3+L+PI9lYqDObzblMgmlabcuFcJH4TCAa5RAkFPoip13GaHKCf05Fi5GU8DqmR+beBvmn/xJ3eXpWlBay0gfOlawyWWehLjYbHnxgitJ6rG1l+EmrX1Uci94mJqQ2NiF4VJJ0rq0J5Xhlo/f/HnJDrCWI5oRGGBBORrn0wbMDKPkjvxKbo/u8+Y3x6XPNa509spA= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: c7163ae8-3833-4d13-ef08-08d71b32e075 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Aug 2019 12:29:22.6223 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: EdlQkcfWJYndnf8pO7GMZTA/eSH9jqpgmXl8ddRXxsZ+ecEEywgeC8s36ht6TZbmP3BQtj+ns5oZu5N95iSGPg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5821 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190807_052925_399769_7853C488 X-CRM114-Status: GOOD ( 21.72 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , "kvm@vger.kernel.org" , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org" , Christoph Hellwig , Atish Patra , Alistair Francis , Thomas Gleixner , "linux-riscv@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org From: Atish Patra The RISC-V hypervisor specification doesn't have any virtual timer feature. Due to this, the guest VCPU timer will be programmed via SBI calls. The host will use a separate hrtimer event for each guest VCPU to provide timer functionality. We inject a virtual timer interrupt to the guest VCPU whenever the guest VCPU hrtimer event expires. The following features are not supported yet and will be added in future: 1. A time offset to adjust guest time from host time 2. A saved next event in guest vcpu for vm migration Signed-off-by: Atish Patra Signed-off-by: Anup Patel --- arch/riscv/include/asm/kvm_host.h | 4 + arch/riscv/include/asm/kvm_vcpu_timer.h | 32 +++++++ arch/riscv/kvm/Makefile | 2 +- arch/riscv/kvm/vcpu.c | 6 ++ arch/riscv/kvm/vcpu_timer.c | 106 ++++++++++++++++++++++++ drivers/clocksource/timer-riscv.c | 8 ++ include/clocksource/timer-riscv.h | 16 ++++ 7 files changed, 173 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/kvm_vcpu_timer.h create mode 100644 arch/riscv/kvm/vcpu_timer.c create mode 100644 include/clocksource/timer-riscv.h diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index ab33e59a3d88..d2a2e45eefc0 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -12,6 +12,7 @@ #include #include #include +#include #ifdef CONFIG_64BIT #define KVM_MAX_VCPUS (1U << 16) @@ -167,6 +168,9 @@ struct kvm_vcpu_arch { unsigned long irqs_pending; unsigned long irqs_pending_mask; + /* VCPU Timer */ + struct kvm_vcpu_timer timer; + /* MMIO instruction details */ struct kvm_mmio_decode mmio_decode; diff --git a/arch/riscv/include/asm/kvm_vcpu_timer.h b/arch/riscv/include/asm/kvm_vcpu_timer.h new file mode 100644 index 000000000000..df67ea86988e --- /dev/null +++ b/arch/riscv/include/asm/kvm_vcpu_timer.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#ifndef __KVM_VCPU_RISCV_TIMER_H +#define __KVM_VCPU_RISCV_TIMER_H + +#include + +#define VCPU_TIMER_PROGRAM_THRESHOLD_NS 1000 + +struct kvm_vcpu_timer { + bool init_done; + /* Check if the timer is programmed */ + bool is_set; + struct hrtimer hrt; + /* Mult & Shift values to get nanosec from cycles */ + u32 mult; + u32 shift; +}; + +int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu); +int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu); +int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu); +int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, + unsigned long ncycles); + +#endif diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index c0f57f26c13d..3e0c7558320d 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -9,6 +9,6 @@ ccflags-y := -Ivirt/kvm -Iarch/riscv/kvm kvm-objs := $(common-objs-y) kvm-objs += main.o vm.o vmid.o tlb.o mmu.o -kvm-objs += vcpu.o vcpu_exit.o vcpu_switch.o +kvm-objs += vcpu.o vcpu_exit.o vcpu_switch.o vcpu_timer.o obj-$(CONFIG_KVM) += kvm.o diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 6124077d154f..018fca436776 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -54,6 +54,8 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) memcpy(cntx, reset_cntx, sizeof(*cntx)); + kvm_riscv_vcpu_timer_reset(vcpu); + WRITE_ONCE(vcpu->arch.irqs_pending, 0); WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0); } @@ -108,6 +110,9 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) cntx->hstatus |= HSTATUS_SP2P; cntx->hstatus |= HSTATUS_SPV; + /* Setup VCPU timer */ + kvm_riscv_vcpu_timer_init(vcpu); + /* Reset VCPU */ kvm_riscv_reset_vcpu(vcpu); @@ -116,6 +121,7 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) { + kvm_riscv_vcpu_timer_deinit(vcpu); kvm_riscv_stage2_flush_cache(vcpu); kmem_cache_free(kvm_vcpu_cache, vcpu); } diff --git a/arch/riscv/kvm/vcpu_timer.c b/arch/riscv/kvm/vcpu_timer.c new file mode 100644 index 000000000000..a45ca06e1aa6 --- /dev/null +++ b/arch/riscv/kvm/vcpu_timer.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#include +#include +#include +#include +#include +#include + +static enum hrtimer_restart kvm_riscv_vcpu_hrtimer_expired(struct hrtimer *h) +{ + struct kvm_vcpu_timer *t = container_of(h, struct kvm_vcpu_timer, hrt); + struct kvm_vcpu *vcpu = container_of(t, struct kvm_vcpu, arch.timer); + + t->is_set = false; + kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_S_TIMER); + + return HRTIMER_NORESTART; +} + +static u64 kvm_riscv_delta_cycles2ns(u64 cycles, struct kvm_vcpu_timer *t) +{ + unsigned long flags; + u64 cycles_now, cycles_delta, delta_ns; + + local_irq_save(flags); + cycles_now = get_cycles64(); + if (cycles_now < cycles) + cycles_delta = cycles - cycles_now; + else + cycles_delta = 0; + delta_ns = (cycles_delta * t->mult) >> t->shift; + local_irq_restore(flags); + + return delta_ns; +} + +static int kvm_riscv_vcpu_timer_cancel(struct kvm_vcpu_timer *t) +{ + if (!t->init_done || !t->is_set) + return -EINVAL; + + hrtimer_cancel(&t->hrt); + t->is_set = false; + + return 0; +} + +int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, + unsigned long ncycles) +{ + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + u64 delta_ns = kvm_riscv_delta_cycles2ns(ncycles, t); + + if (!t->init_done) + return -EINVAL; + + kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_S_TIMER); + + if (delta_ns > VCPU_TIMER_PROGRAM_THRESHOLD_NS) { + hrtimer_start(&t->hrt, ktime_add_ns(ktime_get(), delta_ns), + HRTIMER_MODE_ABS); + t->is_set = true; + } else + kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_S_TIMER); + + return 0; +} + +int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + + if (t->init_done) + return -EINVAL; + + hrtimer_init(&t->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); + t->hrt.function = kvm_riscv_vcpu_hrtimer_expired; + t->init_done = true; + t->is_set = false; + + riscv_cs_get_mult_shift(&t->mult, &t->shift); + + return 0; +} + +int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu) +{ + int ret; + + ret = kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer); + vcpu->arch.timer.init_done = false; + + return ret; +} + +int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu) +{ + return kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer); +} diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 09e031176bc6..7c595203aa5c 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -80,6 +81,13 @@ static int riscv_timer_dying_cpu(unsigned int cpu) return 0; } +void riscv_cs_get_mult_shift(u32 *mult, u32 *shift) +{ + *mult = riscv_clocksource.mult; + *shift = riscv_clocksource.shift; +} +EXPORT_SYMBOL_GPL(riscv_cs_get_mult_shift); + /* called directly from the low-level interrupt handler */ void riscv_timer_interrupt(void) { diff --git a/include/clocksource/timer-riscv.h b/include/clocksource/timer-riscv.h new file mode 100644 index 000000000000..e94e4feecbe8 --- /dev/null +++ b/include/clocksource/timer-riscv.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#ifndef __TIMER_RISCV_H +#define __TIMER_RISCV_H + +#include + +void riscv_cs_get_mult_shift(u32 *mult, u32 *shift); + +#endif -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv