From: Christoph Hellwig <hch@lst.de>
To: Palmer Dabbelt <palmer@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>
Cc: Atish Patra <atish.patra@wdc.com>,
Damien Le Moal <damien.lemoal@wdc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 11/20] riscv: cleanup the default power off implementation
Date: Tue, 3 Sep 2019 11:32:30 +0200 [thread overview]
Message-ID: <20190903093239.21278-12-hch@lst.de> (raw)
In-Reply-To: <20190903093239.21278-1-hch@lst.de>
Move the sbi poweroff to a separate function and file that is only
compiled if CONFIG_SBI is set. Provide a new default fallback
power off that just sits in a wfi loop to save some power.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
---
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/reset.c | 5 ++---
arch/riscv/kernel/sbi.c | 17 +++++++++++++++++
3 files changed, 20 insertions(+), 3 deletions(-)
create mode 100644 arch/riscv/kernel/sbi.c
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index 2420d37d96de..21a8d09c298c 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -39,5 +39,6 @@ obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o
obj-$(CONFIG_PERF_EVENTS) += perf_event.o
+obj-$(CONFIG_RISCV_SBI) += sbi.o
clean:
diff --git a/arch/riscv/kernel/reset.c b/arch/riscv/kernel/reset.c
index d0fe623bfb8f..5e4e69859af1 100644
--- a/arch/riscv/kernel/reset.c
+++ b/arch/riscv/kernel/reset.c
@@ -4,12 +4,11 @@
*/
#include <linux/reboot.h>
-#include <asm/sbi.h>
static void default_power_off(void)
{
- sbi_shutdown();
- while (1);
+ while (1)
+ wait_for_interrupt();
}
void (*pm_power_off)(void) = default_power_off;
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
new file mode 100644
index 000000000000..f6c7c3e82d28
--- /dev/null
+++ b/arch/riscv/kernel/sbi.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <asm/sbi.h>
+
+static void sbi_power_off(void)
+{
+ sbi_shutdown();
+}
+
+static int __init sbi_init(void)
+{
+ pm_power_off = sbi_power_off;
+ return 0;
+}
+early_initcall(sbi_init);
--
2.20.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-09-03 9:33 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-03 9:32 RISC-V nommu support v4 Christoph Hellwig
2019-09-03 9:32 ` [PATCH 01/20] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig
2019-09-03 9:32 ` [PATCH 02/20] riscv: refactor the IPI code Christoph Hellwig
2019-09-03 9:32 ` [PATCH 03/20] riscv: cleanup send_ipi_mask Christoph Hellwig
2019-09-03 9:32 ` [PATCH 04/20] riscv: optimize send_ipi_single Christoph Hellwig
2019-09-03 9:32 ` [PATCH 05/20] riscv: cleanup riscv_cpuid_to_hartid_mask Christoph Hellwig
2019-09-03 9:32 ` [PATCH 06/20] riscv: don't use the rdtime(h) pseudo-instructions Christoph Hellwig
2019-09-03 9:32 ` [PATCH 07/20] riscv: move the TLB flush logic out of line Christoph Hellwig
2019-09-03 9:32 ` [PATCH 08/20] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-10-16 2:07 ` Paul Walmsley
2019-10-17 16:20 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 09/20] riscv: don't allow selecting SBI based drivers for M-mode Christoph Hellwig
2019-09-03 9:32 ` [PATCH 10/20] riscv: poison SBI calls " Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig [this message]
2019-09-03 9:32 ` [PATCH 12/20] riscv: implement remote sfence.i using IPIs Christoph Hellwig
2019-09-03 9:32 ` [PATCH 13/20] riscv: add support for MMIO access to the timer registers Christoph Hellwig
2019-09-03 9:32 ` [PATCH 14/20] riscv: provide native clint access for M-mode Christoph Hellwig
2019-09-03 9:32 ` [PATCH 15/20] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-09-03 9:32 ` [PATCH 16/20] riscv: use the correct interrupt levels for M-mode Christoph Hellwig
2019-09-03 9:32 ` [PATCH 17/20] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-09-03 9:32 ` [PATCH 18/20] riscv: add nommu support Christoph Hellwig
2019-09-03 9:32 ` [PATCH 19/20] riscv: provide a flat image loader Christoph Hellwig
2019-09-03 9:32 ` [PATCH 20/20] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190903093239.21278-12-hch@lst.de \
--to=hch@lst.de \
--cc=atish.patra@wdc.com \
--cc=damien.lemoal@wdc.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@sifive.com \
--cc=paul.walmsley@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).