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From: Palmer Dabbelt <palmer@sifive.com>
To: linux-riscv@lists.infradead.org
Cc: Palmer Dabbelt <palmer@sifive.com>
Subject: [PATCH 2/4] Documentation: riscv: boot: Don't claim we're compliant with PE
Date: Fri, 13 Sep 2019 12:24:31 -0700
Message-ID: <20190913192433.4316-3-palmer@sifive.com> (raw)
In-Reply-To: <20190913192433.4316-1-palmer@sifive.com>

We don't yet have a PE header in our image.  While we could add one, we
shouldn't claim we have one in the documentation.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 Documentation/riscv/boot-image-header.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/riscv/boot-image-header.txt b/Documentation/riscv/boot-image-header.txt
index 77e8e505bc41..219f62ef62c4 100644
--- a/Documentation/riscv/boot-image-header.txt
+++ b/Documentation/riscv/boot-image-header.txt
@@ -21,7 +21,7 @@ The following 64-byte header is present in decompressed Linux kernel image.
 	u32 res3;		  /* Reserved for additional RISC-V specific header */
 	u32 res4;		  /* Reserved for PE COFF offset */
 
-This header format is compliant with PE/COFF header and largely inspired by,
+This header format can be made compliant with PE/COFF header and largely inspired by,
 but not compatible with, the ARM64 header.
 
 Notes:
-- 
2.21.0


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Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-13 19:24 [PATCH 0/4] Documentation: riscv: Image cleanups Palmer Dabbelt
2019-09-13 19:24 ` [PATCH 1/4] Documentation: riscv: boot: We're not compatible with arm64 Palmer Dabbelt
2019-09-14  1:13   ` Paul Walmsley
2019-09-14  2:46     ` Atish Patra
2019-09-13 19:24 ` Palmer Dabbelt [this message]
2019-09-13 19:24 ` [PATCH 3/4] Documentation: riscv: boot: Whitespace fix Palmer Dabbelt
2019-09-13 19:24 ` [PATCH 4/4] Documentation: riscv: boot: Don't mention big-endian Palmer Dabbelt
2019-09-14  4:06 ` [PATCH 0/4] Documentation: riscv: Image cleanups Atish Patra

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