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From: Palmer Dabbelt <>
Cc: Palmer Dabbelt <>
Subject: [PATCH 4/4] Documentation: riscv: boot: Don't mention big-endian
Date: Fri, 13 Sep 2019 12:24:33 -0700	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

The documentation defines a flag to indicate big endian systems, but
doesn't define what that flag actually means -- for example:

* Are the other fields BE or LE?
* Does the BE format assume the bootloader enters BE mode, is there a
  kernel stub that does so, or are we adding extra BE instructions?

Signed-off-by: Palmer Dabbelt <>
 Documentation/riscv/boot-image-header.txt | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/Documentation/riscv/boot-image-header.txt b/Documentation/riscv/boot-image-header.txt
index e325d1c9ad4c..d3efaf374b27 100644
--- a/Documentation/riscv/boot-image-header.txt
+++ b/Documentation/riscv/boot-image-header.txt
@@ -42,8 +42,5 @@ Notes:
   header extendible in future. One example would be to accommodate ISA
   extension for RISC-V in future. For current version, it is set to be zero.
-- In current header, the flag field has only one field.
-	Bit 0: Kernel endianness. 1 if BE, 0 if LE.
 - Image size is mandatory for boot loader to load kernel image. Booting will
   fail otherwise.

linux-riscv mailing list

  parent reply	other threads:[~2019-09-13 19:28 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-13 19:24 [PATCH 0/4] Documentation: riscv: Image cleanups Palmer Dabbelt
2019-09-13 19:24 ` [PATCH 1/4] Documentation: riscv: boot: We're not compatible with arm64 Palmer Dabbelt
2019-09-14  1:13   ` Paul Walmsley
2019-09-14  2:46     ` Atish Patra
2019-09-13 19:24 ` [PATCH 2/4] Documentation: riscv: boot: Don't claim we're compliant with PE Palmer Dabbelt
2019-09-13 19:24 ` [PATCH 3/4] Documentation: riscv: boot: Whitespace fix Palmer Dabbelt
2019-09-13 19:24 ` Palmer Dabbelt [this message]
2019-09-14  4:06 ` [PATCH 0/4] Documentation: riscv: Image cleanups Atish Patra

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