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From: Anup Patel <Anup.Patel@wdc.com>
To: Palmer Dabbelt <palmer@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Paolo Bonzini <pbonzini@redhat.com>, Radim K <rkrcmar@redhat.com>
Cc: Damien Le Moal <Damien.LeMoal@wdc.com>,
	Anup Patel <Anup.Patel@wdc.com>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	Anup Patel <anup@brainfault.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Christoph Hellwig <hch@infradead.org>,
	Atish Patra <Atish.Patra@wdc.com>,
	Alexander Graf <graf@amazon.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>
Subject: [PATCH v8 09/19] RISC-V: KVM: Handle WFI exits for VCPU
Date: Thu, 3 Oct 2019 05:07:39 +0000
Message-ID: <20191003050558.9031-10-anup.patel@wdc.com> (raw)
In-Reply-To: <20191003050558.9031-1-anup.patel@wdc.com>

We get illegal instruction trap whenever Guest/VM executes WFI
instruction.

This patch handles WFI trap by blocking the trapped VCPU using
kvm_vcpu_block() API. The blocked VCPU will be automatically
resumed whenever a VCPU interrupt is injected from user-space
or from in-kernel IRQCHIP emulation.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/riscv/kvm/vcpu_exit.c | 72 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c
index f1378c0a447f..7507b859246b 100644
--- a/arch/riscv/kvm/vcpu_exit.c
+++ b/arch/riscv/kvm/vcpu_exit.c
@@ -12,6 +12,13 @@
 #include <linux/kvm_host.h>
 #include <asm/csr.h>
 
+#define INSN_OPCODE_MASK	0x007c
+#define INSN_OPCODE_SHIFT	2
+#define INSN_OPCODE_SYSTEM	28
+
+#define INSN_MASK_WFI		0xffffff00
+#define INSN_MATCH_WFI		0x10500000
+
 #define INSN_MATCH_LB		0x3
 #define INSN_MASK_LB		0x707f
 #define INSN_MATCH_LH		0x1003
@@ -116,6 +123,67 @@
 				 (s32)(((insn) >> 7) & 0x1f))
 #define MASK_FUNCT3		0x7000
 
+static int truly_illegal_insn(struct kvm_vcpu *vcpu,
+			      struct kvm_run *run,
+			      ulong insn)
+{
+	/* Redirect trap to Guest VCPU */
+	kvm_riscv_vcpu_trap_redirect(vcpu, EXC_INST_ILLEGAL, insn);
+
+	return 1;
+}
+
+static int system_opcode_insn(struct kvm_vcpu *vcpu,
+			      struct kvm_run *run,
+			      ulong insn)
+{
+	if ((insn & INSN_MASK_WFI) == INSN_MATCH_WFI) {
+		vcpu->stat.wfi_exit_stat++;
+		if (!kvm_arch_vcpu_runnable(vcpu)) {
+			srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx);
+			kvm_vcpu_block(vcpu);
+			vcpu->arch.srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
+			kvm_clear_request(KVM_REQ_UNHALT, vcpu);
+		}
+		vcpu->arch.guest_context.sepc += INSN_LEN(insn);
+		return 1;
+	}
+
+	return truly_illegal_insn(vcpu, run, insn);
+}
+
+static int illegal_inst_fault(struct kvm_vcpu *vcpu, struct kvm_run *run,
+			      unsigned long insn)
+{
+	unsigned long ut_scause = 0;
+	struct kvm_cpu_context *ct;
+
+	if (unlikely(INSN_IS_16BIT(insn))) {
+		if (insn == 0) {
+			ct = &vcpu->arch.guest_context;
+			insn = kvm_riscv_vcpu_unpriv_read(vcpu, true,
+							  ct->sepc,
+							  &ut_scause);
+			if (ut_scause) {
+				if (ut_scause == EXC_LOAD_PAGE_FAULT)
+					ut_scause = EXC_INST_PAGE_FAULT;
+				kvm_riscv_vcpu_trap_redirect(vcpu, ut_scause,
+							     ct->sepc);
+				return 1;
+			}
+		}
+		if (INSN_IS_16BIT(insn))
+			return truly_illegal_insn(vcpu, run, insn);
+	}
+
+	switch ((insn & INSN_OPCODE_MASK) >> INSN_OPCODE_SHIFT) {
+	case INSN_OPCODE_SYSTEM:
+		return system_opcode_insn(vcpu, run, insn);
+	default:
+		return truly_illegal_insn(vcpu, run, insn);
+	}
+}
+
 static int emulate_load(struct kvm_vcpu *vcpu, struct kvm_run *run,
 			unsigned long fault_addr)
 {
@@ -508,6 +576,10 @@ int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
 	ret = -EFAULT;
 	run->exit_reason = KVM_EXIT_UNKNOWN;
 	switch (scause) {
+	case EXC_INST_ILLEGAL:
+		if (vcpu->arch.guest_context.hstatus & HSTATUS_SPV)
+			ret = illegal_inst_fault(vcpu, run, stval);
+		break;
 	case EXC_INST_PAGE_FAULT:
 	case EXC_LOAD_PAGE_FAULT:
 	case EXC_STORE_PAGE_FAULT:
-- 
2.17.1


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  parent reply index

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-03  5:06 [PATCH v8 00/19] KVM RISC-V Support Anup Patel
2019-10-03  5:06 ` [PATCH v8 01/19] RISC-V: Add bitmap reprensenting ISA features common across CPUs Anup Patel
2019-10-03  5:06 ` [PATCH v8 02/19] RISC-V: Add hypervisor extension related CSR defines Anup Patel
2019-10-03  5:06 ` [PATCH v8 03/19] RISC-V: Add initial skeletal KVM support Anup Patel
2019-10-03  5:07 ` [PATCH v8 04/19] RISC-V: KVM: Implement VCPU create, init and destroy functions Anup Patel
2019-10-03  5:07 ` [PATCH v8 05/19] RISC-V: KVM: Implement VCPU interrupts and requests handling Anup Patel
2019-10-03  5:07 ` [PATCH v8 06/19] RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls Anup Patel
2019-10-03  5:07 ` [PATCH v8 07/19] RISC-V: KVM: Implement VCPU world-switch Anup Patel
2019-10-03  5:07 ` [PATCH v8 08/19] RISC-V: KVM: Handle MMIO exits for VCPU Anup Patel
2019-10-03 10:18   ` Paolo Bonzini
2019-10-03  5:07 ` Anup Patel [this message]
2019-10-03  5:07 ` [PATCH v8 10/19] RISC-V: KVM: Implement VMID allocator Anup Patel
2019-10-03  5:07 ` [PATCH v8 11/19] RISC-V: KVM: Implement stage2 page table programming Anup Patel
2019-10-03  5:08 ` [PATCH v8 12/19] RISC-V: KVM: Implement MMU notifiers Anup Patel
2019-10-03  5:08 ` [PATCH v8 13/19] RISC-V: KVM: Add timer functionality Anup Patel
2019-10-03  5:08 ` [PATCH v8 14/19] RISC-V: KVM: FP lazy save/restore Anup Patel
2019-10-03  5:08 ` [PATCH v8 15/19] RISC-V: KVM: Implement ONE REG interface for FP registers Anup Patel
2019-10-03  5:08 ` [PATCH v8 16/19] RISC-V: KVM: Add SBI v0.1 support Anup Patel
2019-10-03  5:08 ` [PATCH v8 17/19] RISC-V: KVM: Forward unhandled SBI calls to userspace Anup Patel
2019-10-03  5:08 ` [PATCH v8 18/19] RISC-V: KVM: Document RISC-V specific parts of KVM API Anup Patel
2019-10-03  5:08 ` [PATCH v8 19/19] RISC-V: KVM: Add MAINTAINERS entry Anup Patel

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