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From: Christoph Hellwig <hch@lst.de>
To: Palmer Dabbelt <palmer@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>
Cc: Damien Le Moal <damien.lemoal@wdc.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 11/15] riscv: use the correct interrupt levels for M-mode
Date: Thu, 17 Oct 2019 19:37:39 +0200
Message-ID: <20191017173743.5430-12-hch@lst.de> (raw)
In-Reply-To: <20191017173743.5430-1-hch@lst.de>

The numerical levels for External/Timer/Software interrupts differ
between S-mode and M-mode.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/riscv/kernel/irq.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c
index 804ff70bb853..dbd1fd7c22e4 100644
--- a/arch/riscv/kernel/irq.c
+++ b/arch/riscv/kernel/irq.c
@@ -14,9 +14,15 @@
 /*
  * Possible interrupt causes:
  */
-#define INTERRUPT_CAUSE_SOFTWARE	IRQ_S_SOFT
-#define INTERRUPT_CAUSE_TIMER		IRQ_S_TIMER
-#define INTERRUPT_CAUSE_EXTERNAL	IRQ_S_EXT
+#ifdef CONFIG_RISCV_M_MODE
+# define INTERRUPT_CAUSE_SOFTWARE	IRQ_M_SOFT
+# define INTERRUPT_CAUSE_TIMER		IRQ_M_TIMER
+# define INTERRUPT_CAUSE_EXTERNAL	IRQ_M_EXT
+#else
+# define INTERRUPT_CAUSE_SOFTWARE	IRQ_S_SOFT
+# define INTERRUPT_CAUSE_TIMER		IRQ_S_TIMER
+# define INTERRUPT_CAUSE_EXTERNAL	IRQ_S_EXT
+#endif /* CONFIG_RISCV_M_MODE */
 
 int arch_show_interrupts(struct seq_file *p, int prec)
 {
-- 
2.20.1


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Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-17 17:37 RISC-V nommu support v5 Christoph Hellwig
2019-10-17 17:37 ` [PATCH 01/15] riscv: cleanup <asm/bug.h> Christoph Hellwig
2019-10-18  2:50   ` Anup Patel
2019-10-23 22:04   ` Paul Walmsley
2019-10-17 17:37 ` [PATCH 02/15] riscv: cleanup do_trap_break Christoph Hellwig
2019-10-18  2:51   ` Anup Patel
2019-10-23 22:05   ` Paul Walmsley
2019-10-17 17:37 ` [PATCH 03/15] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-10-18  2:51   ` Anup Patel
2019-10-18 23:55   ` Paul Walmsley
2019-10-28  8:12     ` Christoph Hellwig
2019-10-17 17:37 ` [PATCH 04/15] riscv: don't allow selecting SBI based drivers for M-mode Christoph Hellwig
2019-10-18  2:52   ` Anup Patel
2019-10-17 17:37 ` [PATCH 05/15] riscv: poison SBI calls " Christoph Hellwig
2019-10-18  2:53   ` Anup Patel
2019-10-17 17:37 ` [PATCH 06/15] riscv: cleanup the default power off implementation Christoph Hellwig
2019-10-18  2:53   ` Anup Patel
2019-10-17 17:37 ` [PATCH 07/15] riscv: implement remote sfence.i using IPIs Christoph Hellwig
2019-10-18  2:55   ` Anup Patel
2019-10-17 17:37 ` [PATCH 08/15] riscv: add support for MMIO access to the timer registers Christoph Hellwig
2019-10-18  2:57   ` Anup Patel
2019-10-17 17:37 ` [PATCH 09/15] riscv: provide native clint access for M-mode Christoph Hellwig
2019-10-18  3:00   ` Anup Patel
2019-11-14  7:39   ` Paul Walmsley
2019-10-17 17:37 ` [PATCH 10/15] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-10-18  3:01   ` Anup Patel
2019-11-14  7:40   ` Paul Walmsley
2019-10-17 17:37 ` Christoph Hellwig [this message]
2019-10-18  3:01   ` [PATCH 11/15] riscv: use the correct interrupt levels for M-mode Anup Patel
2019-10-17 17:37 ` [PATCH 12/15] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-10-18  3:05   ` Anup Patel
2019-10-17 17:37 ` [PATCH 13/15] riscv: add nommu support Christoph Hellwig
2019-10-18  3:04   ` Anup Patel
2019-10-17 17:37 ` [PATCH 14/15] riscv: provide a flat image loader Christoph Hellwig
2019-10-18  3:06   ` Anup Patel
2019-10-17 17:37 ` [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
2019-10-18  3:06   ` Anup Patel
2019-10-18  3:08 ` RISC-V nommu support v5 Anup Patel
2019-10-18  3:29   ` Paul Walmsley
2019-10-18 15:25     ` Christoph Hellwig
2019-10-18 23:46       ` Paul Walmsley

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