* [PATCH v4 0/4] dmaengine: sf-pdma: Add platform dma driver @ 2019-10-03 9:09 Green Wan 2019-10-03 9:09 ` [PATCH v4 1/4] dt-bindings: dmaengine: sf-pdma: add bindins for SiFive PDMA Green Wan ` (3 more replies) 0 siblings, 4 replies; 9+ messages in thread From: Green Wan @ 2019-10-03 9:09 UTC (permalink / raw) To: linux-hackers Cc: Mark Rutland, devicetree, Albert Ou, Greg Kroah-Hartman, Palmer Dabbelt, Yash Shah, Green Wan, Bin Meng, dmaengine, Vinod Koul, Rob Herring, Sagar Kadam, Jonathan Cameron, Paul Walmsley, Mauro Carvalho Chehab, Dan Williams, Paul E. McKenney, linux-riscv, David S. Miller, linux-kernel Add PDMA driver support for SiFive HiFive Unleashed RevA00 board. Mainly follows DMAengine controller doc[1] to implement and take other DMA drivers as reference. Such as - drivers/dma/fsl-edma.c - drivers/dma/dw-edma/ - drivers/dma/pxa-dma.c Using DMA test client[2] to test. Detailed datasheet is doc[3]. Driver supports: - 4 physical DMA channels, share same DONE and error interrupt handler. - Support MEM_TO_MEM - Tested by DMA test client - patches include DT Bindgins document and dts for fu450-c000 SoC. Separate dts patch for easier review and apply to different branch or SoC platform. - retry 1 time if DMA error occurs. [Reference Doc] [1] ./Documentation/driver-api/dmaengine/provider.rst [2] ./Documentation/driver-api/dmaengine/dmatest.rst [3] https://static.dev.sifive.com/FU540-C000-v1.0.pdf [Simple steps to test of DMA Test client] $ echo 1 > /sys/module/dmatest/parameters/iterations $ echo dma0chan0 > /sys/module/dmatest/parameters/channel $ echo dma0chan1 > /sys/module/dmatest/parameters/channel $ echo dma0chan2 > /sys/module/dmatest/parameters/channel $ echo dma0chan3 > /sys/module/dmatest/parameters/channel $ echo 1 > /sys/module/dmatest/parameters/run [Expected test result] [ 267.563323] dmatest: dma0chan0-copy0: summary 45629 tests, 0 failures 38769.01 iops 309661 KB/s (0) [ 267.572427] dmatest: dma0chan1-copy0: summary 45863 tests, 0 failures 40286.85 iops 321643 KB/s (0) [ 267.581392] dmatest: dma0chan2-copy0: summary 45975 tests, 0 failures 41178.48 iops 328740 KB/s (0) [ 267.590542] dmatest: dma0chan3-copy0: summary 44768 tests, 0 failures 38560.29 iops 307726 KB/s (0) Green Wan (4): dt-bindings: dmaengine: sf-pdma: add bindins for SiFive PDMA riscv: dts: add support for PDMA device of HiFive Unleashed Rev A00 dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 MAINTAINERS: Add Green as SiFive PDMA driver maintainer .../bindings/dma/sifive,fu540-c000-pdma.yaml | 55 ++ MAINTAINERS | 6 + arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 7 + drivers/dma/Kconfig | 2 + drivers/dma/Makefile | 1 + drivers/dma/sf-pdma/Kconfig | 6 + drivers/dma/sf-pdma/Makefile | 1 + drivers/dma/sf-pdma/sf-pdma.c | 601 ++++++++++++++++++ drivers/dma/sf-pdma/sf-pdma.h | 124 ++++ 9 files changed, 803 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml create mode 100644 drivers/dma/sf-pdma/Kconfig create mode 100644 drivers/dma/sf-pdma/Makefile create mode 100644 drivers/dma/sf-pdma/sf-pdma.c create mode 100644 drivers/dma/sf-pdma/sf-pdma.h -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4 1/4] dt-bindings: dmaengine: sf-pdma: add bindins for SiFive PDMA 2019-10-03 9:09 [PATCH v4 0/4] dmaengine: sf-pdma: Add platform dma driver Green Wan @ 2019-10-03 9:09 ` Green Wan 2019-10-09 23:34 ` Rob Herring 2019-10-03 9:09 ` [PATCH v4 2/4] riscv: dts: add support for PDMA device of HiFive Unleashed Rev A00 Green Wan ` (2 subsequent siblings) 3 siblings, 1 reply; 9+ messages in thread From: Green Wan @ 2019-10-03 9:09 UTC (permalink / raw) To: linux-hackers Cc: Mark Rutland, devicetree, Albert Ou, Greg Kroah-Hartman, Palmer Dabbelt, Yash Shah, Green Wan, Bin Meng, dmaengine, Vinod Koul, Rob Herring, Sagar Kadam, Jonathan Cameron, Paul Walmsley, Mauro Carvalho Chehab, Dan Williams, Paul E. McKenney, linux-riscv, David S. Miller, linux-kernel Add DT bindings document for Platform DMA(PDMA) driver of board, HiFive Unleashed Rev A00. Signed-off-by: Green Wan <green.wan@sifive.com> --- .../bindings/dma/sifive,fu540-c000-pdma.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml diff --git a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml new file mode 100644 index 000000000000..2ca3ddbe1ff4 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Unleashed Rev C000 Platform DMA + +maintainers: + - Green Wan <green.wan@sifive.com> + - Palmer Debbelt <palmer@sifive.com> + - Paul Walmsley <paul.walmsley@sifive.com> + +description: | + Platform DMA is a DMA engine of SiFive Unleashed. It supports 4 + channels. Each channel has 2 interrupts. One is for DMA done and + the other is for DME error. + + In different SoC, DMA could be attached to different IRQ line. + DT file need to be changed to meet the difference. For technical + doc, + + https://static.dev.sifive.com/FU540-C000-v1.0.pdf + +properties: + compatible: + items: + - const: sifive,fu540-c000-pdma + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 8 + + '#dma-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#dma-cells' + +examples: + - | + dma@3000000 { + compatible = "sifive,fu540-c000-pdma"; + reg = <0x0 0x3000000 0x0 0x8000>; + interrupts = <23 24 25 26 27 28 29 30>; + #dma-cells = <1>; + }; + +... -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: dmaengine: sf-pdma: add bindins for SiFive PDMA 2019-10-03 9:09 ` [PATCH v4 1/4] dt-bindings: dmaengine: sf-pdma: add bindins for SiFive PDMA Green Wan @ 2019-10-09 23:34 ` Rob Herring 0 siblings, 0 replies; 9+ messages in thread From: Rob Herring @ 2019-10-09 23:34 UTC (permalink / raw) To: Green Wan Cc: devicetree, Bin Meng, Greg Kroah-Hartman, Yash Shah, Green Wan, linux-kernel, Vinod Koul, Sagar Kadam, Jonathan Cameron, dmaengine, linux-hackers, linux-riscv, Paul E. McKenney, David S. Miller On Thu, 3 Oct 2019 17:09:01 +0800, Green Wan wrote: > Add DT bindings document for Platform DMA(PDMA) driver of board, > HiFive Unleashed Rev A00. > > Signed-off-by: Green Wan <green.wan@sifive.com> > --- > .../bindings/dma/sifive,fu540-c000-pdma.yaml | 55 +++++++++++++++++++ > 1 file changed, 55 insertions(+) > create mode 100644 Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml > Reviewed-by: Rob Herring <robh@kernel.org> _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4 2/4] riscv: dts: add support for PDMA device of HiFive Unleashed Rev A00 2019-10-03 9:09 [PATCH v4 0/4] dmaengine: sf-pdma: Add platform dma driver Green Wan 2019-10-03 9:09 ` [PATCH v4 1/4] dt-bindings: dmaengine: sf-pdma: add bindins for SiFive PDMA Green Wan @ 2019-10-03 9:09 ` Green Wan 2019-10-03 9:09 ` [PATCH v4 3/4] dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 Green Wan 2019-10-03 9:09 ` [PATCH v4 4/4] MAINTAINERS: Add Green as SiFive PDMA driver maintainer Green Wan 3 siblings, 0 replies; 9+ messages in thread From: Green Wan @ 2019-10-03 9:09 UTC (permalink / raw) To: linux-hackers Cc: Mark Rutland, devicetree, Albert Ou, Greg Kroah-Hartman, Linus Walleij, Palmer Dabbelt, Yash Shah, Green Wan, Bin Meng, dmaengine, Vinod Koul, Rob Herring, Sagar Kadam, Paul Walmsley, Mauro Carvalho Chehab, Dan Williams, Paul E. McKenney, linux-riscv, David S. Miller, linux-kernel Add PDMA support to (arch/riscv/boot/dts/sifive/fu540-c000.dtsi) Signed-off-by: Green Wan <green.wan@sifive.com> --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index afa43c7ea369..70a1891e7cd0 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -162,6 +162,13 @@ clocks = <&prci PRCI_CLK_TLCLK>; status = "disabled"; }; + dma: dma@3000000 { + compatible = "sifive,fu540-c000-pdma"; + reg = <0x0 0x3000000 0x0 0x8000>; + interrupt-parent = <&plic0>; + interrupts = <23 24 25 26 27 28 29 30>; + #dma-cells = <1>; + }; uart1: serial@10011000 { compatible = "sifive,fu540-c000-uart", "sifive,uart0"; reg = <0x0 0x10011000 0x0 0x1000>; -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 3/4] dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 2019-10-03 9:09 [PATCH v4 0/4] dmaengine: sf-pdma: Add platform dma driver Green Wan 2019-10-03 9:09 ` [PATCH v4 1/4] dt-bindings: dmaengine: sf-pdma: add bindins for SiFive PDMA Green Wan 2019-10-03 9:09 ` [PATCH v4 2/4] riscv: dts: add support for PDMA device of HiFive Unleashed Rev A00 Green Wan @ 2019-10-03 9:09 ` Green Wan 2019-10-13 13:04 ` [RFC PATCH] dmaengine: sf-pdma: sf_pdma_disclaim_chan() can be static kbuild test robot ` (2 more replies) 2019-10-03 9:09 ` [PATCH v4 4/4] MAINTAINERS: Add Green as SiFive PDMA driver maintainer Green Wan 3 siblings, 3 replies; 9+ messages in thread From: Green Wan @ 2019-10-03 9:09 UTC (permalink / raw) To: linux-hackers Cc: Mark Rutland, devicetree, Albert Ou, Greg Kroah-Hartman, Palmer Dabbelt, Yash Shah, Green Wan, Bin Meng, dmaengine, Vinod Koul, Rob Herring, Sagar Kadam, Jonathan Cameron, Paul Walmsley, Mauro Carvalho Chehab, Dan Williams, Paul E. McKenney, linux-riscv, David S. Miller, linux-kernel Add PDMA driver, sf-pdma, to enable DMA engine on HiFive Unleashed Rev A00 board. - Implement dmaengine APIs, support MEM_TO_MEM async copy. - Tested by DMA Test client - Supports 4 channels DMA, each channel has 1 done and 1 err interrupt connected to platform-level interrupt controller (PLIC). - Depends on DMA_ENGINE and DMA_VIRTUAL_CHANNELS The datasheet is here: https://static.dev.sifive.com/FU540-C000-v1.0.pdf Follow the DMAengine controller doc, "./Documentation/driver-api/dmaengine/provider.rst" to implement DMA engine. And use the dma test client in doc, "./Documentation/driver-api/dmaengine/dmatest.rst", to test. Each DMA channel has separate HW regs and support done and error ISRs. 4 channels share 1 done and 1 err ISRs. There's no expander/arbitrator in DMA HW. ------ ------ | |--< done 23 >--|ch 0| | |--< err 24 >--| | (dma0chan0) | | ------ | | ------ | |--< done 25 >--|ch 1| | |--< err 26 >--| | (dma0chan1) |PLIC| ------ | | ------ | |--< done 27 >--|ch 2| | |--< err 28 >--| | (dma0chan2) | | ------ | | ------ | |--< done 29 >--|ch 3| | |--< err 30 >--| | (dma0chan3) ------ ------ Signed-off-by: Green Wan <green.wan@sifive.com> --- drivers/dma/Kconfig | 2 + drivers/dma/Makefile | 1 + drivers/dma/sf-pdma/Kconfig | 6 + drivers/dma/sf-pdma/Makefile | 1 + drivers/dma/sf-pdma/sf-pdma.c | 601 ++++++++++++++++++++++++++++++++++ drivers/dma/sf-pdma/sf-pdma.h | 124 +++++++ 6 files changed, 735 insertions(+) create mode 100644 drivers/dma/sf-pdma/Kconfig create mode 100644 drivers/dma/sf-pdma/Makefile create mode 100644 drivers/dma/sf-pdma/sf-pdma.c create mode 100644 drivers/dma/sf-pdma/sf-pdma.h diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 7af874b69ffb..03dc82094857 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -661,6 +661,8 @@ source "drivers/dma/qcom/Kconfig" source "drivers/dma/dw/Kconfig" +source "drivers/dma/sf-pdma/Kconfig" + source "drivers/dma/dw-edma/Kconfig" source "drivers/dma/hsu/Kconfig" diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index f5ce8665e944..4bbd90563ede 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_DMA_SUN4I) += sun4i-dma.o obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac/ obj-$(CONFIG_DW_DMAC_CORE) += dw/ +obj-$(CONFIG_SF_PDMA) += sf-pdma/ obj-$(CONFIG_DW_EDMA) += dw-edma/ obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o obj-$(CONFIG_FSL_DMA) += fsldma.o diff --git a/drivers/dma/sf-pdma/Kconfig b/drivers/dma/sf-pdma/Kconfig new file mode 100644 index 000000000000..0e01a5728a79 --- /dev/null +++ b/drivers/dma/sf-pdma/Kconfig @@ -0,0 +1,6 @@ +config SF_PDMA + bool "Sifive PDMA controller driver" + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + help + Support the SiFive PDMA controller. diff --git a/drivers/dma/sf-pdma/Makefile b/drivers/dma/sf-pdma/Makefile new file mode 100644 index 000000000000..764552ab8d0a --- /dev/null +++ b/drivers/dma/sf-pdma/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_SF_PDMA) += sf-pdma.o diff --git a/drivers/dma/sf-pdma/sf-pdma.c b/drivers/dma/sf-pdma/sf-pdma.c new file mode 100644 index 000000000000..70197ad95c1a --- /dev/null +++ b/drivers/dma/sf-pdma/sf-pdma.c @@ -0,0 +1,601 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/** + * SiFive FU540 Platform DMA driver + * Copyright (C) 2019 SiFive + * + * Based partially on: + * - drivers/dma/fsl-edma.c + * - drivers/dma/dw-edma/ + * - drivers/dma/pxa-dma.c + * + * See the following sources for further documentation: + * - Chapter 12 "Platform DMA Engine (PDMA)" of + * SiFive FU540-C000 v1.0 + * https://static.dev.sifive.com/FU540-C000-v1.0.pdf + */ +#include <linux/module.h> +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/pm_runtime.h> +#include <linux/dmaengine.h> +#include <linux/err.h> +#include <linux/interrupt.h> +#include <linux/dma-mapping.h> +#include <linux/irq.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/of_dma.h> +#include <linux/time64.h> + +#include "sf-pdma.h" +#include "../dmaengine.h" +#include "../virt-dma.h" + +#define SIFIVE_PDMA_NAME "sf-pdma" + +#ifndef readq +static inline unsigned long long readq(void __iomem *addr) +{ + return readl(addr) | (((unsigned long long)readl(addr + 4)) << 32LL); +} +#endif + +#ifndef writeq +static inline void writeq(unsigned long long v, void __iomem *addr) +{ + writel(v & 0xffffffff, addr); + writel(v >> 32, addr + 4); +} +#endif + +static inline struct sf_pdma_chan *to_sf_pdma_chan(struct dma_chan *dchan) +{ + return container_of(dchan, struct sf_pdma_chan, vchan.chan); +} + +static inline struct sf_pdma_desc *to_sf_pdma_desc(struct virt_dma_desc *vd) +{ + return container_of(vd, struct sf_pdma_desc, vdesc); +} + +static struct sf_pdma_desc *sf_pdma_alloc_desc(struct sf_pdma_chan *chan) +{ + struct sf_pdma_desc *desc; + unsigned long flags; + + spin_lock_irqsave(&chan->lock, flags); + + if (chan->desc && !chan->desc->in_use) { + spin_unlock_irqrestore(&chan->lock, flags); + return chan->desc; + } + + spin_unlock_irqrestore(&chan->lock, flags); + + desc = kzalloc(sizeof(*desc), GFP_NOWAIT); + + if (!desc) + return NULL; + + desc->chan = chan; + + return desc; +} + +static void sf_pdma_fill_desc(struct sf_pdma_chan *chan, + u64 dst, + u64 src, + u64 size) +{ + struct pdma_regs *regs = &chan->regs; + + writel(PDMA_FULL_SPEED, regs->xfer_type); + writeq(size, regs->xfer_size); + writeq(dst, regs->dst_addr); + writeq(src, regs->src_addr); +} + +void sf_pdma_disclaim_chan(struct sf_pdma_chan *chan) +{ + struct pdma_regs *regs = &chan->regs; + + writel(PDMA_CLEAR_CTRL, regs->ctrl); +} + +struct dma_async_tx_descriptor * + sf_pdma_prep_dma_memcpy(struct dma_chan *dchan, + dma_addr_t dest, + dma_addr_t src, + size_t len, + unsigned long flags) +{ + struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan); + struct sf_pdma_desc *desc; + + if (!chan || !len || !dest || !src) { + pr_debug("%s: Please check dma len, dest, src!\n", __func__); + return NULL; + } + + desc = sf_pdma_alloc_desc(chan); + if (!desc) + return NULL; + + desc->in_use = true; + desc->dirn = DMA_MEM_TO_MEM; + desc->async_tx = vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); + + spin_lock_irqsave(&chan->lock, flags); + chan->desc = desc; + sf_pdma_fill_desc(desc->chan, dest, src, len); + spin_unlock_irqrestore(&chan->lock, flags); + + return desc->async_tx; +} + +static void sf_pdma_unprep_slave_dma(struct sf_pdma_chan *chan) +{ + if (chan->dma_dir != DMA_NONE) + dma_unmap_resource(chan->vchan.chan.device->dev, + chan->dma_dev_addr, + chan->dma_dev_size, + chan->dma_dir, 0); + chan->dma_dir = DMA_NONE; +} + +static int sf_pdma_slave_config(struct dma_chan *dchan, + struct dma_slave_config *cfg) +{ + struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan); + + memcpy(&chan->cfg, cfg, sizeof(*cfg)); + sf_pdma_unprep_slave_dma(chan); + + return 0; +} + +static int sf_pdma_alloc_chan_resources(struct dma_chan *dchan) +{ + struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan); + struct pdma_regs *regs = &chan->regs; + + dma_cookie_init(dchan); + writel(PDMA_CLAIM_MASK, regs->ctrl); + + return 0; +} + +static void sf_pdma_disable_request(struct sf_pdma_chan *chan) +{ + struct pdma_regs *regs = &chan->regs; + + writel(readl(regs->ctrl) & ~PDMA_RUN_MASK, regs->ctrl); +} + +static void sf_pdma_free_chan_resources(struct dma_chan *dchan) +{ + struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan); + unsigned long flags; + LIST_HEAD(head); + + spin_lock_irqsave(&chan->vchan.lock, flags); + sf_pdma_disable_request(chan); + kfree(chan->desc); + chan->desc = NULL; + vchan_get_all_descriptors(&chan->vchan, &head); + sf_pdma_unprep_slave_dma(chan); + vchan_dma_desc_free_list(&chan->vchan, &head); + sf_pdma_disclaim_chan(chan); + spin_unlock_irqrestore(&chan->vchan.lock, flags); +} + +static size_t sf_pdma_desc_residue(struct sf_pdma_chan *chan) +{ + struct pdma_regs *regs = &chan->regs; + u64 residue; + + residue = readq(regs->residue); + + return residue; +} + +static enum dma_status +sf_pdma_tx_status(struct dma_chan *dchan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan); + enum dma_status status; + unsigned long flags; + + spin_lock_irqsave(&chan->lock, flags); + if (chan->xfer_err) { + chan->status = DMA_ERROR; + spin_unlock_irqrestore(&chan->lock, flags); + return chan->status; + } + + spin_unlock_irqrestore(&chan->lock, flags); + + status = dma_cookie_status(dchan, cookie, txstate); + + if (txstate && status != DMA_ERROR) + dma_set_residue(txstate, sf_pdma_desc_residue(chan)); + + return status; +} + +static int sf_pdma_terminate_all(struct dma_chan *dchan) +{ + struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan); + unsigned long flags; + LIST_HEAD(head); + + spin_lock_irqsave(&chan->vchan.lock, flags); + sf_pdma_disable_request(chan); + kfree(chan->desc); + chan->desc = NULL; + chan->xfer_err = false; + vchan_get_all_descriptors(&chan->vchan, &head); + vchan_dma_desc_free_list(&chan->vchan, &head); + spin_unlock_irqrestore(&chan->vchan.lock, flags); + + return 0; +} + +static void sf_pdma_enable_request(struct sf_pdma_chan *chan) +{ + struct pdma_regs *regs = &chan->regs; + u32 v; + + v = PDMA_CLAIM_MASK | + PDMA_ENABLE_DONE_INT_MASK | + PDMA_ENABLE_ERR_INT_MASK | + PDMA_RUN_MASK; + + writel(v, regs->ctrl); +} + +static void sf_pdma_xfer_desc(struct sf_pdma_chan *chan) +{ + struct virt_dma_desc *vdesc; + + vdesc = vchan_next_desc(&chan->vchan); + if (!vdesc) + return; + + chan->desc = to_sf_pdma_desc(vdesc); + chan->status = DMA_IN_PROGRESS; +} + +static void sf_pdma_issue_pending(struct dma_chan *dchan) +{ + struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan); + unsigned long flags; + + spin_lock_irqsave(&chan->vchan.lock, flags); + + if (chan->pm_state != RUNNING) { + spin_unlock_irqrestore(&chan->vchan.lock, flags); + /* cannot submit due to suspend */ + return; + } + + if (vchan_issue_pending(&chan->vchan) && !chan->desc) + sf_pdma_xfer_desc(chan); + + sf_pdma_enable_request(chan); + spin_unlock_irqrestore(&chan->vchan.lock, flags); +} + +static void sf_pdma_free_desc(struct virt_dma_desc *vdesc) +{ + struct sf_pdma_desc *desc; + + desc = to_sf_pdma_desc(vdesc); + desc->in_use = false; +} + +static void sf_pdma_donebh_tasklet(unsigned long arg) +{ + struct sf_pdma_chan *chan = (struct sf_pdma_chan *)arg; + struct sf_pdma_desc *desc = chan->desc; + unsigned long flags; + + spin_lock_irqsave(&chan->vchan.lock, flags); + list_del(&chan->desc->vdesc.node); + vchan_cookie_complete(&chan->desc->vdesc); + spin_unlock_irqrestore(&chan->vchan.lock, flags); + + spin_lock_irqsave(&chan->lock, flags); + if (chan->xfer_err) { + chan->retries = MAX_RETRY; + chan->status = DMA_COMPLETE; + chan->xfer_err = false; + } + spin_unlock_irqrestore(&chan->lock, flags); + + dmaengine_desc_get_callback_invoke(desc->async_tx, NULL); +} + +static void sf_pdma_errbh_tasklet(unsigned long arg) +{ + struct sf_pdma_chan *chan = (struct sf_pdma_chan *)arg; + struct sf_pdma_desc *desc = chan->desc; + unsigned long flags; + + spin_lock_irqsave(&chan->lock, flags); + if (chan->retries <= 0) { + /* fail to recover, tx_status() is in DMA_ERROR */ + spin_unlock_irqrestore(&chan->lock, flags); + dmaengine_desc_get_callback_invoke(desc->async_tx, NULL); + } else { + /* retry */ + chan->retries--; + chan->xfer_err = true; + chan->status = DMA_ERROR; + + sf_pdma_enable_request(chan); + spin_unlock_irqrestore(&chan->lock, flags); + } +} + +static irqreturn_t sf_pdma_done_isr(int irq, void *dev_id) +{ + struct sf_pdma_chan *chan = dev_id; + struct pdma_regs *regs = &chan->regs; + unsigned long flags; + + spin_lock_irqsave(&chan->lock, flags); + writel((readl(regs->ctrl)) & ~PDMA_DONE_STATUS_MASK, regs->ctrl); + spin_unlock_irqrestore(&chan->lock, flags); + + tasklet_hi_schedule(&chan->done_tasklet); + + return IRQ_HANDLED; +} + +static irqreturn_t sf_pdma_err_isr(int irq, void *dev_id) +{ + struct sf_pdma_chan *chan = dev_id; + struct pdma_regs *regs = &chan->regs; + unsigned long flags; + + spin_lock_irqsave(&chan->lock, flags); + writel((readl(regs->ctrl)) & ~PDMA_ERR_STATUS_MASK, regs->ctrl); + spin_unlock_irqrestore(&chan->lock, flags); + + tasklet_schedule(&chan->err_tasklet); + + return IRQ_HANDLED; +} + +/** + * sf_pdma_irq_init() - Init PDMA IRQ Handlers + * @pdev: pointer of platform_device + * @pdma: pointer of PDMA engine. Caller should check NULL + * + * Initialize DONE and ERROR interrupt handler for 4 channels. Caller should + * make sure the pointer passed in are non-NULL. This function should be called + * only one time during the device probe. + * + * Context: Any context. + * + * Return: + * * 0 - OK to init all IRQ handlers + * * irq - Fail to retrieve from DT binding + * * -1 - Fail to call request_irq() + */ +static int sf_pdma_irq_init(struct platform_device *pdev, struct sf_pdma *pdma) +{ + int irq, r, i; + struct sf_pdma_chan *chan; + + for (i = 0; i < pdma->n_chans; i++) { + chan = &pdma->chans[i]; + + irq = platform_get_irq(pdev, i * 2); + if (irq < 0) { + dev_err(&pdev->dev, "Can't get pdma done irq.\n"); + return irq; + } + + r = devm_request_irq(&pdev->dev, irq, sf_pdma_done_isr, 0, + dev_name(&pdev->dev), (void *)chan); + if (r) { + dev_err(&pdev->dev, "Fail to attach done ISR: %d\n", r); + return -1; + } + + chan->txirq = irq; + + irq = platform_get_irq(pdev, (i * 2) + 1); + if (irq < 0) { + dev_err(&pdev->dev, "Can't get pdma err irq.\n"); + return irq; + } + + r = devm_request_irq(&pdev->dev, irq, sf_pdma_err_isr, 0, + dev_name(&pdev->dev), (void *)chan); + if (r) { + dev_err(&pdev->dev, "Fail to attach err ISR: %d\n", r); + return -1; + } + + chan->errirq = irq; + } + + return 0; +} + +/** + * sf_pdma_setup_chans() - Init settings of each channel + * @pdma: pointer of PDMA engine. Caller should check NULL + * + * Initialize all data structure and register base. Caller should make sure + * the pointer passed in are non-NULL. This function should be called only + * one time during the device probe. + * + * Context: Any context. + * + * Return: none + */ +#define SF_PDMA_REG_BASE(ch) (pdma->membase + (PDMA_CHAN_OFFSET * (ch))) +static void sf_pdma_setup_chans(struct sf_pdma *pdma) +{ + int i; + struct sf_pdma_chan *chan; + + INIT_LIST_HEAD(&pdma->dma_dev.channels); + + for (i = 0; i < pdma->n_chans; i++) { + chan = &pdma->chans[i]; + + chan->regs.ctrl = + SF_PDMA_REG_BASE(i) + PDMA_CTRL; + chan->regs.xfer_type = + SF_PDMA_REG_BASE(i) + PDMA_XFER_TYPE; + chan->regs.xfer_size = + SF_PDMA_REG_BASE(i) + PDMA_XFER_SIZE; + chan->regs.dst_addr = + SF_PDMA_REG_BASE(i) + PDMA_DST_ADDR; + chan->regs.src_addr = + SF_PDMA_REG_BASE(i) + PDMA_SRC_ADDR; + chan->regs.act_type = + SF_PDMA_REG_BASE(i) + PDMA_ACT_TYPE; + chan->regs.residue = + SF_PDMA_REG_BASE(i) + PDMA_REMAINING_BYTE; + chan->regs.cur_dst_addr = + SF_PDMA_REG_BASE(i) + PDMA_CUR_DST_ADDR; + chan->regs.cur_src_addr = + SF_PDMA_REG_BASE(i) + PDMA_CUR_SRC_ADDR; + + chan->pdma = pdma; + chan->pm_state = RUNNING; + chan->slave_id = i; + chan->xfer_err = false; + spin_lock_init(&chan->lock); + + chan->vchan.desc_free = sf_pdma_free_desc; + vchan_init(&chan->vchan, &pdma->dma_dev); + + writel(PDMA_CLEAR_CTRL, chan->regs.ctrl); + + tasklet_init(&chan->done_tasklet, + sf_pdma_donebh_tasklet, (unsigned long)chan); + tasklet_init(&chan->err_tasklet, + sf_pdma_errbh_tasklet, (unsigned long)chan); + } +} + +static int sf_pdma_probe(struct platform_device *pdev) +{ + struct sf_pdma *pdma; + struct sf_pdma_chan *chan; + struct resource *res; + int len, chans; + int ret; + + chans = PDMA_NR_CH; + len = sizeof(*pdma) + sizeof(*chan) * chans; + pdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); + if (!pdma) + return -ENOMEM; + + pdma->n_chans = chans; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pdma->membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pdma->membase)) + goto ERR_MEMBASE; + + ret = sf_pdma_irq_init(pdev, pdma); + if (ret) + goto ERR_INITIRQ; + + sf_pdma_setup_chans(pdma); + + pdma->dma_dev.dev = &pdev->dev; + dma_cap_set(DMA_MEMCPY, pdma->dma_dev.cap_mask); + + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); + if (ret) + pr_warn("*** Failed to set DMA mask. Fall back to default.\n"); + + /* Setup DMA APIs */ + pdma->dma_dev.device_alloc_chan_resources = + sf_pdma_alloc_chan_resources; + pdma->dma_dev.device_free_chan_resources = + sf_pdma_free_chan_resources; + pdma->dma_dev.device_tx_status = sf_pdma_tx_status; + pdma->dma_dev.device_prep_dma_memcpy = sf_pdma_prep_dma_memcpy; + pdma->dma_dev.device_config = sf_pdma_slave_config; + pdma->dma_dev.device_terminate_all = sf_pdma_terminate_all; + pdma->dma_dev.device_issue_pending = sf_pdma_issue_pending; + + platform_set_drvdata(pdev, pdma); + + ret = dma_async_device_register(&pdma->dma_dev); + if (ret) + goto ERR_REG_DMADEVICE; + + return 0; + +ERR_MEMBASE: + devm_kfree(&pdev->dev, pdma); + return PTR_ERR(pdma->membase); + +ERR_INITIRQ: + devm_kfree(&pdev->dev, pdma); + return ret; + +ERR_REG_DMADEVICE: + devm_kfree(&pdev->dev, pdma); + dev_err(&pdev->dev, + "Can't register SiFive Platform DMA. (%d)\n", ret); + return ret; +} + +static int sf_pdma_remove(struct platform_device *pdev) +{ + struct sf_pdma *pdma = platform_get_drvdata(pdev); + + dma_async_device_unregister(&pdma->dma_dev); + + return 0; +} + +static const struct of_device_id sf_pdma_of_match[] = { + { .compatible = "sifive,fu540-c000-pdma" }, + {}, +}; +MODULE_DEVICE_TABLE(of, sifive_serial_of_match); + +static struct platform_driver sf_pdma_driver = { + .probe = sf_pdma_probe, + .remove = sf_pdma_remove, + .driver = { + .name = SIFIVE_PDMA_NAME, + .of_match_table = of_match_ptr(sf_pdma_of_match), + }, +}; + +static int __init sf_pdma_init(void) +{ + return platform_driver_register(&sf_pdma_driver); +} + +static void __exit sf_pdma_exit(void) +{ + platform_driver_unregister(&sf_pdma_driver); +} + +/* do early init */ +subsys_initcall(sf_pdma_init); +module_exit(sf_pdma_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("SiFive Platform DMA driver"); +MODULE_AUTHOR("Green Wan <green.wan@sifive.com>"); diff --git a/drivers/dma/sf-pdma/sf-pdma.h b/drivers/dma/sf-pdma/sf-pdma.h new file mode 100644 index 000000000000..d577d5af0bf4 --- /dev/null +++ b/drivers/dma/sf-pdma/sf-pdma.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/** + * SiFive FU540 Platform DMA driver + * Copyright (C) 2019 SiFive + * + * Based partially on: + * - drivers/dma/fsl-edma.c + * - drivers/dma/dw-edma/ + * - drivers/dma/pxa-dma.c + * + * See the following sources for further documentation: + * - Chapter 12 "Platform DMA Engine (PDMA)" of + * SiFive FU540-C000 v1.0 + * https://static.dev.sifive.com/FU540-C000-v1.0.pdf + */ +#ifndef _SF_PDMA_H +#define _SF_PDMA_H + +#include <linux/msi.h> +#include <linux/dmaengine.h> +#include <linux/dma-direction.h> +#include <linux/timer.h> +#include <linux/time64.h> +#include <linux/timekeeping.h> +#include <linux/workqueue.h> + +#include "../dmaengine.h" +#include "../virt-dma.h" + +#define PDMA_NR_CH 4 + +#if (PDMA_NR_CH != 4) +#error "Please define PDMA_NR_CH to 4" +#endif + +#define PDMA_BASE_ADDR 0x3000000 +#define PDMA_CHAN_OFFSET 0x1000 + +/* Register Offset */ +#define PDMA_CTRL 0x000 +#define PDMA_XFER_TYPE 0x004 +#define PDMA_XFER_SIZE 0x008 +#define PDMA_DST_ADDR 0x010 +#define PDMA_SRC_ADDR 0x018 +#define PDMA_ACT_TYPE 0x104 /* Read-only */ +#define PDMA_REMAINING_BYTE 0x108 /* Read-only */ +#define PDMA_CUR_DST_ADDR 0x110 /* Read-only*/ +#define PDMA_CUR_SRC_ADDR 0x118 /* Read-only*/ + +/* CTRL */ +#define PDMA_CLEAR_CTRL 0x0 +#define PDMA_CLAIM_MASK GENMASK(0, 0) +#define PDMA_RUN_MASK GENMASK(1, 1) +#define PDMA_ENABLE_DONE_INT_MASK GENMASK(14, 14) +#define PDMA_ENABLE_ERR_INT_MASK GENMASK(15, 15) +#define PDMA_DONE_STATUS_MASK GENMASK(30, 30) +#define PDMA_ERR_STATUS_MASK GENMASK(31, 31) + +/* Transfer Type */ +#define PDMA_FULL_SPEED 0xFF000008 + +/* Error Recovery */ +#define MAX_RETRY 1 + +struct pdma_regs { + /* read-write regs */ + void __iomem *ctrl; /* 4 bytes */ + + void __iomem *xfer_type; /* 4 bytes */ + void __iomem *xfer_size; /* 8 bytes */ + void __iomem *dst_addr; /* 8 bytes */ + void __iomem *src_addr; /* 8 bytes */ + + /* read-only */ + void __iomem *act_type; /* 4 bytes */ + void __iomem *residue; /* 8 bytes */ + void __iomem *cur_dst_addr; /* 8 bytes */ + void __iomem *cur_src_addr; /* 8 bytes */ +}; + +struct sf_pdma_desc { + struct virt_dma_desc vdesc; + struct sf_pdma_chan *chan; + bool in_use; + enum dma_transfer_direction dirn; + struct dma_async_tx_descriptor *async_tx; +}; + +enum sf_pdma_pm_state { + RUNNING = 0, + SUSPENDED, +}; + +struct sf_pdma_chan { + struct virt_dma_chan vchan; + enum dma_status status; + enum sf_pdma_pm_state pm_state; + u32 slave_id; + struct sf_pdma *pdma; + struct sf_pdma_desc *desc; + struct dma_slave_config cfg; + u32 attr; + dma_addr_t dma_dev_addr; + u32 dma_dev_size; + enum dma_data_direction dma_dir; + struct tasklet_struct done_tasklet; + struct tasklet_struct err_tasklet; + struct pdma_regs regs; + spinlock_t lock; /* protect chan data */ + bool xfer_err; + int txirq; + int errirq; + int retries; +}; + +struct sf_pdma { + struct dma_device dma_dev; + void __iomem *membase; + void __iomem *mappedbase; + u32 n_chans; + struct sf_pdma_chan chans[PDMA_NR_CH]; +}; + +#endif /* _SF_PDMA_H */ -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [RFC PATCH] dmaengine: sf-pdma: sf_pdma_disclaim_chan() can be static 2019-10-03 9:09 ` [PATCH v4 3/4] dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 Green Wan @ 2019-10-13 13:04 ` kbuild test robot 2019-10-13 13:04 ` [PATCH v4 3/4] dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 kbuild test robot 2019-10-20 13:59 ` Vinod Koul 2 siblings, 0 replies; 9+ messages in thread From: kbuild test robot @ 2019-10-13 13:04 UTC (permalink / raw) To: Green Wan Cc: Mark Rutland, Palmer Dabbelt, Sagar Kadam, Mauro Carvalho Chehab, linux-riscv, Paul E. McKenney, Vinod Koul, linux-hackers, devicetree, Albert Ou, Green Wan, Rob Herring, Paul Walmsley, Jonathan Cameron, Dan Williams, kbuild-all, Greg Kroah-Hartman, linux-kernel, Yash Shah, dmaengine, Bin Meng, David S. Miller Fixes: 31c3b98b5a01 ("dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00") Signed-off-by: kbuild test robot <lkp@intel.com> --- sf-pdma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/sf-pdma/sf-pdma.c b/drivers/dma/sf-pdma/sf-pdma.c index 70197ad95c1a6..973ed9d8cfa44 100644 --- a/drivers/dma/sf-pdma/sf-pdma.c +++ b/drivers/dma/sf-pdma/sf-pdma.c @@ -97,14 +97,14 @@ static void sf_pdma_fill_desc(struct sf_pdma_chan *chan, writeq(src, regs->src_addr); } -void sf_pdma_disclaim_chan(struct sf_pdma_chan *chan) +static void sf_pdma_disclaim_chan(struct sf_pdma_chan *chan) { struct pdma_regs *regs = &chan->regs; writel(PDMA_CLEAR_CTRL, regs->ctrl); } -struct dma_async_tx_descriptor * +static struct dma_async_tx_descriptor * sf_pdma_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dest, dma_addr_t src, _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v4 3/4] dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 2019-10-03 9:09 ` [PATCH v4 3/4] dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 Green Wan 2019-10-13 13:04 ` [RFC PATCH] dmaengine: sf-pdma: sf_pdma_disclaim_chan() can be static kbuild test robot @ 2019-10-13 13:04 ` kbuild test robot 2019-10-20 13:59 ` Vinod Koul 2 siblings, 0 replies; 9+ messages in thread From: kbuild test robot @ 2019-10-13 13:04 UTC (permalink / raw) To: Green Wan Cc: Mark Rutland, Palmer Dabbelt, Sagar Kadam, Mauro Carvalho Chehab, linux-riscv, Paul E. McKenney, Vinod Koul, linux-hackers, devicetree, Albert Ou, Green Wan, Rob Herring, Paul Walmsley, Jonathan Cameron, Dan Williams, kbuild-all, Greg Kroah-Hartman, linux-kernel, Yash Shah, dmaengine, Bin Meng, David S. Miller Hi Green, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on linus/master] [cannot apply to v5.4-rc2 next-20191011] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Green-Wan/dmaengine-sf-pdma-Add-platform-dma-driver/20191003-172343 reproduce: # apt-get install sparse # sparse version: v0.6.1-rc1-43-g0ccb3b4-dirty make ARCH=x86_64 allmodconfig make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' If you fix the issue, kindly add following tag Reported-by: kbuild test robot <lkp@intel.com> sparse warnings: (new ones prefixed by >>) >> drivers/dma/sf-pdma/sf-pdma.c:100:6: sparse: sparse: symbol 'sf_pdma_disclaim_chan' was not declared. Should it be static? >> drivers/dma/sf-pdma/sf-pdma.c:107:32: sparse: sparse: symbol 'sf_pdma_prep_dma_memcpy' was not declared. Should it be static? Please review and possibly fold the followup patch. --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v4 3/4] dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 2019-10-03 9:09 ` [PATCH v4 3/4] dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 Green Wan 2019-10-13 13:04 ` [RFC PATCH] dmaengine: sf-pdma: sf_pdma_disclaim_chan() can be static kbuild test robot 2019-10-13 13:04 ` [PATCH v4 3/4] dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 kbuild test robot @ 2019-10-20 13:59 ` Vinod Koul 2 siblings, 0 replies; 9+ messages in thread From: Vinod Koul @ 2019-10-20 13:59 UTC (permalink / raw) To: Green Wan Cc: Mark Rutland, devicetree, Albert Ou, Greg Kroah-Hartman, Palmer Dabbelt, linux-kernel, linux-riscv, Bin Meng, dmaengine, Yash Shah, Rob Herring, Sagar Kadam, Jonathan Cameron, Paul Walmsley, Mauro Carvalho Chehab, linux-hackers, Dan Williams, Paul E. McKenney, David S. Miller On 03-10-19, 17:09, Green Wan wrote: > diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig > index 7af874b69ffb..03dc82094857 100644 > --- a/drivers/dma/Kconfig > +++ b/drivers/dma/Kconfig > @@ -661,6 +661,8 @@ source "drivers/dma/qcom/Kconfig" > > source "drivers/dma/dw/Kconfig" > > +source "drivers/dma/sf-pdma/Kconfig" Please keep this in sorted order > + > source "drivers/dma/dw-edma/Kconfig" > > source "drivers/dma/hsu/Kconfig" > diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile > index f5ce8665e944..4bbd90563ede 100644 > --- a/drivers/dma/Makefile > +++ b/drivers/dma/Makefile > @@ -28,6 +28,7 @@ obj-$(CONFIG_DMA_SUN4I) += sun4i-dma.o > obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o > obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac/ > obj-$(CONFIG_DW_DMAC_CORE) += dw/ > +obj-$(CONFIG_SF_PDMA) += sf-pdma/ here as well! > obj-$(CONFIG_DW_EDMA) += dw-edma/ > obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o > obj-$(CONFIG_FSL_DMA) += fsldma.o > diff --git a/drivers/dma/sf-pdma/Kconfig b/drivers/dma/sf-pdma/Kconfig > new file mode 100644 > index 000000000000..0e01a5728a79 > --- /dev/null > +++ b/drivers/dma/sf-pdma/Kconfig > @@ -0,0 +1,6 @@ > +config SF_PDMA > + bool "Sifive PDMA controller driver" why not a module? > +#include <linux/module.h> > +#include <linux/device.h> > +#include <linux/kernel.h> > +#include <linux/pm_runtime.h> > +#include <linux/dmaengine.h> > +#include <linux/err.h> > +#include <linux/interrupt.h> > +#include <linux/dma-mapping.h> > +#include <linux/irq.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/of_address.h> > +#include <linux/of_irq.h> > +#include <linux/of_dma.h> do you need all the headers? > +#include <linux/time64.h> why is this required? > + > +#include "sf-pdma.h" > +#include "../dmaengine.h" > +#include "../virt-dma.h" > + > +#define SIFIVE_PDMA_NAME "sf-pdma" this is used only once! can you use it directly to help readability! > + > +#ifndef readq > +static inline unsigned long long readq(void __iomem *addr) > +{ > + return readl(addr) | (((unsigned long long)readl(addr + 4)) << 32LL); > +} > +#endif > + > +#ifndef writeq > +static inline void writeq(unsigned long long v, void __iomem *addr) > +{ > + writel(v & 0xffffffff, addr); > + writel(v >> 32, addr + 4); why not use upper/lower_32_bits? > +static void sf_pdma_fill_desc(struct sf_pdma_chan *chan, > + u64 dst, > + u64 src, > + u64 size) these can fit in a line! > +struct dma_async_tx_descriptor * > + sf_pdma_prep_dma_memcpy(struct dma_chan *dchan, > + dma_addr_t dest, > + dma_addr_t src, > + size_t len, > + unsigned long flags) > +{ > + struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan); > + struct sf_pdma_desc *desc; > + > + if (!chan || !len || !dest || !src) { > + pr_debug("%s: Please check dma len, dest, src!\n", __func__); why pr_debug() and not dev_debug(), bonus you get the device name in each print! and this should be an error print! > +static void sf_pdma_unprep_slave_dma(struct sf_pdma_chan *chan) > +{ > + if (chan->dma_dir != DMA_NONE) > + dma_unmap_resource(chan->vchan.chan.device->dev, > + chan->dma_dev_addr, > + chan->dma_dev_size, > + chan->dma_dir, 0); this does not seem correct to me, in slave cases the client is supposed to take care of mapping and unmapping, why is this being done here? > + chan->dma_dir = DMA_NONE; > +} > + > +static int sf_pdma_slave_config(struct dma_chan *dchan, > + struct dma_slave_config *cfg) > +{ > + struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan); > + > + memcpy(&chan->cfg, cfg, sizeof(*cfg)); > + sf_pdma_unprep_slave_dma(chan); why unmap! > +static enum dma_status > +sf_pdma_tx_status(struct dma_chan *dchan, > + dma_cookie_t cookie, > + struct dma_tx_state *txstate) > +{ > + struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan); > + enum dma_status status; > + unsigned long flags; > + > + spin_lock_irqsave(&chan->lock, flags); > + if (chan->xfer_err) { > + chan->status = DMA_ERROR; > + spin_unlock_irqrestore(&chan->lock, flags); > + return chan->status; well this is not correct! The status is queried for a descriptor and we might have that succeeded so returning error of a channel for descriptor does not make sense! > +static irqreturn_t sf_pdma_done_isr(int irq, void *dev_id) > +{ > + struct sf_pdma_chan *chan = dev_id; > + struct pdma_regs *regs = &chan->regs; > + unsigned long flags; > + > + spin_lock_irqsave(&chan->lock, flags); > + writel((readl(regs->ctrl)) & ~PDMA_DONE_STATUS_MASK, regs->ctrl); > + spin_unlock_irqrestore(&chan->lock, flags); why not submit next transaction here? This is DMA so we do care about utilizing it! > +static int sf_pdma_irq_init(struct platform_device *pdev, struct sf_pdma *pdma) > +{ > + int irq, r, i; > + struct sf_pdma_chan *chan; > + > + for (i = 0; i < pdma->n_chans; i++) { > + chan = &pdma->chans[i]; > + > + irq = platform_get_irq(pdev, i * 2); > + if (irq < 0) { > + dev_err(&pdev->dev, "Can't get pdma done irq.\n"); > + return irq; > + } > + > + r = devm_request_irq(&pdev->dev, irq, sf_pdma_done_isr, 0, > + dev_name(&pdev->dev), (void *)chan); > + if (r) { > + dev_err(&pdev->dev, "Fail to attach done ISR: %d\n", r); > + return -1; -1 :( > +static int sf_pdma_probe(struct platform_device *pdev) > +{ > + struct sf_pdma *pdma; > + struct sf_pdma_chan *chan; > + struct resource *res; > + int len, chans; > + int ret; > + > + chans = PDMA_NR_CH; > + len = sizeof(*pdma) + sizeof(*chan) * chans; > + pdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); > + if (!pdma) > + return -ENOMEM; > + > + pdma->n_chans = chans; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + pdma->membase = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(pdma->membase)) > + goto ERR_MEMBASE; > + > + ret = sf_pdma_irq_init(pdev, pdma); > + if (ret) > + goto ERR_INITIRQ; > + > + sf_pdma_setup_chans(pdma); > + > + pdma->dma_dev.dev = &pdev->dev; > + dma_cap_set(DMA_MEMCPY, pdma->dma_dev.cap_mask); > + > + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); > + if (ret) > + pr_warn("*** Failed to set DMA mask. Fall back to default.\n"); > + > + /* Setup DMA APIs */ > + pdma->dma_dev.device_alloc_chan_resources = > + sf_pdma_alloc_chan_resources; > + pdma->dma_dev.device_free_chan_resources = > + sf_pdma_free_chan_resources; > + pdma->dma_dev.device_tx_status = sf_pdma_tx_status; > + pdma->dma_dev.device_prep_dma_memcpy = sf_pdma_prep_dma_memcpy; > + pdma->dma_dev.device_config = sf_pdma_slave_config; > + pdma->dma_dev.device_terminate_all = sf_pdma_terminate_all; > + pdma->dma_dev.device_issue_pending = sf_pdma_issue_pending; please set the capabilities of the controller, width, direction, granularity etc! > +static int sf_pdma_remove(struct platform_device *pdev) > +{ > + struct sf_pdma *pdma = platform_get_drvdata(pdev); > + > + dma_async_device_unregister(&pdma->dma_dev); since you used devm_irq_() you have irq which is running, tasklets which maybe schedule and can be scheduled again including the vchan one! -- ~Vinod _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4 4/4] MAINTAINERS: Add Green as SiFive PDMA driver maintainer 2019-10-03 9:09 [PATCH v4 0/4] dmaengine: sf-pdma: Add platform dma driver Green Wan ` (2 preceding siblings ...) 2019-10-03 9:09 ` [PATCH v4 3/4] dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 Green Wan @ 2019-10-03 9:09 ` Green Wan 3 siblings, 0 replies; 9+ messages in thread From: Green Wan @ 2019-10-03 9:09 UTC (permalink / raw) To: linux-hackers Cc: Mark Rutland, devicetree, Albert Ou, Greg Kroah-Hartman, Linus Walleij, Palmer Dabbelt, Yash Shah, Green Wan, Bin Meng, dmaengine, Vinod Koul, Rob Herring, Sagar Kadam, Paul Walmsley, Mauro Carvalho Chehab, Dan Williams, Paul E. McKenney, linux-riscv, David S. Miller, linux-kernel Update MAINTAINERS for SiFive PDMA driver. Signed-off-by: Green Wan <green.wan@sifive.com> --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 30a5b4028d2f..6c12da0a324d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14779,6 +14779,12 @@ F: drivers/media/usb/siano/ F: drivers/media/usb/siano/ F: drivers/media/mmc/siano/ +SIFIVE PDMA DRIVER +M: Green Wan <green.wan@sifive.com> +S: Maintained +F: drivers/dma/sf-pdma/ +F: Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml + SIFIVE DRIVERS M: Palmer Dabbelt <palmer@sifive.com> M: Paul Walmsley <paul.walmsley@sifive.com> -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2019-10-20 14:00 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-10-03 9:09 [PATCH v4 0/4] dmaengine: sf-pdma: Add platform dma driver Green Wan 2019-10-03 9:09 ` [PATCH v4 1/4] dt-bindings: dmaengine: sf-pdma: add bindins for SiFive PDMA Green Wan 2019-10-09 23:34 ` Rob Herring 2019-10-03 9:09 ` [PATCH v4 2/4] riscv: dts: add support for PDMA device of HiFive Unleashed Rev A00 Green Wan 2019-10-03 9:09 ` [PATCH v4 3/4] dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 Green Wan 2019-10-13 13:04 ` [RFC PATCH] dmaengine: sf-pdma: sf_pdma_disclaim_chan() can be static kbuild test robot 2019-10-13 13:04 ` [PATCH v4 3/4] dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 kbuild test robot 2019-10-20 13:59 ` Vinod Koul 2019-10-03 9:09 ` [PATCH v4 4/4] MAINTAINERS: Add Green as SiFive PDMA driver maintainer Green Wan
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