From: Marc Gauthier <consult-mg@gstardust.com>
To: linux-riscv@lists.infradead.org
Cc: Marc Gauthier <consult-mg@gstardust.com>
Subject: [PATCH 0/2] riscv: Align shared mappings to avoid cache aliasing
Date: Fri, 15 Nov 2019 14:23:52 -0500 [thread overview]
Message-ID: <20191115192354.19814-1-consult-mg@gstardust.com> (raw)
Ensure optimal performance on larger VIPT caches by aligning shared
mappings to the maximum cache "span" (line size * number of sets) of
all CPU L1 instruction and data caches (L2 and up are rarely VIPT).
If the device tree does not provide cache parameters, use a conservative
16 KB alignment: only large enough to avoid aliasing in most VIPT caches.
Tested on Linux 5.4-rc7 in simulation.
Signed-off-by: Marc Gauthier <consult-mg@gstardust.com>
Marc Gauthier (2):
riscv: Align shared mappings to SHMLBA
riscv: Set SHMLBA according to cache geometry
arch/riscv/include/asm/pgtable.h | 4 ++
arch/riscv/include/asm/shmparam.h | 12 ++++
arch/riscv/kernel/cacheinfo.c | 49 +++++++++++++
arch/riscv/kernel/sys_riscv.c | 112 ++++++++++++++++++++++++++++++
4 files changed, 177 insertions(+)
create mode 100644 arch/riscv/include/asm/shmparam.h
--
2.17.1
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next reply other threads:[~2019-11-15 19:24 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-15 19:23 Marc Gauthier [this message]
2019-11-15 19:23 ` [PATCH 1/2] riscv: Align shared mappings to SHMLBA Marc Gauthier
2019-11-15 19:23 ` [PATCH 2/2] riscv: Set SHMLBA according to cache geometry Marc Gauthier
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