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Fri, 15 Nov 2019 14:24:24 -0500 (EST) From: Marc Gauthier To: linux-riscv@lists.infradead.org Subject: [PATCH 0/2] riscv: Align shared mappings to avoid cache aliasing Date: Fri, 15 Nov 2019 14:23:52 -0500 Message-Id: <20191115192354.19814-1-consult-mg@gstardust.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191115_112431_835486_E240A7AE X-CRM114-Status: UNSURE ( 4.29 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Gauthier MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org Ensure optimal performance on larger VIPT caches by aligning shared mappings to the maximum cache "span" (line size * number of sets) of all CPU L1 instruction and data caches (L2 and up are rarely VIPT). If the device tree does not provide cache parameters, use a conservative 16 KB alignment: only large enough to avoid aliasing in most VIPT caches. Tested on Linux 5.4-rc7 in simulation. Signed-off-by: Marc Gauthier Marc Gauthier (2): riscv: Align shared mappings to SHMLBA riscv: Set SHMLBA according to cache geometry arch/riscv/include/asm/pgtable.h | 4 ++ arch/riscv/include/asm/shmparam.h | 12 ++++ arch/riscv/kernel/cacheinfo.c | 49 +++++++++++++ arch/riscv/kernel/sys_riscv.c | 112 ++++++++++++++++++++++++++++++ 4 files changed, 177 insertions(+) create mode 100644 arch/riscv/include/asm/shmparam.h -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv