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Mon, 23 Dec 2019 11:35:20 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Albert Ou , Paolo Bonzini , Radim K Subject: [PATCH v10 02/19] RISC-V: Add bitmap reprensenting ISA features common across CPUs Thread-Topic: [PATCH v10 02/19] RISC-V: Add bitmap reprensenting ISA features common across CPUs Thread-Index: AQHVuYUS5IbGQwTUD021jPt6po1ITw== Date: Mon, 23 Dec 2019 11:35:26 +0000 Message-ID: <20191223113443.68969-3-anup.patel@wdc.com> References: <20191223113443.68969-1-anup.patel@wdc.com> In-Reply-To: <20191223113443.68969-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MA1PR01CA0077.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00::17) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [106.51.20.238] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 8f4fbf9c-8726-400c-7ca0-08d7879c348b x-ms-traffictypediagnostic: MN2PR04MB7072: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: wdcipoutbound: EOP-TRUE x-ms-oob-tlc-oobclassifiers: OLM:317; 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The riscv_isa is not same as elf_hwcap because elf_hwcap will only have ISA features relevant for user-space apps whereas riscv_isa will have ISA features relevant to both kernel and user-space apps. One of the use-case for riscv_isa bitmap is in KVM hypervisor where we will use it to do following operations: 1. Check whether hypervisor extension is available 2. Find ISA features that need to be virtualized (e.g. floating point support, vector extension, etc.) Signed-off-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Alexander Graf --- arch/riscv/include/asm/hwcap.h | 22 +++++++++ arch/riscv/kernel/cpufeature.c | 83 ++++++++++++++++++++++++++++++++-- 2 files changed, 102 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.= h index 1bb0cd04aec3..5589c012e004 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -8,6 +8,7 @@ #ifndef _ASM_RISCV_HWCAP_H #define _ASM_RISCV_HWCAP_H =20 +#include #include =20 #ifndef __ASSEMBLY__ @@ -22,6 +23,27 @@ enum { }; =20 extern unsigned long elf_hwcap; + +#define RISCV_ISA_EXT_a ('a' - 'a') +#define RISCV_ISA_EXT_c ('c' - 'a') +#define RISCV_ISA_EXT_d ('d' - 'a') +#define RISCV_ISA_EXT_f ('f' - 'a') +#define RISCV_ISA_EXT_h ('h' - 'a') +#define RISCV_ISA_EXT_i ('i' - 'a') +#define RISCV_ISA_EXT_m ('m' - 'a') +#define RISCV_ISA_EXT_s ('s' - 'a') +#define RISCV_ISA_EXT_u ('u' - 'a') + +#define RISCV_ISA_EXT_MAX 256 + +unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); + +#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) + +bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int = bit); +#define riscv_isa_extension_available(isa_bitmap, ext) \ + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext) + #endif =20 #endif /* _ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.= c index 0b40705567b7..e172a2322b34 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -6,6 +6,7 @@ * Copyright (C) 2017 SiFive */ =20 +#include #include #include #include @@ -13,15 +14,57 @@ #include =20 unsigned long elf_hwcap __read_mostly; + +/* Host ISA bitmap */ +static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; + #ifdef CONFIG_FPU bool has_fpu __read_mostly; #endif =20 +/** + * riscv_isa_extension_base() - Get base extension word + * + * @isa_bitmap: ISA bitmap to use + * Return: base extension word as unsigned long value + * + * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used. + */ +unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap) +{ + if (!isa_bitmap) + return riscv_isa[0]; + return isa_bitmap[0]; +} +EXPORT_SYMBOL_GPL(riscv_isa_extension_base); + +/** + * __riscv_isa_extension_available() - Check whether given extension + * is available or not + * + * @isa_bitmap: ISA bitmap to use + * @bit: bit position of the desired extension + * Return: true or false + * + * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used. + */ +bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int = bit) +{ + const unsigned long *bmap =3D (isa_bitmap) ? isa_bitmap : riscv_isa; + + if (bit >=3D RISCV_ISA_EXT_MAX) + return false; + + return test_bit(bit, bmap) ? true : false; +} +EXPORT_SYMBOL_GPL(__riscv_isa_extension_available); + void riscv_fill_hwcap(void) { struct device_node *node; const char *isa; - size_t i; + char print_str[BITS_PER_LONG + 1]; + size_t i, j, isa_len; static unsigned long isa2hwcap[256] =3D {0}; =20 isa2hwcap['i'] =3D isa2hwcap['I'] =3D COMPAT_HWCAP_ISA_I; @@ -33,8 +76,11 @@ void riscv_fill_hwcap(void) =20 elf_hwcap =3D 0; =20 + bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); + for_each_of_cpu_node(node) { unsigned long this_hwcap =3D 0; + unsigned long this_isa =3D 0; =20 if (riscv_of_processor_hartid(node) < 0) continue; @@ -42,8 +88,24 @@ void riscv_fill_hwcap(void) if (riscv_read_check_isa(node, &isa) < 0) continue; =20 - for (i =3D 0; i < strlen(isa); ++i) + i =3D 0; + isa_len =3D strlen(isa); +#if IS_ENABLED(CONFIG_32BIT) + if (!strncmp(isa, "rv32", 4)) + i +=3D 4; +#elif IS_ENABLED(CONFIG_64BIT) + if (!strncmp(isa, "rv64", 4)) + i +=3D 4; +#endif + for (; i < isa_len; ++i) { this_hwcap |=3D isa2hwcap[(unsigned char)(isa[i])]; + /* + * TODO: X, Y and Z extension parsing for Host ISA + * bitmap will be added in-future. + */ + if ('a' <=3D isa[i] && isa[i] < 'x') + this_isa |=3D (1UL << (isa[i] - 'a')); + } =20 /* * All "okay" hart should have same isa. Set HWCAP based on @@ -54,6 +116,11 @@ void riscv_fill_hwcap(void) elf_hwcap &=3D this_hwcap; else elf_hwcap =3D this_hwcap; + + if (riscv_isa[0]) + riscv_isa[0] &=3D this_isa; + else + riscv_isa[0] =3D this_isa; } =20 /* We don't support systems with F but without D, so mask those out @@ -63,7 +130,17 @@ void riscv_fill_hwcap(void) elf_hwcap &=3D ~COMPAT_HWCAP_ISA_F; } =20 - pr_info("elf_hwcap is 0x%lx\n", elf_hwcap); + memset(print_str, 0, sizeof(print_str)); + for (i =3D 0, j =3D 0; i < BITS_PER_LONG; i++) + if (riscv_isa[0] & BIT_MASK(i)) + print_str[j++] =3D (char)('a' + i); + pr_info("riscv: ISA extensions %s\n", print_str); + + memset(print_str, 0, sizeof(print_str)); + for (i =3D 0, j =3D 0; i < BITS_PER_LONG; i++) + if (elf_hwcap & BIT_MASK(i)) + print_str[j++] =3D (char)('a' + i); + pr_info("riscv: ELF capabilities %s\n", print_str); =20 #ifdef CONFIG_FPU if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) --=20 2.17.1