* [PATCH] riscv: gcov: enable gcov for RISC-V
@ 2020-01-02 3:09 Zong Li
2020-01-02 3:37 ` Anup Patel
2020-01-04 0:11 ` Paul Walmsley
0 siblings, 2 replies; 5+ messages in thread
From: Zong Li @ 2020-01-02 3:09 UTC (permalink / raw)
To: corbet, paul.walmsley, palmer, aou, linux-doc, linux-kernel, linux-riscv
Cc: Zong Li
This patch enables GCOV code coverage measurement on RISC-V.
Lightly tested on QEMU and Hifive Unleashed board, seems to work as
expected.
Signed-off-by: Zong Li <zong.li@sifive.com>
---
Documentation/features/debug/gcov-profile-all/arch-support.txt | 2 +-
arch/riscv/Kconfig | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/features/debug/gcov-profile-all/arch-support.txt b/Documentation/features/debug/gcov-profile-all/arch-support.txt
index 059d58a549c7..6fb2b0671994 100644
--- a/Documentation/features/debug/gcov-profile-all/arch-support.txt
+++ b/Documentation/features/debug/gcov-profile-all/arch-support.txt
@@ -23,7 +23,7 @@
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
- | riscv: | TODO |
+ | riscv: | ok |
| s390: | ok |
| sh: | ok |
| sparc: | TODO |
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index d8efbaa78d67..a31169b02ec0 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -64,6 +64,7 @@ config RISCV
select SPARSEMEM_STATIC if 32BIT
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
select HAVE_ARCH_MMAP_RND_BITS if MMU
+ select ARCH_HAS_GCOV_PROFILE_ALL
config ARCH_MMAP_RND_BITS_MIN
default 18 if 64BIT
--
2.24.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: gcov: enable gcov for RISC-V
2020-01-02 3:09 [PATCH] riscv: gcov: enable gcov for RISC-V Zong Li
@ 2020-01-02 3:37 ` Anup Patel
2020-01-02 3:47 ` Zong Li
2020-01-02 14:59 ` Jonathan Corbet
2020-01-04 0:11 ` Paul Walmsley
1 sibling, 2 replies; 5+ messages in thread
From: Anup Patel @ 2020-01-02 3:37 UTC (permalink / raw)
To: Zong Li
Cc: Albert Ou, linux-doc, corbet, linux-kernel@vger.kernel.org List,
Palmer Dabbelt, Paul Walmsley, linux-riscv
On Thu, Jan 2, 2020 at 8:40 AM Zong Li <zong.li@sifive.com> wrote:
>
> This patch enables GCOV code coverage measurement on RISC-V.
> Lightly tested on QEMU and Hifive Unleashed board, seems to work as
> expected.
>
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
> Documentation/features/debug/gcov-profile-all/arch-support.txt | 2 +-
> arch/riscv/Kconfig | 1 +
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/features/debug/gcov-profile-all/arch-support.txt b/Documentation/features/debug/gcov-profile-all/arch-support.txt
> index 059d58a549c7..6fb2b0671994 100644
> --- a/Documentation/features/debug/gcov-profile-all/arch-support.txt
> +++ b/Documentation/features/debug/gcov-profile-all/arch-support.txt
> @@ -23,7 +23,7 @@
> | openrisc: | TODO |
> | parisc: | TODO |
> | powerpc: | ok |
> - | riscv: | TODO |
> + | riscv: | ok |
> | s390: | ok |
> | sh: | ok |
> | sparc: | TODO |
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index d8efbaa78d67..a31169b02ec0 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -64,6 +64,7 @@ config RISCV
> select SPARSEMEM_STATIC if 32BIT
> select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
> select HAVE_ARCH_MMAP_RND_BITS if MMU
> + select ARCH_HAS_GCOV_PROFILE_ALL
>
> config ARCH_MMAP_RND_BITS_MIN
> default 18 if 64BIT
> --
> 2.24.1
>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
May be (not 100% sure) split this into two patches so that
Documentation patch can be taken by Jonathan.
Regards,
Anup
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: gcov: enable gcov for RISC-V
2020-01-02 3:37 ` Anup Patel
@ 2020-01-02 3:47 ` Zong Li
2020-01-02 14:59 ` Jonathan Corbet
1 sibling, 0 replies; 5+ messages in thread
From: Zong Li @ 2020-01-02 3:47 UTC (permalink / raw)
To: Anup Patel
Cc: Albert Ou, linux-doc, corbet, linux-kernel@vger.kernel.org List,
Palmer Dabbelt, Paul Walmsley, linux-riscv
On Thu, Jan 2, 2020 at 11:37 AM Anup Patel <anup@brainfault.org> wrote:
>
> On Thu, Jan 2, 2020 at 8:40 AM Zong Li <zong.li@sifive.com> wrote:
> >
> > This patch enables GCOV code coverage measurement on RISC-V.
> > Lightly tested on QEMU and Hifive Unleashed board, seems to work as
> > expected.
> >
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > ---
> > Documentation/features/debug/gcov-profile-all/arch-support.txt | 2 +-
> > arch/riscv/Kconfig | 1 +
> > 2 files changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/features/debug/gcov-profile-all/arch-support.txt b/Documentation/features/debug/gcov-profile-all/arch-support.txt
> > index 059d58a549c7..6fb2b0671994 100644
> > --- a/Documentation/features/debug/gcov-profile-all/arch-support.txt
> > +++ b/Documentation/features/debug/gcov-profile-all/arch-support.txt
> > @@ -23,7 +23,7 @@
> > | openrisc: | TODO |
> > | parisc: | TODO |
> > | powerpc: | ok |
> > - | riscv: | TODO |
> > + | riscv: | ok |
> > | s390: | ok |
> > | sh: | ok |
> > | sparc: | TODO |
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index d8efbaa78d67..a31169b02ec0 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -64,6 +64,7 @@ config RISCV
> > select SPARSEMEM_STATIC if 32BIT
> > select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
> > select HAVE_ARCH_MMAP_RND_BITS if MMU
> > + select ARCH_HAS_GCOV_PROFILE_ALL
> >
> > config ARCH_MMAP_RND_BITS_MIN
> > default 18 if 64BIT
> > --
> > 2.24.1
> >
>
> Looks good to me.
>
> Reviewed-by: Anup Patel <anup@brainfault.org>
>
> May be (not 100% sure) split this into two patches so that
> Documentation patch can be taken by Jonathan.
OK, let me split this patch in next version.
>
> Regards,
> Anup
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: gcov: enable gcov for RISC-V
2020-01-02 3:37 ` Anup Patel
2020-01-02 3:47 ` Zong Li
@ 2020-01-02 14:59 ` Jonathan Corbet
1 sibling, 0 replies; 5+ messages in thread
From: Jonathan Corbet @ 2020-01-02 14:59 UTC (permalink / raw)
To: Anup Patel
Cc: Albert Ou, linux-doc, linux-kernel@vger.kernel.org List,
Palmer Dabbelt, Zong Li, Paul Walmsley, linux-riscv
On Thu, 2 Jan 2020 09:07:12 +0530
Anup Patel <anup@brainfault.org> wrote:
> May be (not 100% sure) split this into two patches so that
> Documentation patch can be taken by Jonathan.
That's fine if you want, but this patch can also easily go together
through the risc-v tree.
Acked-by: Jonathan Corbet <corbet@lwn.net>
jon
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: gcov: enable gcov for RISC-V
2020-01-02 3:09 [PATCH] riscv: gcov: enable gcov for RISC-V Zong Li
2020-01-02 3:37 ` Anup Patel
@ 2020-01-04 0:11 ` Paul Walmsley
1 sibling, 0 replies; 5+ messages in thread
From: Paul Walmsley @ 2020-01-04 0:11 UTC (permalink / raw)
To: Zong Li; +Cc: aou, linux-doc, corbet, linux-kernel, palmer, linux-riscv
On Thu, 2 Jan 2020, Zong Li wrote:
> This patch enables GCOV code coverage measurement on RISC-V.
> Lightly tested on QEMU and Hifive Unleashed board, seems to work as
> expected.
>
> Signed-off-by: Zong Li <zong.li@sifive.com>
Thanks, queued for v5.5-rc.
- Paul
^ permalink raw reply [flat|nested] 5+ messages in thread
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2020-01-02 3:09 [PATCH] riscv: gcov: enable gcov for RISC-V Zong Li
2020-01-02 3:37 ` Anup Patel
2020-01-02 3:47 ` Zong Li
2020-01-02 14:59 ` Jonathan Corbet
2020-01-04 0:11 ` Paul Walmsley
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