* [PATCH v7 01/10] RISC-V: Mark existing SBI as 0.1 SBI.
2020-01-28 2:27 [PATCH v7 00/10] Add support for SBI v0.2 and CPU hotplug Atish Patra
@ 2020-01-28 2:27 ` Atish Patra
2020-03-06 3:32 ` Bin Meng
2020-01-28 2:27 ` [PATCH v7 02/10] RISC-V: Add basic support for SBI v0.2 Atish Patra
` (8 subsequent siblings)
9 siblings, 1 reply; 22+ messages in thread
From: Atish Patra @ 2020-01-28 2:27 UTC (permalink / raw)
To: linux-kernel
Cc: Albert Ou, Thomas Gleixner, Kees Cook, abner.chang, Vincent Chen,
nickhu, Anup Patel, Palmer Dabbelt, Heiko Carstens,
Mike Rapoport, clin, Atish Patra, Geert Uytterhoeven,
Eric W. Biederman, Paul Walmsley, Greg Kroah-Hartman,
Greentime Hu, linux-riscv, Borislav Petkov, Palmer Dabbelt,
Mao Han
As per the new SBI specification, current SBI implementation version
is defined as 0.1 and will be removed/replaced in future. Each of the
function call in 0.1 is defined as a separate extension which makes
easier to replace them one at a time.
Rename existing implementation to reflect that. This patch is just
a preparatory patch for SBI v0.2 and doesn't introduce any functional
changes.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
arch/riscv/include/asm/sbi.h | 44 ++++++++++++++++++++----------------
1 file changed, 24 insertions(+), 20 deletions(-)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 2570c1e683d3..b38bc36f7429 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2015 Regents of the University of California
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
*/
#ifndef _ASM_RISCV_SBI_H
@@ -9,17 +10,17 @@
#include <linux/types.h>
#ifdef CONFIG_RISCV_SBI
-#define SBI_SET_TIMER 0
-#define SBI_CONSOLE_PUTCHAR 1
-#define SBI_CONSOLE_GETCHAR 2
-#define SBI_CLEAR_IPI 3
-#define SBI_SEND_IPI 4
-#define SBI_REMOTE_FENCE_I 5
-#define SBI_REMOTE_SFENCE_VMA 6
-#define SBI_REMOTE_SFENCE_VMA_ASID 7
-#define SBI_SHUTDOWN 8
+#define SBI_EXT_0_1_SET_TIMER 0x0
+#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
+#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
+#define SBI_EXT_0_1_CLEAR_IPI 0x3
+#define SBI_EXT_0_1_SEND_IPI 0x4
+#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
+#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
+#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
+#define SBI_EXT_0_1_SHUTDOWN 0x8
-#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \
+#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \
register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
@@ -43,48 +44,50 @@
static inline void sbi_console_putchar(int ch)
{
- SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch);
+ SBI_CALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, ch);
}
static inline int sbi_console_getchar(void)
{
- return SBI_CALL_0(SBI_CONSOLE_GETCHAR);
+ return SBI_CALL_0(SBI_EXT_0_1_CONSOLE_GETCHAR);
}
static inline void sbi_set_timer(uint64_t stime_value)
{
#if __riscv_xlen == 32
- SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32);
+ SBI_CALL_2(SBI_EXT_0_1_SET_TIMER, stime_value,
+ stime_value >> 32);
#else
- SBI_CALL_1(SBI_SET_TIMER, stime_value);
+ SBI_CALL_1(SBI_EXT_0_1_SET_TIMER, stime_value);
#endif
}
static inline void sbi_shutdown(void)
{
- SBI_CALL_0(SBI_SHUTDOWN);
+ SBI_CALL_0(SBI_EXT_0_1_SHUTDOWN);
}
static inline void sbi_clear_ipi(void)
{
- SBI_CALL_0(SBI_CLEAR_IPI);
+ SBI_CALL_0(SBI_EXT_0_1_CLEAR_IPI);
}
static inline void sbi_send_ipi(const unsigned long *hart_mask)
{
- SBI_CALL_1(SBI_SEND_IPI, hart_mask);
+ SBI_CALL_1(SBI_EXT_0_1_SEND_IPI, hart_mask);
}
static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
{
- SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask);
+ SBI_CALL_1(SBI_EXT_0_1_REMOTE_FENCE_I, hart_mask);
}
static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
unsigned long start,
unsigned long size)
{
- SBI_CALL_3(SBI_REMOTE_SFENCE_VMA, hart_mask, start, size);
+ SBI_CALL_3(SBI_EXT_0_1_REMOTE_SFENCE_VMA, hart_mask,
+ start, size);
}
static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
@@ -92,7 +95,8 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
unsigned long size,
unsigned long asid)
{
- SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
+ SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask,
+ start, size, asid);
}
#else /* CONFIG_RISCV_SBI */
/* stubs for code that is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
--
2.24.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v7 01/10] RISC-V: Mark existing SBI as 0.1 SBI.
2020-01-28 2:27 ` [PATCH v7 01/10] RISC-V: Mark existing SBI as 0.1 SBI Atish Patra
@ 2020-03-06 3:32 ` Bin Meng
0 siblings, 0 replies; 22+ messages in thread
From: Bin Meng @ 2020-03-06 3:32 UTC (permalink / raw)
To: Atish Patra
Cc: Albert Ou, Kees Cook, Chang, Abner (HPS SW/FW Technologist),
Greg Kroah-Hartman, nickhu, Palmer Dabbelt, Heiko Carstens,
linux-kernel, Mike Rapoport, clin, Vincent Chen, Palmer Dabbelt,
Geert Uytterhoeven, Eric W. Biederman, Paul Walmsley, Anup Patel,
Greentime Hu, Thomas Gleixner, Borislav Petkov, linux-riscv,
Mao Han
On Tue, Jan 28, 2020 at 10:28 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> As per the new SBI specification, current SBI implementation version
> is defined as 0.1 and will be removed/replaced in future. Each of the
> function call in 0.1 is defined as a separate extension which makes
> easier to replace them one at a time.
>
> Rename existing implementation to reflect that. This patch is just
> a preparatory patch for SBI v0.2 and doesn't introduce any functional
> changes.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> ---
> arch/riscv/include/asm/sbi.h | 44 ++++++++++++++++++++----------------
> 1 file changed, 24 insertions(+), 20 deletions(-)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 2570c1e683d3..b38bc36f7429 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -1,6 +1,7 @@
> /* SPDX-License-Identifier: GPL-2.0-only */
> /*
> * Copyright (C) 2015 Regents of the University of California
> + * Copyright (c) 2019 Western Digital Corporation or its affiliates.
> */
>
> #ifndef _ASM_RISCV_SBI_H
> @@ -9,17 +10,17 @@
> #include <linux/types.h>
>
> #ifdef CONFIG_RISCV_SBI
> -#define SBI_SET_TIMER 0
> -#define SBI_CONSOLE_PUTCHAR 1
> -#define SBI_CONSOLE_GETCHAR 2
> -#define SBI_CLEAR_IPI 3
> -#define SBI_SEND_IPI 4
> -#define SBI_REMOTE_FENCE_I 5
> -#define SBI_REMOTE_SFENCE_VMA 6
> -#define SBI_REMOTE_SFENCE_VMA_ASID 7
> -#define SBI_SHUTDOWN 8
> +#define SBI_EXT_0_1_SET_TIMER 0x0
> +#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
> +#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
> +#define SBI_EXT_0_1_CLEAR_IPI 0x3
> +#define SBI_EXT_0_1_SEND_IPI 0x4
> +#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
> +#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
> +#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
> +#define SBI_EXT_0_1_SHUTDOWN 0x8
>
> -#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \
> +#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \
nits: this line should not be changed
> register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
> register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
> register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
> @@ -43,48 +44,50 @@
>
[snip]
Regards,
Bin
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v7 02/10] RISC-V: Add basic support for SBI v0.2
2020-01-28 2:27 [PATCH v7 00/10] Add support for SBI v0.2 and CPU hotplug Atish Patra
2020-01-28 2:27 ` [PATCH v7 01/10] RISC-V: Mark existing SBI as 0.1 SBI Atish Patra
@ 2020-01-28 2:27 ` Atish Patra
2020-01-28 4:25 ` Anup Patel
2020-01-28 2:27 ` [PATCH v7 03/10] RISC-V: Add SBI v0.2 extension definitions Atish Patra
` (7 subsequent siblings)
9 siblings, 1 reply; 22+ messages in thread
From: Atish Patra @ 2020-01-28 2:27 UTC (permalink / raw)
To: linux-kernel
Cc: Albert Ou, Thomas Gleixner, Kees Cook, abner.chang, Vincent Chen,
nickhu, Anup Patel, Palmer Dabbelt, Heiko Carstens,
Mike Rapoport, clin, Atish Patra, Geert Uytterhoeven,
Eric W. Biederman, Paul Walmsley, Greg Kroah-Hartman,
Greentime Hu, linux-riscv, Borislav Petkov, Palmer Dabbelt,
Mao Han
The SBI v0.2 introduces a base extension which is backward compatible
with v0.1. Implement all helper functions and minimum required SBI
calls from v0.2 for now. All other base extension function will be
added later as per need.
As v0.2 calling convention is backward compatible with v0.1, remove
the v0.1 helper functions and just use v0.2 calling convention.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
arch/riscv/include/asm/sbi.h | 140 ++++++++++----------
arch/riscv/kernel/sbi.c | 243 ++++++++++++++++++++++++++++++++++-
arch/riscv/kernel/setup.c | 4 +
3 files changed, 313 insertions(+), 74 deletions(-)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index b38bc36f7429..fbdb7443784a 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -10,93 +10,88 @@
#include <linux/types.h>
#ifdef CONFIG_RISCV_SBI
-#define SBI_EXT_0_1_SET_TIMER 0x0
-#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
-#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
-#define SBI_EXT_0_1_CLEAR_IPI 0x3
-#define SBI_EXT_0_1_SEND_IPI 0x4
-#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
-#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
-#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
-#define SBI_EXT_0_1_SHUTDOWN 0x8
+enum sbi_ext_id {
+ SBI_EXT_0_1_SET_TIMER = 0x0,
+ SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
+ SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
+ SBI_EXT_0_1_CLEAR_IPI = 0x3,
+ SBI_EXT_0_1_SEND_IPI = 0x4,
+ SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
+ SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
+ SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
+ SBI_EXT_0_1_SHUTDOWN = 0x8,
+ SBI_EXT_BASE = 0x10,
+};
-#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \
- register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
- register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
- register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
- register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3); \
- register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \
- asm volatile ("ecall" \
- : "+r" (a0) \
- : "r" (a1), "r" (a2), "r" (a3), "r" (a7) \
- : "memory"); \
- a0; \
-})
+enum sbi_ext_base_fid {
+ SBI_EXT_BASE_GET_SPEC_VERSION = 0,
+ SBI_EXT_BASE_GET_IMP_ID,
+ SBI_EXT_BASE_GET_IMP_VERSION,
+ SBI_EXT_BASE_PROBE_EXT,
+ SBI_EXT_BASE_GET_MVENDORID,
+ SBI_EXT_BASE_GET_MARCHID,
+ SBI_EXT_BASE_GET_MIMPID,
+};
-/* Lazy implementations until SBI is finalized */
-#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0, 0)
-#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0, 0)
-#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0, 0)
-#define SBI_CALL_3(which, arg0, arg1, arg2) \
- SBI_CALL(which, arg0, arg1, arg2, 0)
-#define SBI_CALL_4(which, arg0, arg1, arg2, arg3) \
- SBI_CALL(which, arg0, arg1, arg2, arg3)
+#define SBI_SPEC_VERSION_DEFAULT 0x1
+#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
+#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
+#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
-static inline void sbi_console_putchar(int ch)
-{
- SBI_CALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, ch);
-}
+/* SBI return error codes */
+#define SBI_SUCCESS 0
+#define SBI_ERR_FAILURE -1
+#define SBI_ERR_NOT_SUPPORTED -2
+#define SBI_ERR_INVALID_PARAM -3
+#define SBI_ERR_DENIED -4
+#define SBI_ERR_INVALID_ADDRESS -5
-static inline int sbi_console_getchar(void)
-{
- return SBI_CALL_0(SBI_EXT_0_1_CONSOLE_GETCHAR);
-}
+extern unsigned long sbi_spec_version;
+struct sbiret {
+ long error;
+ long value;
+};
-static inline void sbi_set_timer(uint64_t stime_value)
-{
-#if __riscv_xlen == 32
- SBI_CALL_2(SBI_EXT_0_1_SET_TIMER, stime_value,
- stime_value >> 32);
-#else
- SBI_CALL_1(SBI_EXT_0_1_SET_TIMER, stime_value);
-#endif
-}
-
-static inline void sbi_shutdown(void)
-{
- SBI_CALL_0(SBI_EXT_0_1_SHUTDOWN);
-}
+int sbi_init(void);
+struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
+ unsigned long arg1, unsigned long arg2,
+ unsigned long arg3, unsigned long arg4,
+ unsigned long arg5);
-static inline void sbi_clear_ipi(void)
-{
- SBI_CALL_0(SBI_EXT_0_1_CLEAR_IPI);
-}
+void sbi_console_putchar(int ch);
+int sbi_console_getchar(void);
+void sbi_set_timer(uint64_t stime_value);
+void sbi_shutdown(void);
+void sbi_clear_ipi(void);
+void sbi_send_ipi(const unsigned long *hart_mask);
+void sbi_remote_fence_i(const unsigned long *hart_mask);
+void sbi_remote_sfence_vma(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size);
-static inline void sbi_send_ipi(const unsigned long *hart_mask)
-{
- SBI_CALL_1(SBI_EXT_0_1_SEND_IPI, hart_mask);
-}
+void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size,
+ unsigned long asid);
+int sbi_probe_extension(int ext);
-static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
+/* Check if current SBI specification version is 0.1 or not */
+static inline int sbi_spec_is_0_1(void)
{
- SBI_CALL_1(SBI_EXT_0_1_REMOTE_FENCE_I, hart_mask);
+ return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT) ? 1 : 0;
}
-static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
- unsigned long start,
- unsigned long size)
+/* Get the major version of SBI */
+static inline unsigned long sbi_major_version(void)
{
- SBI_CALL_3(SBI_EXT_0_1_REMOTE_SFENCE_VMA, hart_mask,
- start, size);
+ return (sbi_spec_version >> SBI_SPEC_VERSION_MAJOR_SHIFT) &
+ SBI_SPEC_VERSION_MAJOR_MASK;
}
-static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
- unsigned long start,
- unsigned long size,
- unsigned long asid)
+/* Get the minor version of SBI */
+static inline unsigned long sbi_minor_version(void)
{
- SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask,
- start, size, asid);
+ return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK;
}
#else /* CONFIG_RISCV_SBI */
/* stubs for code that is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
@@ -104,5 +99,6 @@ void sbi_set_timer(uint64_t stime_value);
void sbi_clear_ipi(void);
void sbi_send_ipi(const unsigned long *hart_mask);
void sbi_remote_fence_i(const unsigned long *hart_mask);
+void sbi_init(void);
#endif /* CONFIG_RISCV_SBI */
#endif /* _ASM_RISCV_SBI_H */
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index f6c7c3e82d28..33632e7f91da 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -1,17 +1,256 @@
// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * SBI initialilization and all extension implementation.
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ */
#include <linux/init.h>
#include <linux/pm.h>
#include <asm/sbi.h>
+/* default SBI version is 0.1 */
+unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT;
+EXPORT_SYMBOL(sbi_spec_version);
+
+struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
+ unsigned long arg1, unsigned long arg2,
+ unsigned long arg3, unsigned long arg4,
+ unsigned long arg5)
+{
+ struct sbiret ret;
+
+ register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
+ register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
+ register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
+ register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
+ register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
+ register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
+ register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
+ register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
+ asm volatile ("ecall"
+ : "+r" (a0), "+r" (a1)
+ : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
+ : "memory");
+ ret.error = a0;
+ ret.value = a1;
+
+ return ret;
+}
+EXPORT_SYMBOL(sbi_ecall);
+
+static int sbi_err_map_linux_errno(int err)
+{
+ switch (err) {
+ case SBI_SUCCESS:
+ return 0;
+ case SBI_ERR_DENIED:
+ return -EPERM;
+ case SBI_ERR_INVALID_PARAM:
+ return -EINVAL;
+ case SBI_ERR_INVALID_ADDRESS:
+ return -EFAULT;
+ case SBI_ERR_NOT_SUPPORTED:
+ case SBI_ERR_FAILURE:
+ default:
+ return -ENOTSUPP;
+ };
+}
+
+/**
+ * sbi_console_putchar() - Writes given character to the console device.
+ * @ch: The data to be written to the console.
+ *
+ * Return: None
+ */
+void sbi_console_putchar(int ch)
+{
+ sbi_ecall(SBI_EXT_0_1_CONSOLE_PUTCHAR, 0, ch, 0, 0, 0, 0, 0);
+}
+EXPORT_SYMBOL(sbi_console_putchar);
+
+/**
+ * sbi_console_getchar() - Reads a byte from console device.
+ *
+ * Returns the value read from console.
+ */
+int sbi_console_getchar(void)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_0_1_CONSOLE_GETCHAR, 0, 0, 0, 0, 0, 0, 0);
+
+ return ret.error;
+}
+EXPORT_SYMBOL(sbi_console_getchar);
+
+/**
+ * sbi_set_timer() - Program the timer for next timer event.
+ * @stime_value: The value after which next timer event should fire.
+ *
+ * Return: None
+ */
+void sbi_set_timer(uint64_t stime_value)
+{
+#if __riscv_xlen == 32
+ sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
+ stime_value >> 32, 0, 0, 0, 0);
+#else
+ sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
+#endif
+}
+EXPORT_SYMBOL(sbi_set_timer);
+
+/**
+ * sbi_shutdown() - Remove all the harts from executing supervisor code.
+ *
+ * Return: None
+ */
+void sbi_shutdown(void)
+{
+ sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
+}
+EXPORT_SYMBOL(sbi_shutdown);
+
+/**
+ * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
+ *
+ * Return: None
+ */
+void sbi_clear_ipi(void)
+{
+ sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0);
+}
+
+/**
+ * sbi_send_ipi() - Send an IPI to any hart.
+ * @hart_mask: A cpu mask containing all the target harts.
+ *
+ * Return: None
+ */
+void sbi_send_ipi(const unsigned long *hart_mask)
+{
+ sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
+ 0, 0, 0, 0, 0);
+}
+EXPORT_SYMBOL(sbi_send_ipi);
+
+/**
+ * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
+ * @hart_mask: A cpu mask containing all the target harts.
+ *
+ * Return: None
+ */
+void sbi_remote_fence_i(const unsigned long *hart_mask)
+{
+ sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned long)hart_mask,
+ 0, 0, 0, 0, 0);
+}
+EXPORT_SYMBOL(sbi_remote_fence_i);
+
+/**
+ * sbi_remote_sfence_vma() - Execute SFENCE.VMA instructions on given remote
+ * harts for the specified virtual address range.
+ * @hart_mask: A cpu mask containing all the target harts.
+ * @start: Start of the virtual address
+ * @size: Total size of the virtual address range.
+ *
+ * Return: None
+ */
+void sbi_remote_sfence_vma(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size)
+{
+ sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
+ (unsigned long)hart_mask, start, size, 0, 0, 0);
+}
+EXPORT_SYMBOL(sbi_remote_sfence_vma);
+
+/**
+ * sbi_remote_sfence_vma_asid() - Execute SFENCE.VMA instructions on given
+ * remote harts for a virtual address range belonging to a specific ASID.
+ *
+ * @hart_mask: A cpu mask containing all the target harts.
+ * @start: Start of the virtual address
+ * @size: Total size of the virtual address range.
+ * @asid: The value of address space identifier (ASID).
+ *
+ * Return: None
+ */
+void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size,
+ unsigned long asid)
+{
+ sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
+ (unsigned long)hart_mask, start, size, asid, 0, 0);
+}
+EXPORT_SYMBOL(sbi_remote_sfence_vma_asid);
+
+/**
+ * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
+ * @extid: The extension ID to be probed.
+ *
+ * Return: Extension specific nonzero value f yes, -ENOTSUPP otherwise.
+ */
+int sbi_probe_extension(int extid)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, extid,
+ 0, 0, 0, 0, 0);
+ if (!ret.error)
+ if (ret.value)
+ return ret.value;
+
+ return -ENOTSUPP;
+}
+EXPORT_SYMBOL(sbi_probe_extension);
+
+static long __sbi_base_ecall(int fid)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_BASE, fid, 0, 0, 0, 0, 0, 0);
+ if (!ret.error)
+ return ret.value;
+ else
+ return sbi_err_map_linux_errno(ret.error);
+}
+
+static inline long sbi_get_spec_version(void)
+{
+ return __sbi_base_ecall(SBI_EXT_BASE_GET_SPEC_VERSION);
+}
+
+static inline long sbi_get_firmware_id(void)
+{
+ return __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_ID);
+}
+
+static inline long sbi_get_firmware_version(void)
+{
+ return __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_VERSION);
+}
+
static void sbi_power_off(void)
{
sbi_shutdown();
}
-static int __init sbi_init(void)
+int __init sbi_init(void)
{
+ int ret;
+
pm_power_off = sbi_power_off;
+ ret = sbi_get_spec_version();
+ if (ret > 0)
+ sbi_spec_version = ret;
+
+ pr_info("SBI specification v%lu.%lu detected\n",
+ sbi_major_version(), sbi_minor_version());
+ if (!sbi_spec_is_0_1())
+ pr_info("SBI implementation ID=0x%lx Version=0x%lx\n",
+ sbi_get_firmware_id(), sbi_get_firmware_version());
return 0;
}
-early_initcall(sbi_init);
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index 365ff8420bfe..de3e65dae83a 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -22,6 +22,7 @@
#include <asm/sections.h>
#include <asm/pgtable.h>
#include <asm/smp.h>
+#include <asm/sbi.h>
#include <asm/tlbflush.h>
#include <asm/thread_info.h>
@@ -74,6 +75,9 @@ void __init setup_arch(char **cmdline_p)
swiotlb_init(1);
#endif
+ if (IS_ENABLED(CONFIG_RISCV_SBI))
+ sbi_init();
+
#ifdef CONFIG_SMP
setup_smp();
#endif
--
2.24.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v7 02/10] RISC-V: Add basic support for SBI v0.2
2020-01-28 2:27 ` [PATCH v7 02/10] RISC-V: Add basic support for SBI v0.2 Atish Patra
@ 2020-01-28 4:25 ` Anup Patel
2020-01-28 19:12 ` Atish Patra
0 siblings, 1 reply; 22+ messages in thread
From: Anup Patel @ 2020-01-28 4:25 UTC (permalink / raw)
To: Atish Patra
Cc: Albert Ou, Thomas Gleixner, Kees Cook, Abner Chang, nickhu,
Greg Kroah-Hartman, Palmer Dabbelt, Heiko Carstens,
linux-kernel@vger.kernel.org List, Mike Rapoport, Chester Lin,
Vincent Chen, Geert Uytterhoeven, Eric W. Biederman,
Paul Walmsley, Greentime Hu, linux-riscv, Borislav Petkov,
Palmer Dabbelt, Mao Han
On Tue, Jan 28, 2020 at 7:58 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> The SBI v0.2 introduces a base extension which is backward compatible
> with v0.1. Implement all helper functions and minimum required SBI
> calls from v0.2 for now. All other base extension function will be
> added later as per need.
> As v0.2 calling convention is backward compatible with v0.1, remove
> the v0.1 helper functions and just use v0.2 calling convention.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> ---
> arch/riscv/include/asm/sbi.h | 140 ++++++++++----------
> arch/riscv/kernel/sbi.c | 243 ++++++++++++++++++++++++++++++++++-
> arch/riscv/kernel/setup.c | 4 +
> 3 files changed, 313 insertions(+), 74 deletions(-)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index b38bc36f7429..fbdb7443784a 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -10,93 +10,88 @@
> #include <linux/types.h>
>
> #ifdef CONFIG_RISCV_SBI
> -#define SBI_EXT_0_1_SET_TIMER 0x0
> -#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
> -#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
> -#define SBI_EXT_0_1_CLEAR_IPI 0x3
> -#define SBI_EXT_0_1_SEND_IPI 0x4
> -#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
> -#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
> -#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
> -#define SBI_EXT_0_1_SHUTDOWN 0x8
> +enum sbi_ext_id {
> + SBI_EXT_0_1_SET_TIMER = 0x0,
> + SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
> + SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
> + SBI_EXT_0_1_CLEAR_IPI = 0x3,
> + SBI_EXT_0_1_SEND_IPI = 0x4,
> + SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
> + SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
> + SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
> + SBI_EXT_0_1_SHUTDOWN = 0x8,
> + SBI_EXT_BASE = 0x10,
> +};
>
> -#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \
> - register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
> - register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
> - register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
> - register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3); \
> - register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \
> - asm volatile ("ecall" \
> - : "+r" (a0) \
> - : "r" (a1), "r" (a2), "r" (a3), "r" (a7) \
> - : "memory"); \
> - a0; \
> -})
> +enum sbi_ext_base_fid {
> + SBI_EXT_BASE_GET_SPEC_VERSION = 0,
> + SBI_EXT_BASE_GET_IMP_ID,
> + SBI_EXT_BASE_GET_IMP_VERSION,
> + SBI_EXT_BASE_PROBE_EXT,
> + SBI_EXT_BASE_GET_MVENDORID,
> + SBI_EXT_BASE_GET_MARCHID,
> + SBI_EXT_BASE_GET_MIMPID,
> +};
>
> -/* Lazy implementations until SBI is finalized */
> -#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0, 0)
> -#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0, 0)
> -#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0, 0)
> -#define SBI_CALL_3(which, arg0, arg1, arg2) \
> - SBI_CALL(which, arg0, arg1, arg2, 0)
> -#define SBI_CALL_4(which, arg0, arg1, arg2, arg3) \
> - SBI_CALL(which, arg0, arg1, arg2, arg3)
> +#define SBI_SPEC_VERSION_DEFAULT 0x1
> +#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
> +#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
> +#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
>
> -static inline void sbi_console_putchar(int ch)
> -{
> - SBI_CALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, ch);
> -}
> +/* SBI return error codes */
> +#define SBI_SUCCESS 0
> +#define SBI_ERR_FAILURE -1
> +#define SBI_ERR_NOT_SUPPORTED -2
> +#define SBI_ERR_INVALID_PARAM -3
> +#define SBI_ERR_DENIED -4
> +#define SBI_ERR_INVALID_ADDRESS -5
>
> -static inline int sbi_console_getchar(void)
> -{
> - return SBI_CALL_0(SBI_EXT_0_1_CONSOLE_GETCHAR);
> -}
> +extern unsigned long sbi_spec_version;
> +struct sbiret {
> + long error;
> + long value;
> +};
>
> -static inline void sbi_set_timer(uint64_t stime_value)
> -{
> -#if __riscv_xlen == 32
> - SBI_CALL_2(SBI_EXT_0_1_SET_TIMER, stime_value,
> - stime_value >> 32);
> -#else
> - SBI_CALL_1(SBI_EXT_0_1_SET_TIMER, stime_value);
> -#endif
> -}
> -
> -static inline void sbi_shutdown(void)
> -{
> - SBI_CALL_0(SBI_EXT_0_1_SHUTDOWN);
> -}
> +int sbi_init(void);
> +struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> + unsigned long arg1, unsigned long arg2,
> + unsigned long arg3, unsigned long arg4,
> + unsigned long arg5);
>
> -static inline void sbi_clear_ipi(void)
> -{
> - SBI_CALL_0(SBI_EXT_0_1_CLEAR_IPI);
> -}
> +void sbi_console_putchar(int ch);
> +int sbi_console_getchar(void);
> +void sbi_set_timer(uint64_t stime_value);
> +void sbi_shutdown(void);
> +void sbi_clear_ipi(void);
> +void sbi_send_ipi(const unsigned long *hart_mask);
> +void sbi_remote_fence_i(const unsigned long *hart_mask);
> +void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size);
>
> -static inline void sbi_send_ipi(const unsigned long *hart_mask)
> -{
> - SBI_CALL_1(SBI_EXT_0_1_SEND_IPI, hart_mask);
> -}
> +void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size,
> + unsigned long asid);
> +int sbi_probe_extension(int ext);
>
> -static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
> +/* Check if current SBI specification version is 0.1 or not */
> +static inline int sbi_spec_is_0_1(void)
> {
> - SBI_CALL_1(SBI_EXT_0_1_REMOTE_FENCE_I, hart_mask);
> + return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT) ? 1 : 0;
> }
>
> -static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> - unsigned long start,
> - unsigned long size)
> +/* Get the major version of SBI */
> +static inline unsigned long sbi_major_version(void)
> {
> - SBI_CALL_3(SBI_EXT_0_1_REMOTE_SFENCE_VMA, hart_mask,
> - start, size);
> + return (sbi_spec_version >> SBI_SPEC_VERSION_MAJOR_SHIFT) &
> + SBI_SPEC_VERSION_MAJOR_MASK;
> }
>
> -static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> - unsigned long start,
> - unsigned long size,
> - unsigned long asid)
> +/* Get the minor version of SBI */
> +static inline unsigned long sbi_minor_version(void)
> {
> - SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask,
> - start, size, asid);
> + return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK;
> }
> #else /* CONFIG_RISCV_SBI */
> /* stubs for code that is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
> @@ -104,5 +99,6 @@ void sbi_set_timer(uint64_t stime_value);
> void sbi_clear_ipi(void);
> void sbi_send_ipi(const unsigned long *hart_mask);
> void sbi_remote_fence_i(const unsigned long *hart_mask);
> +void sbi_init(void);
> #endif /* CONFIG_RISCV_SBI */
> #endif /* _ASM_RISCV_SBI_H */
> diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> index f6c7c3e82d28..33632e7f91da 100644
> --- a/arch/riscv/kernel/sbi.c
> +++ b/arch/riscv/kernel/sbi.c
> @@ -1,17 +1,256 @@
> // SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * SBI initialilization and all extension implementation.
> + *
> + * Copyright (c) 2019 Western Digital Corporation or its affiliates.
> + */
>
> #include <linux/init.h>
> #include <linux/pm.h>
> #include <asm/sbi.h>
>
> +/* default SBI version is 0.1 */
> +unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT;
> +EXPORT_SYMBOL(sbi_spec_version);
> +
> +struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> + unsigned long arg1, unsigned long arg2,
> + unsigned long arg3, unsigned long arg4,
> + unsigned long arg5)
> +{
> + struct sbiret ret;
> +
> + register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
> + register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
> + register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
> + register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
> + register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
> + register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
> + register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
> + register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
> + asm volatile ("ecall"
> + : "+r" (a0), "+r" (a1)
> + : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
> + : "memory");
> + ret.error = a0;
> + ret.value = a1;
> +
> + return ret;
> +}
> +EXPORT_SYMBOL(sbi_ecall);
> +
> +static int sbi_err_map_linux_errno(int err)
> +{
> + switch (err) {
> + case SBI_SUCCESS:
> + return 0;
> + case SBI_ERR_DENIED:
> + return -EPERM;
> + case SBI_ERR_INVALID_PARAM:
> + return -EINVAL;
> + case SBI_ERR_INVALID_ADDRESS:
> + return -EFAULT;
> + case SBI_ERR_NOT_SUPPORTED:
> + case SBI_ERR_FAILURE:
> + default:
> + return -ENOTSUPP;
> + };
> +}
> +
> +/**
> + * sbi_console_putchar() - Writes given character to the console device.
> + * @ch: The data to be written to the console.
> + *
> + * Return: None
> + */
> +void sbi_console_putchar(int ch)
> +{
> + sbi_ecall(SBI_EXT_0_1_CONSOLE_PUTCHAR, 0, ch, 0, 0, 0, 0, 0);
> +}
> +EXPORT_SYMBOL(sbi_console_putchar);
> +
> +/**
> + * sbi_console_getchar() - Reads a byte from console device.
> + *
> + * Returns the value read from console.
> + */
> +int sbi_console_getchar(void)
> +{
> + struct sbiret ret;
> +
> + ret = sbi_ecall(SBI_EXT_0_1_CONSOLE_GETCHAR, 0, 0, 0, 0, 0, 0, 0);
> +
> + return ret.error;
> +}
> +EXPORT_SYMBOL(sbi_console_getchar);
> +
> +/**
> + * sbi_set_timer() - Program the timer for next timer event.
> + * @stime_value: The value after which next timer event should fire.
> + *
> + * Return: None
> + */
> +void sbi_set_timer(uint64_t stime_value)
> +{
> +#if __riscv_xlen == 32
> + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
> + stime_value >> 32, 0, 0, 0, 0);
> +#else
> + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
> +#endif
> +}
> +EXPORT_SYMBOL(sbi_set_timer);
> +
> +/**
> + * sbi_shutdown() - Remove all the harts from executing supervisor code.
> + *
> + * Return: None
> + */
> +void sbi_shutdown(void)
> +{
> + sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
> +}
> +EXPORT_SYMBOL(sbi_shutdown);
> +
> +/**
> + * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
> + *
> + * Return: None
> + */
> +void sbi_clear_ipi(void)
> +{
> + sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0);
> +}
> +
> +/**
> + * sbi_send_ipi() - Send an IPI to any hart.
> + * @hart_mask: A cpu mask containing all the target harts.
> + *
> + * Return: None
> + */
> +void sbi_send_ipi(const unsigned long *hart_mask)
> +{
> + sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
> + 0, 0, 0, 0, 0);
> +}
> +EXPORT_SYMBOL(sbi_send_ipi);
> +
> +/**
> + * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
> + * @hart_mask: A cpu mask containing all the target harts.
> + *
> + * Return: None
> + */
> +void sbi_remote_fence_i(const unsigned long *hart_mask)
> +{
> + sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned long)hart_mask,
> + 0, 0, 0, 0, 0);
> +}
> +EXPORT_SYMBOL(sbi_remote_fence_i);
> +
> +/**
> + * sbi_remote_sfence_vma() - Execute SFENCE.VMA instructions on given remote
> + * harts for the specified virtual address range.
> + * @hart_mask: A cpu mask containing all the target harts.
> + * @start: Start of the virtual address
> + * @size: Total size of the virtual address range.
> + *
> + * Return: None
> + */
> +void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size)
> +{
> + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
> + (unsigned long)hart_mask, start, size, 0, 0, 0);
> +}
> +EXPORT_SYMBOL(sbi_remote_sfence_vma);
> +
> +/**
> + * sbi_remote_sfence_vma_asid() - Execute SFENCE.VMA instructions on given
> + * remote harts for a virtual address range belonging to a specific ASID.
> + *
> + * @hart_mask: A cpu mask containing all the target harts.
> + * @start: Start of the virtual address
> + * @size: Total size of the virtual address range.
> + * @asid: The value of address space identifier (ASID).
> + *
> + * Return: None
> + */
> +void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> + unsigned long start,
> + unsigned long size,
> + unsigned long asid)
> +{
> + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
> + (unsigned long)hart_mask, start, size, asid, 0, 0);
> +}
> +EXPORT_SYMBOL(sbi_remote_sfence_vma_asid);
> +
> +/**
> + * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
> + * @extid: The extension ID to be probed.
> + *
> + * Return: Extension specific nonzero value f yes, -ENOTSUPP otherwise.
> + */
> +int sbi_probe_extension(int extid)
> +{
> + struct sbiret ret;
> +
> + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, extid,
> + 0, 0, 0, 0, 0);
> + if (!ret.error)
> + if (ret.value)
> + return ret.value;
> +
> + return -ENOTSUPP;
> +}
> +EXPORT_SYMBOL(sbi_probe_extension);
> +
> +static long __sbi_base_ecall(int fid)
> +{
> + struct sbiret ret;
> +
> + ret = sbi_ecall(SBI_EXT_BASE, fid, 0, 0, 0, 0, 0, 0);
> + if (!ret.error)
> + return ret.value;
> + else
> + return sbi_err_map_linux_errno(ret.error);
> +}
> +
> +static inline long sbi_get_spec_version(void)
> +{
> + return __sbi_base_ecall(SBI_EXT_BASE_GET_SPEC_VERSION);
> +}
> +
> +static inline long sbi_get_firmware_id(void)
> +{
> + return __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_ID);
> +}
> +
> +static inline long sbi_get_firmware_version(void)
> +{
> + return __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_VERSION);
> +}
> +
> static void sbi_power_off(void)
> {
> sbi_shutdown();
> }
>
> -static int __init sbi_init(void)
> +int __init sbi_init(void)
> {
> + int ret;
> +
> pm_power_off = sbi_power_off;
> + ret = sbi_get_spec_version();
> + if (ret > 0)
> + sbi_spec_version = ret;
> +
> + pr_info("SBI specification v%lu.%lu detected\n",
> + sbi_major_version(), sbi_minor_version());
> + if (!sbi_spec_is_0_1())
> + pr_info("SBI implementation ID=0x%lx Version=0x%lx\n",
> + sbi_get_firmware_id(), sbi_get_firmware_version());
> return 0;
> }
> -early_initcall(sbi_init);
> diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> index 365ff8420bfe..de3e65dae83a 100644
> --- a/arch/riscv/kernel/setup.c
> +++ b/arch/riscv/kernel/setup.c
> @@ -22,6 +22,7 @@
> #include <asm/sections.h>
> #include <asm/pgtable.h>
> #include <asm/smp.h>
> +#include <asm/sbi.h>
> #include <asm/tlbflush.h>
> #include <asm/thread_info.h>
>
> @@ -74,6 +75,9 @@ void __init setup_arch(char **cmdline_p)
> swiotlb_init(1);
> #endif
>
> + if (IS_ENABLED(CONFIG_RISCV_SBI))
> + sbi_init();
> +
This has to "#if IS_ENABLED(CONFIG_RISCV_SBI)" instead of
"if ()".
Regards,
Anup
> #ifdef CONFIG_SMP
> setup_smp();
> #endif
> --
> 2.24.0
>
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v7 02/10] RISC-V: Add basic support for SBI v0.2
2020-01-28 4:25 ` Anup Patel
@ 2020-01-28 19:12 ` Atish Patra
2020-02-06 6:24 ` Anup Patel
0 siblings, 1 reply; 22+ messages in thread
From: Atish Patra @ 2020-01-28 19:12 UTC (permalink / raw)
To: Anup Patel
Cc: Albert Ou, Kees Cook, nickhu, Vincent Chen, Greg Kroah-Hartman,
Palmer Dabbelt, Heiko Carstens,
linux-kernel@vger.kernel.org List, Mike Rapoport, Chester Lin,
Atish Patra, Palmer Dabbelt, Geert Uytterhoeven,
Eric W. Biederman, Paul Walmsley, Greentime Hu, Thomas Gleixner,
Borislav Petkov, Abner Chang, linux-riscv, Mao Han
On Mon, Jan 27, 2020 at 8:25 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Tue, Jan 28, 2020 at 7:58 AM Atish Patra <atish.patra@wdc.com> wrote:
> >
> > The SBI v0.2 introduces a base extension which is backward compatible
> > with v0.1. Implement all helper functions and minimum required SBI
> > calls from v0.2 for now. All other base extension function will be
> > added later as per need.
> > As v0.2 calling convention is backward compatible with v0.1, remove
> > the v0.1 helper functions and just use v0.2 calling convention.
> >
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > Reviewed-by: Anup Patel <anup@brainfault.org>
> > Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> > ---
> > arch/riscv/include/asm/sbi.h | 140 ++++++++++----------
> > arch/riscv/kernel/sbi.c | 243 ++++++++++++++++++++++++++++++++++-
> > arch/riscv/kernel/setup.c | 4 +
> > 3 files changed, 313 insertions(+), 74 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> > index b38bc36f7429..fbdb7443784a 100644
> > --- a/arch/riscv/include/asm/sbi.h
> > +++ b/arch/riscv/include/asm/sbi.h
> > @@ -10,93 +10,88 @@
> > #include <linux/types.h>
> >
> > #ifdef CONFIG_RISCV_SBI
> > -#define SBI_EXT_0_1_SET_TIMER 0x0
> > -#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
> > -#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
> > -#define SBI_EXT_0_1_CLEAR_IPI 0x3
> > -#define SBI_EXT_0_1_SEND_IPI 0x4
> > -#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
> > -#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
> > -#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
> > -#define SBI_EXT_0_1_SHUTDOWN 0x8
> > +enum sbi_ext_id {
> > + SBI_EXT_0_1_SET_TIMER = 0x0,
> > + SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
> > + SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
> > + SBI_EXT_0_1_CLEAR_IPI = 0x3,
> > + SBI_EXT_0_1_SEND_IPI = 0x4,
> > + SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
> > + SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
> > + SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
> > + SBI_EXT_0_1_SHUTDOWN = 0x8,
> > + SBI_EXT_BASE = 0x10,
> > +};
> >
> > -#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \
> > - register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
> > - register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
> > - register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
> > - register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3); \
> > - register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \
> > - asm volatile ("ecall" \
> > - : "+r" (a0) \
> > - : "r" (a1), "r" (a2), "r" (a3), "r" (a7) \
> > - : "memory"); \
> > - a0; \
> > -})
> > +enum sbi_ext_base_fid {
> > + SBI_EXT_BASE_GET_SPEC_VERSION = 0,
> > + SBI_EXT_BASE_GET_IMP_ID,
> > + SBI_EXT_BASE_GET_IMP_VERSION,
> > + SBI_EXT_BASE_PROBE_EXT,
> > + SBI_EXT_BASE_GET_MVENDORID,
> > + SBI_EXT_BASE_GET_MARCHID,
> > + SBI_EXT_BASE_GET_MIMPID,
> > +};
> >
> > -/* Lazy implementations until SBI is finalized */
> > -#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0, 0)
> > -#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0, 0)
> > -#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0, 0)
> > -#define SBI_CALL_3(which, arg0, arg1, arg2) \
> > - SBI_CALL(which, arg0, arg1, arg2, 0)
> > -#define SBI_CALL_4(which, arg0, arg1, arg2, arg3) \
> > - SBI_CALL(which, arg0, arg1, arg2, arg3)
> > +#define SBI_SPEC_VERSION_DEFAULT 0x1
> > +#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
> > +#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
> > +#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
> >
> > -static inline void sbi_console_putchar(int ch)
> > -{
> > - SBI_CALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, ch);
> > -}
> > +/* SBI return error codes */
> > +#define SBI_SUCCESS 0
> > +#define SBI_ERR_FAILURE -1
> > +#define SBI_ERR_NOT_SUPPORTED -2
> > +#define SBI_ERR_INVALID_PARAM -3
> > +#define SBI_ERR_DENIED -4
> > +#define SBI_ERR_INVALID_ADDRESS -5
> >
> > -static inline int sbi_console_getchar(void)
> > -{
> > - return SBI_CALL_0(SBI_EXT_0_1_CONSOLE_GETCHAR);
> > -}
> > +extern unsigned long sbi_spec_version;
> > +struct sbiret {
> > + long error;
> > + long value;
> > +};
> >
> > -static inline void sbi_set_timer(uint64_t stime_value)
> > -{
> > -#if __riscv_xlen == 32
> > - SBI_CALL_2(SBI_EXT_0_1_SET_TIMER, stime_value,
> > - stime_value >> 32);
> > -#else
> > - SBI_CALL_1(SBI_EXT_0_1_SET_TIMER, stime_value);
> > -#endif
> > -}
> > -
> > -static inline void sbi_shutdown(void)
> > -{
> > - SBI_CALL_0(SBI_EXT_0_1_SHUTDOWN);
> > -}
> > +int sbi_init(void);
> > +struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> > + unsigned long arg1, unsigned long arg2,
> > + unsigned long arg3, unsigned long arg4,
> > + unsigned long arg5);
> >
> > -static inline void sbi_clear_ipi(void)
> > -{
> > - SBI_CALL_0(SBI_EXT_0_1_CLEAR_IPI);
> > -}
> > +void sbi_console_putchar(int ch);
> > +int sbi_console_getchar(void);
> > +void sbi_set_timer(uint64_t stime_value);
> > +void sbi_shutdown(void);
> > +void sbi_clear_ipi(void);
> > +void sbi_send_ipi(const unsigned long *hart_mask);
> > +void sbi_remote_fence_i(const unsigned long *hart_mask);
> > +void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size);
> >
> > -static inline void sbi_send_ipi(const unsigned long *hart_mask)
> > -{
> > - SBI_CALL_1(SBI_EXT_0_1_SEND_IPI, hart_mask);
> > -}
> > +void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size,
> > + unsigned long asid);
> > +int sbi_probe_extension(int ext);
> >
> > -static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
> > +/* Check if current SBI specification version is 0.1 or not */
> > +static inline int sbi_spec_is_0_1(void)
> > {
> > - SBI_CALL_1(SBI_EXT_0_1_REMOTE_FENCE_I, hart_mask);
> > + return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT) ? 1 : 0;
> > }
> >
> > -static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> > - unsigned long start,
> > - unsigned long size)
> > +/* Get the major version of SBI */
> > +static inline unsigned long sbi_major_version(void)
> > {
> > - SBI_CALL_3(SBI_EXT_0_1_REMOTE_SFENCE_VMA, hart_mask,
> > - start, size);
> > + return (sbi_spec_version >> SBI_SPEC_VERSION_MAJOR_SHIFT) &
> > + SBI_SPEC_VERSION_MAJOR_MASK;
> > }
> >
> > -static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> > - unsigned long start,
> > - unsigned long size,
> > - unsigned long asid)
> > +/* Get the minor version of SBI */
> > +static inline unsigned long sbi_minor_version(void)
> > {
> > - SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask,
> > - start, size, asid);
> > + return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK;
> > }
> > #else /* CONFIG_RISCV_SBI */
> > /* stubs for code that is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
> > @@ -104,5 +99,6 @@ void sbi_set_timer(uint64_t stime_value);
> > void sbi_clear_ipi(void);
> > void sbi_send_ipi(const unsigned long *hart_mask);
> > void sbi_remote_fence_i(const unsigned long *hart_mask);
> > +void sbi_init(void);
> > #endif /* CONFIG_RISCV_SBI */
> > #endif /* _ASM_RISCV_SBI_H */
> > diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> > index f6c7c3e82d28..33632e7f91da 100644
> > --- a/arch/riscv/kernel/sbi.c
> > +++ b/arch/riscv/kernel/sbi.c
> > @@ -1,17 +1,256 @@
> > // SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * SBI initialilization and all extension implementation.
> > + *
> > + * Copyright (c) 2019 Western Digital Corporation or its affiliates.
> > + */
> >
> > #include <linux/init.h>
> > #include <linux/pm.h>
> > #include <asm/sbi.h>
> >
> > +/* default SBI version is 0.1 */
> > +unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT;
> > +EXPORT_SYMBOL(sbi_spec_version);
> > +
> > +struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> > + unsigned long arg1, unsigned long arg2,
> > + unsigned long arg3, unsigned long arg4,
> > + unsigned long arg5)
> > +{
> > + struct sbiret ret;
> > +
> > + register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
> > + register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
> > + register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
> > + register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
> > + register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
> > + register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
> > + register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
> > + register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
> > + asm volatile ("ecall"
> > + : "+r" (a0), "+r" (a1)
> > + : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
> > + : "memory");
> > + ret.error = a0;
> > + ret.value = a1;
> > +
> > + return ret;
> > +}
> > +EXPORT_SYMBOL(sbi_ecall);
> > +
> > +static int sbi_err_map_linux_errno(int err)
> > +{
> > + switch (err) {
> > + case SBI_SUCCESS:
> > + return 0;
> > + case SBI_ERR_DENIED:
> > + return -EPERM;
> > + case SBI_ERR_INVALID_PARAM:
> > + return -EINVAL;
> > + case SBI_ERR_INVALID_ADDRESS:
> > + return -EFAULT;
> > + case SBI_ERR_NOT_SUPPORTED:
> > + case SBI_ERR_FAILURE:
> > + default:
> > + return -ENOTSUPP;
> > + };
> > +}
> > +
> > +/**
> > + * sbi_console_putchar() - Writes given character to the console device.
> > + * @ch: The data to be written to the console.
> > + *
> > + * Return: None
> > + */
> > +void sbi_console_putchar(int ch)
> > +{
> > + sbi_ecall(SBI_EXT_0_1_CONSOLE_PUTCHAR, 0, ch, 0, 0, 0, 0, 0);
> > +}
> > +EXPORT_SYMBOL(sbi_console_putchar);
> > +
> > +/**
> > + * sbi_console_getchar() - Reads a byte from console device.
> > + *
> > + * Returns the value read from console.
> > + */
> > +int sbi_console_getchar(void)
> > +{
> > + struct sbiret ret;
> > +
> > + ret = sbi_ecall(SBI_EXT_0_1_CONSOLE_GETCHAR, 0, 0, 0, 0, 0, 0, 0);
> > +
> > + return ret.error;
> > +}
> > +EXPORT_SYMBOL(sbi_console_getchar);
> > +
> > +/**
> > + * sbi_set_timer() - Program the timer for next timer event.
> > + * @stime_value: The value after which next timer event should fire.
> > + *
> > + * Return: None
> > + */
> > +void sbi_set_timer(uint64_t stime_value)
> > +{
> > +#if __riscv_xlen == 32
> > + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
> > + stime_value >> 32, 0, 0, 0, 0);
> > +#else
> > + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
> > +#endif
> > +}
> > +EXPORT_SYMBOL(sbi_set_timer);
> > +
> > +/**
> > + * sbi_shutdown() - Remove all the harts from executing supervisor code.
> > + *
> > + * Return: None
> > + */
> > +void sbi_shutdown(void)
> > +{
> > + sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
> > +}
> > +EXPORT_SYMBOL(sbi_shutdown);
> > +
> > +/**
> > + * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
> > + *
> > + * Return: None
> > + */
> > +void sbi_clear_ipi(void)
> > +{
> > + sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0);
> > +}
> > +
> > +/**
> > + * sbi_send_ipi() - Send an IPI to any hart.
> > + * @hart_mask: A cpu mask containing all the target harts.
> > + *
> > + * Return: None
> > + */
> > +void sbi_send_ipi(const unsigned long *hart_mask)
> > +{
> > + sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
> > + 0, 0, 0, 0, 0);
> > +}
> > +EXPORT_SYMBOL(sbi_send_ipi);
> > +
> > +/**
> > + * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
> > + * @hart_mask: A cpu mask containing all the target harts.
> > + *
> > + * Return: None
> > + */
> > +void sbi_remote_fence_i(const unsigned long *hart_mask)
> > +{
> > + sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned long)hart_mask,
> > + 0, 0, 0, 0, 0);
> > +}
> > +EXPORT_SYMBOL(sbi_remote_fence_i);
> > +
> > +/**
> > + * sbi_remote_sfence_vma() - Execute SFENCE.VMA instructions on given remote
> > + * harts for the specified virtual address range.
> > + * @hart_mask: A cpu mask containing all the target harts.
> > + * @start: Start of the virtual address
> > + * @size: Total size of the virtual address range.
> > + *
> > + * Return: None
> > + */
> > +void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size)
> > +{
> > + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
> > + (unsigned long)hart_mask, start, size, 0, 0, 0);
> > +}
> > +EXPORT_SYMBOL(sbi_remote_sfence_vma);
> > +
> > +/**
> > + * sbi_remote_sfence_vma_asid() - Execute SFENCE.VMA instructions on given
> > + * remote harts for a virtual address range belonging to a specific ASID.
> > + *
> > + * @hart_mask: A cpu mask containing all the target harts.
> > + * @start: Start of the virtual address
> > + * @size: Total size of the virtual address range.
> > + * @asid: The value of address space identifier (ASID).
> > + *
> > + * Return: None
> > + */
> > +void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> > + unsigned long start,
> > + unsigned long size,
> > + unsigned long asid)
> > +{
> > + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
> > + (unsigned long)hart_mask, start, size, asid, 0, 0);
> > +}
> > +EXPORT_SYMBOL(sbi_remote_sfence_vma_asid);
> > +
> > +/**
> > + * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
> > + * @extid: The extension ID to be probed.
> > + *
> > + * Return: Extension specific nonzero value f yes, -ENOTSUPP otherwise.
> > + */
> > +int sbi_probe_extension(int extid)
> > +{
> > + struct sbiret ret;
> > +
> > + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, extid,
> > + 0, 0, 0, 0, 0);
> > + if (!ret.error)
> > + if (ret.value)
> > + return ret.value;
> > +
> > + return -ENOTSUPP;
> > +}
> > +EXPORT_SYMBOL(sbi_probe_extension);
> > +
> > +static long __sbi_base_ecall(int fid)
> > +{
> > + struct sbiret ret;
> > +
> > + ret = sbi_ecall(SBI_EXT_BASE, fid, 0, 0, 0, 0, 0, 0);
> > + if (!ret.error)
> > + return ret.value;
> > + else
> > + return sbi_err_map_linux_errno(ret.error);
> > +}
> > +
> > +static inline long sbi_get_spec_version(void)
> > +{
> > + return __sbi_base_ecall(SBI_EXT_BASE_GET_SPEC_VERSION);
> > +}
> > +
> > +static inline long sbi_get_firmware_id(void)
> > +{
> > + return __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_ID);
> > +}
> > +
> > +static inline long sbi_get_firmware_version(void)
> > +{
> > + return __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_VERSION);
> > +}
> > +
> > static void sbi_power_off(void)
> > {
> > sbi_shutdown();
> > }
> >
> > -static int __init sbi_init(void)
> > +int __init sbi_init(void)
> > {
> > + int ret;
> > +
> > pm_power_off = sbi_power_off;
> > + ret = sbi_get_spec_version();
> > + if (ret > 0)
> > + sbi_spec_version = ret;
> > +
> > + pr_info("SBI specification v%lu.%lu detected\n",
> > + sbi_major_version(), sbi_minor_version());
> > + if (!sbi_spec_is_0_1())
> > + pr_info("SBI implementation ID=0x%lx Version=0x%lx\n",
> > + sbi_get_firmware_id(), sbi_get_firmware_version());
> > return 0;
> > }
> > -early_initcall(sbi_init);
> > diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> > index 365ff8420bfe..de3e65dae83a 100644
> > --- a/arch/riscv/kernel/setup.c
> > +++ b/arch/riscv/kernel/setup.c
> > @@ -22,6 +22,7 @@
> > #include <asm/sections.h>
> > #include <asm/pgtable.h>
> > #include <asm/smp.h>
> > +#include <asm/sbi.h>
> > #include <asm/tlbflush.h>
> > #include <asm/thread_info.h>
> >
> > @@ -74,6 +75,9 @@ void __init setup_arch(char **cmdline_p)
> > swiotlb_init(1);
> > #endif
> >
> > + if (IS_ENABLED(CONFIG_RISCV_SBI))
> > + sbi_init();
> > +
>
> This has to "#if IS_ENABLED(CONFIG_RISCV_SBI)" instead of
> "if ()".
>
I am using it as a conditional statement. So I think usage is correct.
Do you mean #if IS_ENABLED preferred over if() ?
> Regards,
> Anup
>
> > #ifdef CONFIG_SMP
> > setup_smp();
> > #endif
> > --
> > 2.24.0
> >
>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v7 02/10] RISC-V: Add basic support for SBI v0.2
2020-01-28 19:12 ` Atish Patra
@ 2020-02-06 6:24 ` Anup Patel
0 siblings, 0 replies; 22+ messages in thread
From: Anup Patel @ 2020-02-06 6:24 UTC (permalink / raw)
To: Atish Patra
Cc: Albert Ou, Kees Cook, nickhu, Vincent Chen, Greg Kroah-Hartman,
Palmer Dabbelt, Heiko Carstens,
linux-kernel@vger.kernel.org List, Mike Rapoport, Chester Lin,
Atish Patra, Palmer Dabbelt, Geert Uytterhoeven,
Eric W. Biederman, Paul Walmsley, Greentime Hu, Thomas Gleixner,
Borislav Petkov, Abner Chang, linux-riscv, Mao Han
On Wed, Jan 29, 2020 at 12:42 AM Atish Patra <atishp@atishpatra.org> wrote:
>
> On Mon, Jan 27, 2020 at 8:25 PM Anup Patel <anup@brainfault.org> wrote:
> >
> > On Tue, Jan 28, 2020 at 7:58 AM Atish Patra <atish.patra@wdc.com> wrote:
> > >
> > > The SBI v0.2 introduces a base extension which is backward compatible
> > > with v0.1. Implement all helper functions and minimum required SBI
> > > calls from v0.2 for now. All other base extension function will be
> > > added later as per need.
> > > As v0.2 calling convention is backward compatible with v0.1, remove
> > > the v0.1 helper functions and just use v0.2 calling convention.
> > >
> > > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > > Reviewed-by: Anup Patel <anup@brainfault.org>
> > > Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> > > ---
> > > arch/riscv/include/asm/sbi.h | 140 ++++++++++----------
> > > arch/riscv/kernel/sbi.c | 243 ++++++++++++++++++++++++++++++++++-
> > > arch/riscv/kernel/setup.c | 4 +
> > > 3 files changed, 313 insertions(+), 74 deletions(-)
> > >
> > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> > > index b38bc36f7429..fbdb7443784a 100644
> > > --- a/arch/riscv/include/asm/sbi.h
> > > +++ b/arch/riscv/include/asm/sbi.h
> > > @@ -10,93 +10,88 @@
> > > #include <linux/types.h>
> > >
> > > #ifdef CONFIG_RISCV_SBI
> > > -#define SBI_EXT_0_1_SET_TIMER 0x0
> > > -#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
> > > -#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
> > > -#define SBI_EXT_0_1_CLEAR_IPI 0x3
> > > -#define SBI_EXT_0_1_SEND_IPI 0x4
> > > -#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
> > > -#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
> > > -#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
> > > -#define SBI_EXT_0_1_SHUTDOWN 0x8
> > > +enum sbi_ext_id {
> > > + SBI_EXT_0_1_SET_TIMER = 0x0,
> > > + SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
> > > + SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
> > > + SBI_EXT_0_1_CLEAR_IPI = 0x3,
> > > + SBI_EXT_0_1_SEND_IPI = 0x4,
> > > + SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
> > > + SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
> > > + SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
> > > + SBI_EXT_0_1_SHUTDOWN = 0x8,
> > > + SBI_EXT_BASE = 0x10,
> > > +};
> > >
> > > -#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({ \
> > > - register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
> > > - register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
> > > - register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
> > > - register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3); \
> > > - register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \
> > > - asm volatile ("ecall" \
> > > - : "+r" (a0) \
> > > - : "r" (a1), "r" (a2), "r" (a3), "r" (a7) \
> > > - : "memory"); \
> > > - a0; \
> > > -})
> > > +enum sbi_ext_base_fid {
> > > + SBI_EXT_BASE_GET_SPEC_VERSION = 0,
> > > + SBI_EXT_BASE_GET_IMP_ID,
> > > + SBI_EXT_BASE_GET_IMP_VERSION,
> > > + SBI_EXT_BASE_PROBE_EXT,
> > > + SBI_EXT_BASE_GET_MVENDORID,
> > > + SBI_EXT_BASE_GET_MARCHID,
> > > + SBI_EXT_BASE_GET_MIMPID,
> > > +};
> > >
> > > -/* Lazy implementations until SBI is finalized */
> > > -#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0, 0)
> > > -#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0, 0)
> > > -#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0, 0)
> > > -#define SBI_CALL_3(which, arg0, arg1, arg2) \
> > > - SBI_CALL(which, arg0, arg1, arg2, 0)
> > > -#define SBI_CALL_4(which, arg0, arg1, arg2, arg3) \
> > > - SBI_CALL(which, arg0, arg1, arg2, arg3)
> > > +#define SBI_SPEC_VERSION_DEFAULT 0x1
> > > +#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
> > > +#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
> > > +#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
> > >
> > > -static inline void sbi_console_putchar(int ch)
> > > -{
> > > - SBI_CALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, ch);
> > > -}
> > > +/* SBI return error codes */
> > > +#define SBI_SUCCESS 0
> > > +#define SBI_ERR_FAILURE -1
> > > +#define SBI_ERR_NOT_SUPPORTED -2
> > > +#define SBI_ERR_INVALID_PARAM -3
> > > +#define SBI_ERR_DENIED -4
> > > +#define SBI_ERR_INVALID_ADDRESS -5
> > >
> > > -static inline int sbi_console_getchar(void)
> > > -{
> > > - return SBI_CALL_0(SBI_EXT_0_1_CONSOLE_GETCHAR);
> > > -}
> > > +extern unsigned long sbi_spec_version;
> > > +struct sbiret {
> > > + long error;
> > > + long value;
> > > +};
> > >
> > > -static inline void sbi_set_timer(uint64_t stime_value)
> > > -{
> > > -#if __riscv_xlen == 32
> > > - SBI_CALL_2(SBI_EXT_0_1_SET_TIMER, stime_value,
> > > - stime_value >> 32);
> > > -#else
> > > - SBI_CALL_1(SBI_EXT_0_1_SET_TIMER, stime_value);
> > > -#endif
> > > -}
> > > -
> > > -static inline void sbi_shutdown(void)
> > > -{
> > > - SBI_CALL_0(SBI_EXT_0_1_SHUTDOWN);
> > > -}
> > > +int sbi_init(void);
> > > +struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> > > + unsigned long arg1, unsigned long arg2,
> > > + unsigned long arg3, unsigned long arg4,
> > > + unsigned long arg5);
> > >
> > > -static inline void sbi_clear_ipi(void)
> > > -{
> > > - SBI_CALL_0(SBI_EXT_0_1_CLEAR_IPI);
> > > -}
> > > +void sbi_console_putchar(int ch);
> > > +int sbi_console_getchar(void);
> > > +void sbi_set_timer(uint64_t stime_value);
> > > +void sbi_shutdown(void);
> > > +void sbi_clear_ipi(void);
> > > +void sbi_send_ipi(const unsigned long *hart_mask);
> > > +void sbi_remote_fence_i(const unsigned long *hart_mask);
> > > +void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> > > + unsigned long start,
> > > + unsigned long size);
> > >
> > > -static inline void sbi_send_ipi(const unsigned long *hart_mask)
> > > -{
> > > - SBI_CALL_1(SBI_EXT_0_1_SEND_IPI, hart_mask);
> > > -}
> > > +void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> > > + unsigned long start,
> > > + unsigned long size,
> > > + unsigned long asid);
> > > +int sbi_probe_extension(int ext);
> > >
> > > -static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
> > > +/* Check if current SBI specification version is 0.1 or not */
> > > +static inline int sbi_spec_is_0_1(void)
> > > {
> > > - SBI_CALL_1(SBI_EXT_0_1_REMOTE_FENCE_I, hart_mask);
> > > + return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT) ? 1 : 0;
> > > }
> > >
> > > -static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> > > - unsigned long start,
> > > - unsigned long size)
> > > +/* Get the major version of SBI */
> > > +static inline unsigned long sbi_major_version(void)
> > > {
> > > - SBI_CALL_3(SBI_EXT_0_1_REMOTE_SFENCE_VMA, hart_mask,
> > > - start, size);
> > > + return (sbi_spec_version >> SBI_SPEC_VERSION_MAJOR_SHIFT) &
> > > + SBI_SPEC_VERSION_MAJOR_MASK;
> > > }
> > >
> > > -static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> > > - unsigned long start,
> > > - unsigned long size,
> > > - unsigned long asid)
> > > +/* Get the minor version of SBI */
> > > +static inline unsigned long sbi_minor_version(void)
> > > {
> > > - SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask,
> > > - start, size, asid);
> > > + return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK;
> > > }
> > > #else /* CONFIG_RISCV_SBI */
> > > /* stubs for code that is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
> > > @@ -104,5 +99,6 @@ void sbi_set_timer(uint64_t stime_value);
> > > void sbi_clear_ipi(void);
> > > void sbi_send_ipi(const unsigned long *hart_mask);
> > > void sbi_remote_fence_i(const unsigned long *hart_mask);
> > > +void sbi_init(void);
> > > #endif /* CONFIG_RISCV_SBI */
> > > #endif /* _ASM_RISCV_SBI_H */
> > > diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> > > index f6c7c3e82d28..33632e7f91da 100644
> > > --- a/arch/riscv/kernel/sbi.c
> > > +++ b/arch/riscv/kernel/sbi.c
> > > @@ -1,17 +1,256 @@
> > > // SPDX-License-Identifier: GPL-2.0-only
> > > +/*
> > > + * SBI initialilization and all extension implementation.
> > > + *
> > > + * Copyright (c) 2019 Western Digital Corporation or its affiliates.
> > > + */
> > >
> > > #include <linux/init.h>
> > > #include <linux/pm.h>
> > > #include <asm/sbi.h>
> > >
> > > +/* default SBI version is 0.1 */
> > > +unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT;
> > > +EXPORT_SYMBOL(sbi_spec_version);
> > > +
> > > +struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> > > + unsigned long arg1, unsigned long arg2,
> > > + unsigned long arg3, unsigned long arg4,
> > > + unsigned long arg5)
> > > +{
> > > + struct sbiret ret;
> > > +
> > > + register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
> > > + register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
> > > + register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
> > > + register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
> > > + register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
> > > + register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
> > > + register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
> > > + register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
> > > + asm volatile ("ecall"
> > > + : "+r" (a0), "+r" (a1)
> > > + : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
> > > + : "memory");
> > > + ret.error = a0;
> > > + ret.value = a1;
> > > +
> > > + return ret;
> > > +}
> > > +EXPORT_SYMBOL(sbi_ecall);
> > > +
> > > +static int sbi_err_map_linux_errno(int err)
> > > +{
> > > + switch (err) {
> > > + case SBI_SUCCESS:
> > > + return 0;
> > > + case SBI_ERR_DENIED:
> > > + return -EPERM;
> > > + case SBI_ERR_INVALID_PARAM:
> > > + return -EINVAL;
> > > + case SBI_ERR_INVALID_ADDRESS:
> > > + return -EFAULT;
> > > + case SBI_ERR_NOT_SUPPORTED:
> > > + case SBI_ERR_FAILURE:
> > > + default:
> > > + return -ENOTSUPP;
> > > + };
> > > +}
> > > +
> > > +/**
> > > + * sbi_console_putchar() - Writes given character to the console device.
> > > + * @ch: The data to be written to the console.
> > > + *
> > > + * Return: None
> > > + */
> > > +void sbi_console_putchar(int ch)
> > > +{
> > > + sbi_ecall(SBI_EXT_0_1_CONSOLE_PUTCHAR, 0, ch, 0, 0, 0, 0, 0);
> > > +}
> > > +EXPORT_SYMBOL(sbi_console_putchar);
> > > +
> > > +/**
> > > + * sbi_console_getchar() - Reads a byte from console device.
> > > + *
> > > + * Returns the value read from console.
> > > + */
> > > +int sbi_console_getchar(void)
> > > +{
> > > + struct sbiret ret;
> > > +
> > > + ret = sbi_ecall(SBI_EXT_0_1_CONSOLE_GETCHAR, 0, 0, 0, 0, 0, 0, 0);
> > > +
> > > + return ret.error;
> > > +}
> > > +EXPORT_SYMBOL(sbi_console_getchar);
> > > +
> > > +/**
> > > + * sbi_set_timer() - Program the timer for next timer event.
> > > + * @stime_value: The value after which next timer event should fire.
> > > + *
> > > + * Return: None
> > > + */
> > > +void sbi_set_timer(uint64_t stime_value)
> > > +{
> > > +#if __riscv_xlen == 32
> > > + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
> > > + stime_value >> 32, 0, 0, 0, 0);
> > > +#else
> > > + sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
> > > +#endif
> > > +}
> > > +EXPORT_SYMBOL(sbi_set_timer);
> > > +
> > > +/**
> > > + * sbi_shutdown() - Remove all the harts from executing supervisor code.
> > > + *
> > > + * Return: None
> > > + */
> > > +void sbi_shutdown(void)
> > > +{
> > > + sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
> > > +}
> > > +EXPORT_SYMBOL(sbi_shutdown);
> > > +
> > > +/**
> > > + * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
> > > + *
> > > + * Return: None
> > > + */
> > > +void sbi_clear_ipi(void)
> > > +{
> > > + sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0);
> > > +}
> > > +
> > > +/**
> > > + * sbi_send_ipi() - Send an IPI to any hart.
> > > + * @hart_mask: A cpu mask containing all the target harts.
> > > + *
> > > + * Return: None
> > > + */
> > > +void sbi_send_ipi(const unsigned long *hart_mask)
> > > +{
> > > + sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
> > > + 0, 0, 0, 0, 0);
> > > +}
> > > +EXPORT_SYMBOL(sbi_send_ipi);
> > > +
> > > +/**
> > > + * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
> > > + * @hart_mask: A cpu mask containing all the target harts.
> > > + *
> > > + * Return: None
> > > + */
> > > +void sbi_remote_fence_i(const unsigned long *hart_mask)
> > > +{
> > > + sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned long)hart_mask,
> > > + 0, 0, 0, 0, 0);
> > > +}
> > > +EXPORT_SYMBOL(sbi_remote_fence_i);
> > > +
> > > +/**
> > > + * sbi_remote_sfence_vma() - Execute SFENCE.VMA instructions on given remote
> > > + * harts for the specified virtual address range.
> > > + * @hart_mask: A cpu mask containing all the target harts.
> > > + * @start: Start of the virtual address
> > > + * @size: Total size of the virtual address range.
> > > + *
> > > + * Return: None
> > > + */
> > > +void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> > > + unsigned long start,
> > > + unsigned long size)
> > > +{
> > > + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
> > > + (unsigned long)hart_mask, start, size, 0, 0, 0);
> > > +}
> > > +EXPORT_SYMBOL(sbi_remote_sfence_vma);
> > > +
> > > +/**
> > > + * sbi_remote_sfence_vma_asid() - Execute SFENCE.VMA instructions on given
> > > + * remote harts for a virtual address range belonging to a specific ASID.
> > > + *
> > > + * @hart_mask: A cpu mask containing all the target harts.
> > > + * @start: Start of the virtual address
> > > + * @size: Total size of the virtual address range.
> > > + * @asid: The value of address space identifier (ASID).
> > > + *
> > > + * Return: None
> > > + */
> > > +void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> > > + unsigned long start,
> > > + unsigned long size,
> > > + unsigned long asid)
> > > +{
> > > + sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
> > > + (unsigned long)hart_mask, start, size, asid, 0, 0);
> > > +}
> > > +EXPORT_SYMBOL(sbi_remote_sfence_vma_asid);
> > > +
> > > +/**
> > > + * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
> > > + * @extid: The extension ID to be probed.
> > > + *
> > > + * Return: Extension specific nonzero value f yes, -ENOTSUPP otherwise.
> > > + */
> > > +int sbi_probe_extension(int extid)
> > > +{
> > > + struct sbiret ret;
> > > +
> > > + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, extid,
> > > + 0, 0, 0, 0, 0);
> > > + if (!ret.error)
> > > + if (ret.value)
> > > + return ret.value;
> > > +
> > > + return -ENOTSUPP;
> > > +}
> > > +EXPORT_SYMBOL(sbi_probe_extension);
> > > +
> > > +static long __sbi_base_ecall(int fid)
> > > +{
> > > + struct sbiret ret;
> > > +
> > > + ret = sbi_ecall(SBI_EXT_BASE, fid, 0, 0, 0, 0, 0, 0);
> > > + if (!ret.error)
> > > + return ret.value;
> > > + else
> > > + return sbi_err_map_linux_errno(ret.error);
> > > +}
> > > +
> > > +static inline long sbi_get_spec_version(void)
> > > +{
> > > + return __sbi_base_ecall(SBI_EXT_BASE_GET_SPEC_VERSION);
> > > +}
> > > +
> > > +static inline long sbi_get_firmware_id(void)
> > > +{
> > > + return __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_ID);
> > > +}
> > > +
> > > +static inline long sbi_get_firmware_version(void)
> > > +{
> > > + return __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_VERSION);
> > > +}
> > > +
> > > static void sbi_power_off(void)
> > > {
> > > sbi_shutdown();
> > > }
> > >
> > > -static int __init sbi_init(void)
> > > +int __init sbi_init(void)
> > > {
> > > + int ret;
> > > +
> > > pm_power_off = sbi_power_off;
> > > + ret = sbi_get_spec_version();
> > > + if (ret > 0)
> > > + sbi_spec_version = ret;
> > > +
> > > + pr_info("SBI specification v%lu.%lu detected\n",
> > > + sbi_major_version(), sbi_minor_version());
> > > + if (!sbi_spec_is_0_1())
> > > + pr_info("SBI implementation ID=0x%lx Version=0x%lx\n",
> > > + sbi_get_firmware_id(), sbi_get_firmware_version());
> > > return 0;
> > > }
> > > -early_initcall(sbi_init);
> > > diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> > > index 365ff8420bfe..de3e65dae83a 100644
> > > --- a/arch/riscv/kernel/setup.c
> > > +++ b/arch/riscv/kernel/setup.c
> > > @@ -22,6 +22,7 @@
> > > #include <asm/sections.h>
> > > #include <asm/pgtable.h>
> > > #include <asm/smp.h>
> > > +#include <asm/sbi.h>
> > > #include <asm/tlbflush.h>
> > > #include <asm/thread_info.h>
> > >
> > > @@ -74,6 +75,9 @@ void __init setup_arch(char **cmdline_p)
> > > swiotlb_init(1);
> > > #endif
> > >
> > > + if (IS_ENABLED(CONFIG_RISCV_SBI))
> > > + sbi_init();
> > > +
> >
> > This has to "#if IS_ENABLED(CONFIG_RISCV_SBI)" instead of
> > "if ()".
> >
> I am using it as a conditional statement. So I think usage is correct.
> Do you mean #if IS_ENABLED preferred over if() ?
Yes, I mean use "#if IS_ENABLED()".
Regards,
Anup
>
> > Regards,
> > Anup
> >
> > > #ifdef CONFIG_SMP
> > > setup_smp();
> > > #endif
> > > --
> > > 2.24.0
> > >
> >
>
>
> --
> Regards,
> Atish
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v7 03/10] RISC-V: Add SBI v0.2 extension definitions
2020-01-28 2:27 [PATCH v7 00/10] Add support for SBI v0.2 and CPU hotplug Atish Patra
2020-01-28 2:27 ` [PATCH v7 01/10] RISC-V: Mark existing SBI as 0.1 SBI Atish Patra
2020-01-28 2:27 ` [PATCH v7 02/10] RISC-V: Add basic support for SBI v0.2 Atish Patra
@ 2020-01-28 2:27 ` Atish Patra
2020-01-28 2:27 ` [PATCH v7 04/10] RISC-V: Introduce a new config for SBI v0.1 Atish Patra
` (6 subsequent siblings)
9 siblings, 0 replies; 22+ messages in thread
From: Atish Patra @ 2020-01-28 2:27 UTC (permalink / raw)
To: linux-kernel
Cc: Albert Ou, Thomas Gleixner, Kees Cook, abner.chang, Vincent Chen,
nickhu, Anup Patel, Palmer Dabbelt, Heiko Carstens,
Mike Rapoport, clin, Atish Patra, Geert Uytterhoeven,
Eric W. Biederman, Paul Walmsley, Greg Kroah-Hartman,
Greentime Hu, linux-riscv, Borislav Petkov, Palmer Dabbelt,
Mao Han
Few v0.1 SBI calls are being replaced by new SBI calls that follows
v0.2 calling convention.
This patch just defines these new extensions.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
arch/riscv/include/asm/sbi.h | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index fbdb7443784a..e478368a47f3 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -21,6 +21,9 @@ enum sbi_ext_id {
SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
SBI_EXT_0_1_SHUTDOWN = 0x8,
SBI_EXT_BASE = 0x10,
+ SBI_EXT_TIME = 0x54494D45,
+ SBI_EXT_IPI = 0x735049,
+ SBI_EXT_RFENCE = 0x52464E43,
};
enum sbi_ext_base_fid {
@@ -33,6 +36,24 @@ enum sbi_ext_base_fid {
SBI_EXT_BASE_GET_MIMPID,
};
+enum sbi_ext_time_fid {
+ SBI_EXT_TIME_SET_TIMER = 0,
+};
+
+enum sbi_ext_ipi_fid {
+ SBI_EXT_IPI_SEND_IPI = 0,
+};
+
+enum sbi_ext_rfence_fid {
+ SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
+ SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
+ SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
+ SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
+};
+
#define SBI_SPEC_VERSION_DEFAULT 0x1
#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
--
2.24.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v7 04/10] RISC-V: Introduce a new config for SBI v0.1
2020-01-28 2:27 [PATCH v7 00/10] Add support for SBI v0.2 and CPU hotplug Atish Patra
` (2 preceding siblings ...)
2020-01-28 2:27 ` [PATCH v7 03/10] RISC-V: Add SBI v0.2 extension definitions Atish Patra
@ 2020-01-28 2:27 ` Atish Patra
2020-01-28 2:27 ` [PATCH v7 05/10] RISC-V: Implement new SBI v0.2 extensions Atish Patra
` (5 subsequent siblings)
9 siblings, 0 replies; 22+ messages in thread
From: Atish Patra @ 2020-01-28 2:27 UTC (permalink / raw)
To: linux-kernel
Cc: Albert Ou, Thomas Gleixner, Kees Cook, abner.chang, Vincent Chen,
nickhu, Anup Patel, Paul Walmsley, Heiko Carstens, Mike Rapoport,
clin, Atish Patra, Geert Uytterhoeven, Eric W. Biederman,
Greg Kroah-Hartman, Palmer Dabbelt, Greentime Hu, linux-riscv,
Borislav Petkov, Palmer Dabbelt, Mao Han
We now have SBI v0.2 which is more scalable and extendable to handle
future needs for RISC-V supervisor interfaces.
Introduce a new config and move all SBI v0.1 code under that config.
This allows to implement the new replacement SBI extensions cleanly
and remove v0.1 extensions easily in future. Currently, the config
is enabled by default. Once all M-mode software, with v0.1, is no
longer in use, this config option and all relevant code can be easily
removed.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
arch/riscv/Kconfig | 6 ++
arch/riscv/include/asm/sbi.h | 2 +
arch/riscv/kernel/sbi.c | 137 +++++++++++++++++++++++++++++------
3 files changed, 121 insertions(+), 24 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fa7dc03459e7..518da42be545 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -307,6 +307,12 @@ config SECCOMP
and the task is only allowed to execute a few safe syscalls
defined by each seccomp mode.
+config RISCV_SBI_V01
+ bool "SBI v0.1 support"
+ default y
+ help
+ This config allows kernel to use SBI v0.1 APIs. This will be
+ deprecated in future once legacy M-mode software are no longer in use.
endmenu
menu "Boot options"
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index e478368a47f3..4d67bef8f894 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -11,6 +11,7 @@
#ifdef CONFIG_RISCV_SBI
enum sbi_ext_id {
+#ifdef CONFIG_RISCV_SBI_V01
SBI_EXT_0_1_SET_TIMER = 0x0,
SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
@@ -20,6 +21,7 @@ enum sbi_ext_id {
SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
SBI_EXT_0_1_SHUTDOWN = 0x8,
+#endif
SBI_EXT_BASE = 0x10,
SBI_EXT_TIME = 0x54494D45,
SBI_EXT_IPI = 0x735049,
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 33632e7f91da..265637cb5eb0 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -13,6 +13,13 @@
unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT;
EXPORT_SYMBOL(sbi_spec_version);
+static void (*__sbi_set_timer)(uint64_t stime);
+static int (*__sbi_send_ipi)(const unsigned long *hart_mask);
+static int (*__sbi_rfence)(int fid, const unsigned long *hart_mask,
+ unsigned long hbase, unsigned long start,
+ unsigned long size, unsigned long arg4,
+ unsigned long arg5);
+
struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
unsigned long arg1, unsigned long arg2,
unsigned long arg3, unsigned long arg4,
@@ -57,6 +64,7 @@ static int sbi_err_map_linux_errno(int err)
};
}
+#ifdef CONFIG_RISCV_SBI_V01
/**
* sbi_console_putchar() - Writes given character to the console device.
* @ch: The data to be written to the console.
@@ -85,41 +93,115 @@ int sbi_console_getchar(void)
EXPORT_SYMBOL(sbi_console_getchar);
/**
- * sbi_set_timer() - Program the timer for next timer event.
- * @stime_value: The value after which next timer event should fire.
+ * sbi_shutdown() - Remove all the harts from executing supervisor code.
*
* Return: None
*/
-void sbi_set_timer(uint64_t stime_value)
+void sbi_shutdown(void)
{
-#if __riscv_xlen == 32
- sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
- stime_value >> 32, 0, 0, 0, 0);
-#else
- sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
-#endif
+ sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
}
EXPORT_SYMBOL(sbi_set_timer);
/**
- * sbi_shutdown() - Remove all the harts from executing supervisor code.
+ * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
*
* Return: None
*/
-void sbi_shutdown(void)
+void sbi_clear_ipi(void)
{
- sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
+ sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0);
}
EXPORT_SYMBOL(sbi_shutdown);
/**
- * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
+ * sbi_set_timer_v01() - Program the timer for next timer event.
+ * @stime_value: The value after which next timer event should fire.
*
* Return: None
*/
-void sbi_clear_ipi(void)
+static void __sbi_set_timer_v01(uint64_t stime_value)
{
- sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0);
+#if __riscv_xlen == 32
+ sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
+ stime_value >> 32, 0, 0, 0, 0);
+#else
+ sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
+#endif
+}
+
+static int __sbi_send_ipi_v01(const unsigned long *hart_mask)
+{
+ sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
+ 0, 0, 0, 0, 0);
+ return 0;
+}
+
+static int __sbi_rfence_v01(int fid, const unsigned long *hart_mask,
+ unsigned long hbase, unsigned long start,
+ unsigned long size, unsigned long arg4,
+ unsigned long arg5)
+{
+ int result = 0;
+
+ /* v0.2 function IDs are equivalent to v0.1 extension IDs */
+ switch (fid) {
+ case SBI_EXT_RFENCE_REMOTE_FENCE_I:
+ sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0,
+ (unsigned long)hart_mask, 0, 0, 0, 0, 0);
+ break;
+ case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA:
+ sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
+ (unsigned long)hart_mask, start, size,
+ 0, 0, 0);
+ break;
+ case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID:
+ sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
+ (unsigned long)hart_mask, start, size,
+ arg4, 0, 0);
+ break;
+ default:
+ pr_err("SBI call [%d]not supported in SBI v0.1\n", fid);
+ result = -EINVAL;
+ }
+
+ return result;
+}
+#else
+static void __sbi_set_timer_v01(uint64_t stime_value)
+{
+ pr_warn("Timer extension is not available in SBI v%lu.%lu\n",
+ sbi_major_version(), sbi_minor_version());
+}
+static int __sbi_send_ipi_v01(const unsigned long *hart_mask)
+{
+ pr_warn("IPI extension is not available in SBI v%lu.%lu\n",
+ sbi_major_version(), sbi_minor_version());
+
+ return 0;
+}
+static int __sbi_rfence_v01(int fid,
+ const unsigned long *hart_mask,
+ unsigned long hbase, unsigned long start,
+ unsigned long size, unsigned long arg4,
+ unsigned long arg5)
+{
+ pr_warn("remote fence extension is not available in SBI v%lu.%lu\n",
+ sbi_major_version(), sbi_minor_version());
+
+ return 0;
+}
+#endif /* CONFIG_RISCV_SBI_V01 */
+
+/**
+ * sbi_set_timer() - Program the timer for next timer event.
+ * @stime_value: The value after which next timer event should fire.
+ *
+ * Return: None
+ */
+void sbi_set_timer(uint64_t stime_value)
+{
+ __sbi_set_timer(stime_value);
}
/**
@@ -130,11 +212,11 @@ void sbi_clear_ipi(void)
*/
void sbi_send_ipi(const unsigned long *hart_mask)
{
- sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
- 0, 0, 0, 0, 0);
+ __sbi_send_ipi(hart_mask);
}
EXPORT_SYMBOL(sbi_send_ipi);
+
/**
* sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
* @hart_mask: A cpu mask containing all the target harts.
@@ -143,8 +225,8 @@ EXPORT_SYMBOL(sbi_send_ipi);
*/
void sbi_remote_fence_i(const unsigned long *hart_mask)
{
- sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned long)hart_mask,
- 0, 0, 0, 0, 0);
+ __sbi_rfence(SBI_EXT_RFENCE_REMOTE_FENCE_I,
+ hart_mask, 0, 0, 0, 0, 0);
}
EXPORT_SYMBOL(sbi_remote_fence_i);
@@ -161,8 +243,8 @@ void sbi_remote_sfence_vma(const unsigned long *hart_mask,
unsigned long start,
unsigned long size)
{
- sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
- (unsigned long)hart_mask, start, size, 0, 0, 0);
+ __sbi_rfence(SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
+ hart_mask, 0, start, size, 0, 0);
}
EXPORT_SYMBOL(sbi_remote_sfence_vma);
@@ -182,8 +264,8 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
unsigned long size,
unsigned long asid)
{
- sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
- (unsigned long)hart_mask, start, size, asid, 0, 0);
+ __sbi_rfence(SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
+ hart_mask, 0, start, size, asid, 0);
}
EXPORT_SYMBOL(sbi_remote_sfence_vma_asid);
@@ -249,8 +331,15 @@ int __init sbi_init(void)
pr_info("SBI specification v%lu.%lu detected\n",
sbi_major_version(), sbi_minor_version());
- if (!sbi_spec_is_0_1())
+
+ if (!sbi_spec_is_0_1()) {
pr_info("SBI implementation ID=0x%lx Version=0x%lx\n",
sbi_get_firmware_id(), sbi_get_firmware_version());
+ }
+
+ __sbi_set_timer = __sbi_set_timer_v01;
+ __sbi_send_ipi = __sbi_send_ipi_v01;
+ __sbi_rfence = __sbi_rfence_v01;
+
return 0;
}
--
2.24.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v7 05/10] RISC-V: Implement new SBI v0.2 extensions
2020-01-28 2:27 [PATCH v7 00/10] Add support for SBI v0.2 and CPU hotplug Atish Patra
` (3 preceding siblings ...)
2020-01-28 2:27 ` [PATCH v7 04/10] RISC-V: Introduce a new config for SBI v0.1 Atish Patra
@ 2020-01-28 2:27 ` Atish Patra
2020-01-28 2:27 ` [PATCH v7 06/10] RISC-V: Add cpu_ops and modify default booting method Atish Patra
` (4 subsequent siblings)
9 siblings, 0 replies; 22+ messages in thread
From: Atish Patra @ 2020-01-28 2:27 UTC (permalink / raw)
To: linux-kernel
Cc: Albert Ou, Thomas Gleixner, Kees Cook, abner.chang, Vincent Chen,
nickhu, Anup Patel, Paul Walmsley, Heiko Carstens, Mike Rapoport,
clin, Atish Patra, Geert Uytterhoeven, Eric W. Biederman,
Greg Kroah-Hartman, Palmer Dabbelt, Greentime Hu, linux-riscv,
Borislav Petkov, Palmer Dabbelt, Mao Han
Few v0.1 SBI calls are being replaced by new SBI calls that follows v0.2
calling convention.
Implement the replacement extensions and few additional new SBI function calls
that makes way for a better SBI interface in future.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
arch/riscv/include/asm/sbi.h | 14 +++
arch/riscv/include/asm/smp.h | 7 ++
arch/riscv/kernel/sbi.c | 199 ++++++++++++++++++++++++++++++++++-
3 files changed, 216 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 4d67bef8f894..d55d8090ab5c 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -96,6 +96,20 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
unsigned long start,
unsigned long size,
unsigned long asid);
+int sbi_remote_hfence_gvma(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size);
+int sbi_remote_hfence_gvma_vmid(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size,
+ unsigned long vmid);
+int sbi_remote_hfence_vvma(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size);
+int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size,
+ unsigned long asid);
int sbi_probe_extension(int ext);
/* Check if current SBI specification version is 0.1 or not */
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index a83451d73a4e..023f74fb8b3b 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -61,5 +61,12 @@ static inline unsigned long cpuid_to_hartid_map(int cpu)
return boot_cpu_hartid;
}
+static inline void riscv_cpuid_to_hartid_mask(const struct cpumask *in,
+ struct cpumask *out)
+{
+ cpumask_clear(out);
+ cpumask_set_cpu(boot_cpu_hartid, out);
+}
+
#endif /* CONFIG_SMP */
#endif /* _ASM_RISCV_SMP_H */
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 265637cb5eb0..3c34aba30f6f 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -8,6 +8,7 @@
#include <linux/init.h>
#include <linux/pm.h>
#include <asm/sbi.h>
+#include <asm/smp.h>
/* default SBI version is 0.1 */
unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT;
@@ -193,6 +194,102 @@ static int __sbi_rfence_v01(int fid,
}
#endif /* CONFIG_RISCV_SBI_V01 */
+static void __sbi_set_timer_v02(uint64_t stime_value)
+{
+#if __riscv_xlen == 32
+ sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value,
+ stime_value >> 32, 0, 0, 0, 0);
+#else
+ sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, 0,
+ 0, 0, 0, 0);
+#endif
+}
+
+static int __sbi_send_ipi_v02(const unsigned long *hart_mask)
+{
+ unsigned long hmask_val;
+ struct cpumask tmask;
+ struct sbiret ret = {0};
+ int result;
+
+ if (!hart_mask) {
+ riscv_cpuid_to_hartid_mask(cpu_online_mask, &tmask);
+ hmask_val = *(cpumask_bits(&tmask));
+ } else
+ hmask_val = *hart_mask;
+
+ ret = sbi_ecall(SBI_EXT_IPI, SBI_EXT_IPI_SEND_IPI, hmask_val,
+ 0, 0, 0, 0, 0);
+ if (ret.error) {
+ result = sbi_err_map_linux_errno(ret.error);
+ pr_err("%s: failed with error [%d]\n", __func__, result);
+ } else
+ result = ret.value;
+
+ return result;
+}
+
+static int __sbi_rfence_v02(int fid, const unsigned long *hart_mask,
+ unsigned long hbase, unsigned long start,
+ unsigned long size, unsigned long arg4,
+ unsigned long arg5)
+{
+ unsigned long hmask_val;
+ struct cpumask tmask;
+ struct sbiret ret = {0};
+ int ext = SBI_EXT_RFENCE;
+ int result;
+
+ if (!hart_mask) {
+ riscv_cpuid_to_hartid_mask(cpu_online_mask, &tmask);
+ hmask_val = *(cpumask_bits(&tmask));
+ } else
+ hmask_val = *hart_mask;
+
+ switch (fid) {
+ case SBI_EXT_RFENCE_REMOTE_FENCE_I:
+ ret = sbi_ecall(ext, fid, hmask_val, 0, 0, 0, 0, 0);
+ break;
+ case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA:
+ ret = sbi_ecall(ext, fid, hmask_val, 0, start,
+ size, 0, 0);
+ break;
+ case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID:
+ ret = sbi_ecall(ext, fid, hmask_val, 0, start,
+ size, arg4, 0);
+ break;
+ /*TODO: Handle non zero hbase cases */
+ case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA:
+ ret = sbi_ecall(ext, fid, hmask_val, 0, start,
+ size, 0, 0);
+ break;
+ case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID:
+ ret = sbi_ecall(ext, fid, hmask_val, 0, start,
+ size, arg4, 0);
+ break;
+ case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA:
+ ret = sbi_ecall(ext, fid, hmask_val, 0, start,
+ size, 0, 0);
+ break;
+ case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID:
+ ret = sbi_ecall(ext, fid, hmask_val, 0, start,
+ size, arg4, 0);
+ break;
+ default:
+ pr_err("unknown function ID [%d] for SBI extension [%d]\n",
+ fid, ext);
+ result = -EINVAL;
+ }
+
+ if (ret.error) {
+ result = sbi_err_map_linux_errno(ret.error);
+ pr_err("%s: failed with error [%d]\n", __func__, result);
+ } else
+ result = ret.value;
+
+ return result;
+}
+
/**
* sbi_set_timer() - Program the timer for next timer event.
* @stime_value: The value after which next timer event should fire.
@@ -269,6 +366,85 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
}
EXPORT_SYMBOL(sbi_remote_sfence_vma_asid);
+/**
+ * sbi_remote_hfence_gvma() - Execute HFENCE.GVMA instructions on given remote
+ * harts for the specified guest physical address range.
+ * @hart_mask: A cpu mask containing all the target harts.
+ * @start: Start of the guest physical address
+ * @size: Total size of the guest physical address range.
+ *
+ * Return: None
+ */
+int sbi_remote_hfence_gvma(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size)
+{
+ return __sbi_rfence(SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
+ hart_mask, 0, start, size, 0, 0);
+}
+EXPORT_SYMBOL_GPL(sbi_remote_hfence_gvma);
+
+/**
+ * sbi_remote_hfence_gvma_vmid() - Execute HFENCE.GVMA instructions on given
+ * remote harts for a guest physical address range belonging to a specific VMID.
+ *
+ * @hart_mask: A cpu mask containing all the target harts.
+ * @start: Start of the guest physical address
+ * @size: Total size of the guest physical address range.
+ * @vmid: The value of guest ID (VMID).
+ *
+ * Return: 0 if success, Error otherwise.
+ */
+int sbi_remote_hfence_gvma_vmid(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size,
+ unsigned long vmid)
+{
+ return __sbi_rfence(SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
+ hart_mask, 0, start, size, vmid, 0);
+}
+EXPORT_SYMBOL(sbi_remote_hfence_gvma_vmid);
+
+/**
+ * sbi_remote_hfence_vvma() - Execute HFENCE.VVMA instructions on given remote
+ * harts for the current guest virtual address range.
+ * @hart_mask: A cpu mask containing all the target harts.
+ * @start: Start of the current guest virtual address
+ * @size: Total size of the current guest virtual address range.
+ *
+ * Return: None
+ */
+int sbi_remote_hfence_vvma(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size)
+{
+ return __sbi_rfence(SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
+ hart_mask, 0, start, size, 0, 0);
+}
+EXPORT_SYMBOL(sbi_remote_hfence_vvma);
+
+/**
+ * sbi_remote_hfence_vvma_asid() - Execute HFENCE.VVMA instructions on given
+ * remote harts for current guest virtual address range belonging to a specific
+ * ASID.
+ *
+ * @hart_mask: A cpu mask containing all the target harts.
+ * @start: Start of the current guest virtual address
+ * @size: Total size of the current guest virtual address range.
+ * @asid: The value of address space identifier (ASID).
+ *
+ * Return: None
+ */
+int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size,
+ unsigned long asid)
+{
+ return __sbi_rfence(SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
+ hart_mask, 0, start, size, asid, 0);
+}
+EXPORT_SYMBOL(sbi_remote_hfence_vvma_asid);
+
/**
* sbi_probe_extension() - Check if an SBI extension ID is supported or not.
* @extid: The extension ID to be probed.
@@ -335,11 +511,26 @@ int __init sbi_init(void)
if (!sbi_spec_is_0_1()) {
pr_info("SBI implementation ID=0x%lx Version=0x%lx\n",
sbi_get_firmware_id(), sbi_get_firmware_version());
+ if (sbi_probe_extension(SBI_EXT_TIME) > 0) {
+ __sbi_set_timer = __sbi_set_timer_v02;
+ pr_info("SBI v0.2 TIME extension detected\n");
+ } else
+ __sbi_set_timer = __sbi_set_timer_v01;
+ if (sbi_probe_extension(SBI_EXT_IPI) > 0) {
+ __sbi_send_ipi = __sbi_send_ipi_v02;
+ pr_info("SBI v0.2 IPI extension detected\n");
+ } else
+ __sbi_send_ipi = __sbi_send_ipi_v01;
+ if (sbi_probe_extension(SBI_EXT_RFENCE) > 0) {
+ __sbi_rfence = __sbi_rfence_v02;
+ pr_info("SBI v0.2 RFENCE extension detected\n");
+ } else
+ __sbi_rfence = __sbi_rfence_v01;
+ } else {
+ __sbi_set_timer = __sbi_set_timer_v01;
+ __sbi_send_ipi = __sbi_send_ipi_v01;
+ __sbi_rfence = __sbi_rfence_v01;
}
- __sbi_set_timer = __sbi_set_timer_v01;
- __sbi_send_ipi = __sbi_send_ipi_v01;
- __sbi_rfence = __sbi_rfence_v01;
-
return 0;
}
--
2.24.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v7 06/10] RISC-V: Add cpu_ops and modify default booting method
2020-01-28 2:27 [PATCH v7 00/10] Add support for SBI v0.2 and CPU hotplug Atish Patra
` (4 preceding siblings ...)
2020-01-28 2:27 ` [PATCH v7 05/10] RISC-V: Implement new SBI v0.2 extensions Atish Patra
@ 2020-01-28 2:27 ` Atish Patra
2020-01-28 4:31 ` Anup Patel
2020-01-28 2:27 ` [PATCH v7 07/10] RISC-V: Move relocate and few other functions out of __init Atish Patra
` (3 subsequent siblings)
9 siblings, 1 reply; 22+ messages in thread
From: Atish Patra @ 2020-01-28 2:27 UTC (permalink / raw)
To: linux-kernel
Cc: Albert Ou, Thomas Gleixner, Kees Cook, abner.chang, Vincent Chen,
nickhu, Anup Patel, Paul Walmsley, Heiko Carstens, Mike Rapoport,
clin, Atish Patra, Geert Uytterhoeven, Eric W. Biederman,
Greg Kroah-Hartman, Palmer Dabbelt, Greentime Hu, linux-riscv,
Borislav Petkov, Palmer Dabbelt, Mao Han
Currently, all non-booting harts start booting after the booting hart
updates the per-hart stack pointer. This is done in a way that, it's
difficult to implement any other booting method without breaking the
backward compatibility.
Define a cpu_ops method that allows to introduce other booting methods
in future. Modify the current booting method to be compatible with
cpu_ops.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
arch/riscv/include/asm/cpu_ops.h | 31 ++++++++++++++++
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/cpu_ops.c | 61 ++++++++++++++++++++++++++++++++
arch/riscv/kernel/setup.c | 4 ++-
arch/riscv/kernel/smpboot.c | 52 ++++++++++++++++-----------
5 files changed, 127 insertions(+), 22 deletions(-)
create mode 100644 arch/riscv/include/asm/cpu_ops.h
create mode 100644 arch/riscv/kernel/cpu_ops.c
diff --git a/arch/riscv/include/asm/cpu_ops.h b/arch/riscv/include/asm/cpu_ops.h
new file mode 100644
index 000000000000..27e9dfee5460
--- /dev/null
+++ b/arch/riscv/include/asm/cpu_ops.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ * Based on arch/arm64/include/asm/cpu_ops.h
+ */
+#ifndef __ASM_CPU_OPS_H
+#define __ASM_CPU_OPS_H
+
+#include <linux/init.h>
+#include <linux/threads.h>
+
+/**
+ * struct cpu_operations - Callback operations for hotplugging CPUs.
+ *
+ * @name: Name of the boot protocol.
+ * @cpu_prepare: Early one-time preparation step for a cpu. If there
+ * is a mechanism for doing so, tests whether it is
+ * possible to boot the given HART.
+ * @cpu_start: Boots a cpu into the kernel.
+ */
+struct cpu_operations {
+ const char *name;
+ int (*cpu_prepare)(unsigned int cpu);
+ int (*cpu_start)(unsigned int cpu,
+ struct task_struct *tidle);
+};
+
+extern const struct cpu_operations *cpu_ops[NR_CPUS];
+int __init cpu_set_ops(int cpu);
+
+#endif /* ifndef __ASM_CPU_OPS_H */
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index f40205cb9a22..d77def5b4e87 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_RISCV_M_MODE) += clint.o
obj-$(CONFIG_FPU) += fpu.o
obj-$(CONFIG_SMP) += smpboot.o
obj-$(CONFIG_SMP) += smp.o
+obj-$(CONFIG_SMP) += cpu_ops.o
obj-$(CONFIG_MODULES) += module.o
obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o
diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c
new file mode 100644
index 000000000000..099dbb6ff9f0
--- /dev/null
+++ b/arch/riscv/kernel/cpu_ops.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ */
+
+#include <linux/errno.h>
+#include <linux/mm.h>
+#include <linux/of.h>
+#include <linux/string.h>
+#include <linux/sched/task_stack.h>
+#include <asm/cpu_ops.h>
+#include <asm/sbi.h>
+#include <asm/smp.h>
+
+const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init;
+
+void *__cpu_up_stack_pointer[NR_CPUS];
+void *__cpu_up_task_pointer[NR_CPUS];
+
+const struct cpu_operations cpu_spinwait_ops;
+
+static int spinwait_cpu_prepare(unsigned int cpuid)
+{
+ if (!cpu_spinwait_ops.cpu_start) {
+ pr_err("cpu start method not defined for CPU [%d]\n", cpuid);
+ return -ENODEV;
+ }
+ return 0;
+}
+
+static int spinwait_cpu_start(unsigned int cpuid, struct task_struct *tidle)
+{
+ int hartid = cpuid_to_hartid_map(cpuid);
+
+ /*
+ * In this protocol, all cpus boot on their own accord. _start
+ * selects the first cpu to boot the kernel and causes the remainder
+ * of the cpus to spin in a loop waiting for their stack pointer to be
+ * setup by that main cpu. Writing __cpu_up_stack_pointer signals to
+ * the spinning cpus that they can continue the boot process.
+ */
+ smp_mb();
+ WRITE_ONCE(__cpu_up_stack_pointer[hartid],
+ task_stack_page(tidle) + THREAD_SIZE);
+ WRITE_ONCE(__cpu_up_task_pointer[hartid], tidle);
+
+ return 0;
+}
+
+const struct cpu_operations cpu_spinwait_ops = {
+ .name = "spinwait",
+ .cpu_prepare = spinwait_cpu_prepare,
+ .cpu_start = spinwait_cpu_start,
+};
+
+int __init cpu_set_ops(int cpuid)
+{
+ cpu_ops[cpuid] = &cpu_spinwait_ops;
+ return 0;
+}
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index de3e65dae83a..8208d1109ddb 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -16,12 +16,13 @@
#include <linux/of_platform.h>
#include <linux/sched/task.h>
#include <linux/swiotlb.h>
+#include <linux/smp.h>
#include <asm/clint.h>
+#include <asm/cpu_ops.h>
#include <asm/setup.h>
#include <asm/sections.h>
#include <asm/pgtable.h>
-#include <asm/smp.h>
#include <asm/sbi.h>
#include <asm/tlbflush.h>
#include <asm/thread_info.h>
@@ -79,6 +80,7 @@ void __init setup_arch(char **cmdline_p)
sbi_init();
#ifdef CONFIG_SMP
+ cpu_set_ops(0);
setup_smp();
#endif
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 8bc01f0ca73b..f2cf541bc895 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -25,6 +25,7 @@
#include <linux/sched/task_stack.h>
#include <linux/sched/mm.h>
#include <asm/clint.h>
+#include <asm/cpu_ops.h>
#include <asm/irq.h>
#include <asm/mmu_context.h>
#include <asm/tlbflush.h>
@@ -34,8 +35,6 @@
#include "head.h"
-void *__cpu_up_stack_pointer[NR_CPUS];
-void *__cpu_up_task_pointer[NR_CPUS];
static DECLARE_COMPLETION(cpu_running);
void __init smp_prepare_boot_cpu(void)
@@ -46,6 +45,7 @@ void __init smp_prepare_boot_cpu(void)
void __init smp_prepare_cpus(unsigned int max_cpus)
{
int cpuid;
+ int ret;
/* This covers non-smp usecase mandated by "nosmp" option */
if (max_cpus == 0)
@@ -54,6 +54,11 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
for_each_possible_cpu(cpuid) {
if (cpuid == smp_processor_id())
continue;
+ if (cpu_ops[cpuid]->cpu_prepare) {
+ ret = cpu_ops[cpuid]->cpu_prepare(cpuid);
+ if (ret)
+ continue;
+ }
set_cpu_present(cpuid, true);
}
}
@@ -92,36 +97,41 @@ void __init setup_smp(void)
cpuid, nr_cpu_ids);
for (cpuid = 1; cpuid < nr_cpu_ids; cpuid++) {
- if (cpuid_to_hartid_map(cpuid) != INVALID_HARTID)
+ if (cpuid_to_hartid_map(cpuid) != INVALID_HARTID) {
+ if (cpu_set_ops(cpuid)) {
+ cpuid_to_hartid_map(cpuid) = INVALID_HARTID;
+ continue;
+ }
set_cpu_possible(cpuid, true);
+ }
}
}
+int start_secondary_cpu(int cpu, struct task_struct *tidle)
+{
+ if (cpu_ops[cpu]->cpu_start)
+ return cpu_ops[cpu]->cpu_start(cpu, tidle);
+
+ return -EOPNOTSUPP;
+}
+
int __cpu_up(unsigned int cpu, struct task_struct *tidle)
{
int ret = 0;
- int hartid = cpuid_to_hartid_map(cpu);
tidle->thread_info.cpu = cpu;
- /*
- * On RISC-V systems, all harts boot on their own accord. Our _start
- * selects the first hart to boot the kernel and causes the remainder
- * of the harts to spin in a loop waiting for their stack pointer to be
- * setup by that main hart. Writing __cpu_up_stack_pointer signals to
- * the spinning harts that they can continue the boot process.
- */
- smp_mb();
- WRITE_ONCE(__cpu_up_stack_pointer[hartid],
- task_stack_page(tidle) + THREAD_SIZE);
- WRITE_ONCE(__cpu_up_task_pointer[hartid], tidle);
-
- lockdep_assert_held(&cpu_running);
- wait_for_completion_timeout(&cpu_running,
+ ret = start_secondary_cpu(cpu, tidle);
+ if (!ret) {
+ lockdep_assert_held(&cpu_running);
+ wait_for_completion_timeout(&cpu_running,
msecs_to_jiffies(1000));
- if (!cpu_online(cpu)) {
- pr_crit("CPU%u: failed to come online\n", cpu);
- ret = -EIO;
+ if (!cpu_online(cpu)) {
+ pr_crit("CPU%u: failed to come online\n", cpu);
+ ret = -EIO;
+ }
+ } else {
+ pr_crit("CPU%u: failed to start\n", cpu);
}
return ret;
--
2.24.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v7 06/10] RISC-V: Add cpu_ops and modify default booting method
2020-01-28 2:27 ` [PATCH v7 06/10] RISC-V: Add cpu_ops and modify default booting method Atish Patra
@ 2020-01-28 4:31 ` Anup Patel
0 siblings, 0 replies; 22+ messages in thread
From: Anup Patel @ 2020-01-28 4:31 UTC (permalink / raw)
To: Atish Patra
Cc: Albert Ou, Thomas Gleixner, Kees Cook, Abner Chang, nickhu,
Greg Kroah-Hartman, Palmer Dabbelt, Heiko Carstens,
linux-kernel@vger.kernel.org List, Mike Rapoport, Chester Lin,
Vincent Chen, Geert Uytterhoeven, Eric W. Biederman,
Paul Walmsley, Greentime Hu, linux-riscv, Borislav Petkov,
Palmer Dabbelt, Mao Han
On Tue, Jan 28, 2020 at 7:58 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> Currently, all non-booting harts start booting after the booting hart
> updates the per-hart stack pointer. This is done in a way that, it's
> difficult to implement any other booting method without breaking the
> backward compatibility.
>
> Define a cpu_ops method that allows to introduce other booting methods
> in future. Modify the current booting method to be compatible with
> cpu_ops.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> arch/riscv/include/asm/cpu_ops.h | 31 ++++++++++++++++
> arch/riscv/kernel/Makefile | 1 +
> arch/riscv/kernel/cpu_ops.c | 61 ++++++++++++++++++++++++++++++++
> arch/riscv/kernel/setup.c | 4 ++-
> arch/riscv/kernel/smpboot.c | 52 ++++++++++++++++-----------
> 5 files changed, 127 insertions(+), 22 deletions(-)
> create mode 100644 arch/riscv/include/asm/cpu_ops.h
> create mode 100644 arch/riscv/kernel/cpu_ops.c
This has to be more modular considering the fact that CONFIG_RISCV_SBI
can be disabled.
I have few suggestions on how to break cpu_ops.c
>
> diff --git a/arch/riscv/include/asm/cpu_ops.h b/arch/riscv/include/asm/cpu_ops.h
> new file mode 100644
> index 000000000000..27e9dfee5460
> --- /dev/null
> +++ b/arch/riscv/include/asm/cpu_ops.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2019 Western Digital Corporation or its affiliates.
> + * Based on arch/arm64/include/asm/cpu_ops.h
> + */
> +#ifndef __ASM_CPU_OPS_H
> +#define __ASM_CPU_OPS_H
> +
> +#include <linux/init.h>
> +#include <linux/threads.h>
> +
> +/**
> + * struct cpu_operations - Callback operations for hotplugging CPUs.
> + *
> + * @name: Name of the boot protocol.
> + * @cpu_prepare: Early one-time preparation step for a cpu. If there
> + * is a mechanism for doing so, tests whether it is
> + * possible to boot the given HART.
> + * @cpu_start: Boots a cpu into the kernel.
> + */
> +struct cpu_operations {
> + const char *name;
> + int (*cpu_prepare)(unsigned int cpu);
> + int (*cpu_start)(unsigned int cpu,
> + struct task_struct *tidle);
> +};
> +
> +extern const struct cpu_operations *cpu_ops[NR_CPUS];
Add following here:
extern void *__cpu_up_stack_pointer[NR_CPUS];
extern void *__cpu_up_task_pointer[NR_CPUS];
> +int __init cpu_set_ops(int cpu);
> +
> +#endif /* ifndef __ASM_CPU_OPS_H */
> diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
> index f40205cb9a22..d77def5b4e87 100644
> --- a/arch/riscv/kernel/Makefile
> +++ b/arch/riscv/kernel/Makefile
> @@ -32,6 +32,7 @@ obj-$(CONFIG_RISCV_M_MODE) += clint.o
> obj-$(CONFIG_FPU) += fpu.o
> obj-$(CONFIG_SMP) += smpboot.o
> obj-$(CONFIG_SMP) += smp.o
> +obj-$(CONFIG_SMP) += cpu_ops.o
> obj-$(CONFIG_MODULES) += module.o
> obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o
>
> diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c
> new file mode 100644
> index 000000000000..099dbb6ff9f0
> --- /dev/null
> +++ b/arch/riscv/kernel/cpu_ops.c
> @@ -0,0 +1,61 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2019 Western Digital Corporation or its affiliates.
> + *
> + */
> +
> +#include <linux/errno.h>
> +#include <linux/mm.h>
> +#include <linux/of.h>
> +#include <linux/string.h>
> +#include <linux/sched/task_stack.h>
> +#include <asm/cpu_ops.h>
> +#include <asm/sbi.h>
> +#include <asm/smp.h>
> +
> +const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init;
> +
> +void *__cpu_up_stack_pointer[NR_CPUS];
> +void *__cpu_up_task_pointer[NR_CPUS];
> +
> +const struct cpu_operations cpu_spinwait_ops;
> +
> +static int spinwait_cpu_prepare(unsigned int cpuid)
> +{
> + if (!cpu_spinwait_ops.cpu_start) {
> + pr_err("cpu start method not defined for CPU [%d]\n", cpuid);
> + return -ENODEV;
> + }
> + return 0;
> +}
> +
> +static int spinwait_cpu_start(unsigned int cpuid, struct task_struct *tidle)
> +{
> + int hartid = cpuid_to_hartid_map(cpuid);
> +
> + /*
> + * In this protocol, all cpus boot on their own accord. _start
> + * selects the first cpu to boot the kernel and causes the remainder
> + * of the cpus to spin in a loop waiting for their stack pointer to be
> + * setup by that main cpu. Writing __cpu_up_stack_pointer signals to
> + * the spinning cpus that they can continue the boot process.
> + */
> + smp_mb();
> + WRITE_ONCE(__cpu_up_stack_pointer[hartid],
> + task_stack_page(tidle) + THREAD_SIZE);
> + WRITE_ONCE(__cpu_up_task_pointer[hartid], tidle);
> +
> + return 0;
> +}
> +
> +const struct cpu_operations cpu_spinwait_ops = {
> + .name = "spinwait",
> + .cpu_prepare = spinwait_cpu_prepare,
> + .cpu_start = spinwait_cpu_start,
> +};
Move cpu_spinwait_ops, spinwait_cpu_start, and spinwait_cpu_prepare
to arch/riscv/kernel/cpu_ops_spinwait.c
Have "extern const struct cpu_operations cpu_spinwait_ops;" here.
> +
> +int __init cpu_set_ops(int cpuid)
> +{
> + cpu_ops[cpuid] = &cpu_spinwait_ops;
> + return 0;
> +}
> diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> index de3e65dae83a..8208d1109ddb 100644
> --- a/arch/riscv/kernel/setup.c
> +++ b/arch/riscv/kernel/setup.c
> @@ -16,12 +16,13 @@
> #include <linux/of_platform.h>
> #include <linux/sched/task.h>
> #include <linux/swiotlb.h>
> +#include <linux/smp.h>
>
> #include <asm/clint.h>
> +#include <asm/cpu_ops.h>
> #include <asm/setup.h>
> #include <asm/sections.h>
> #include <asm/pgtable.h>
> -#include <asm/smp.h>
> #include <asm/sbi.h>
> #include <asm/tlbflush.h>
> #include <asm/thread_info.h>
> @@ -79,6 +80,7 @@ void __init setup_arch(char **cmdline_p)
> sbi_init();
>
> #ifdef CONFIG_SMP
> + cpu_set_ops(0);
> setup_smp();
> #endif
>
> diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
> index 8bc01f0ca73b..f2cf541bc895 100644
> --- a/arch/riscv/kernel/smpboot.c
> +++ b/arch/riscv/kernel/smpboot.c
> @@ -25,6 +25,7 @@
> #include <linux/sched/task_stack.h>
> #include <linux/sched/mm.h>
> #include <asm/clint.h>
> +#include <asm/cpu_ops.h>
> #include <asm/irq.h>
> #include <asm/mmu_context.h>
> #include <asm/tlbflush.h>
> @@ -34,8 +35,6 @@
>
> #include "head.h"
>
> -void *__cpu_up_stack_pointer[NR_CPUS];
> -void *__cpu_up_task_pointer[NR_CPUS];
> static DECLARE_COMPLETION(cpu_running);
>
> void __init smp_prepare_boot_cpu(void)
> @@ -46,6 +45,7 @@ void __init smp_prepare_boot_cpu(void)
> void __init smp_prepare_cpus(unsigned int max_cpus)
> {
> int cpuid;
> + int ret;
>
> /* This covers non-smp usecase mandated by "nosmp" option */
> if (max_cpus == 0)
> @@ -54,6 +54,11 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
> for_each_possible_cpu(cpuid) {
> if (cpuid == smp_processor_id())
> continue;
> + if (cpu_ops[cpuid]->cpu_prepare) {
> + ret = cpu_ops[cpuid]->cpu_prepare(cpuid);
> + if (ret)
> + continue;
> + }
> set_cpu_present(cpuid, true);
> }
> }
> @@ -92,36 +97,41 @@ void __init setup_smp(void)
> cpuid, nr_cpu_ids);
>
> for (cpuid = 1; cpuid < nr_cpu_ids; cpuid++) {
> - if (cpuid_to_hartid_map(cpuid) != INVALID_HARTID)
> + if (cpuid_to_hartid_map(cpuid) != INVALID_HARTID) {
> + if (cpu_set_ops(cpuid)) {
> + cpuid_to_hartid_map(cpuid) = INVALID_HARTID;
> + continue;
> + }
> set_cpu_possible(cpuid, true);
> + }
> }
> }
>
> +int start_secondary_cpu(int cpu, struct task_struct *tidle)
> +{
> + if (cpu_ops[cpu]->cpu_start)
> + return cpu_ops[cpu]->cpu_start(cpu, tidle);
> +
> + return -EOPNOTSUPP;
> +}
> +
> int __cpu_up(unsigned int cpu, struct task_struct *tidle)
> {
> int ret = 0;
> - int hartid = cpuid_to_hartid_map(cpu);
> tidle->thread_info.cpu = cpu;
>
> - /*
> - * On RISC-V systems, all harts boot on their own accord. Our _start
> - * selects the first hart to boot the kernel and causes the remainder
> - * of the harts to spin in a loop waiting for their stack pointer to be
> - * setup by that main hart. Writing __cpu_up_stack_pointer signals to
> - * the spinning harts that they can continue the boot process.
> - */
> - smp_mb();
> - WRITE_ONCE(__cpu_up_stack_pointer[hartid],
> - task_stack_page(tidle) + THREAD_SIZE);
> - WRITE_ONCE(__cpu_up_task_pointer[hartid], tidle);
> -
> - lockdep_assert_held(&cpu_running);
> - wait_for_completion_timeout(&cpu_running,
> + ret = start_secondary_cpu(cpu, tidle);
> + if (!ret) {
> + lockdep_assert_held(&cpu_running);
> + wait_for_completion_timeout(&cpu_running,
> msecs_to_jiffies(1000));
>
> - if (!cpu_online(cpu)) {
> - pr_crit("CPU%u: failed to come online\n", cpu);
> - ret = -EIO;
> + if (!cpu_online(cpu)) {
> + pr_crit("CPU%u: failed to come online\n", cpu);
> + ret = -EIO;
> + }
> + } else {
> + pr_crit("CPU%u: failed to start\n", cpu);
> }
>
> return ret;
> --
> 2.24.0
>
Regards,
Anup
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v7 07/10] RISC-V: Move relocate and few other functions out of __init
2020-01-28 2:27 [PATCH v7 00/10] Add support for SBI v0.2 and CPU hotplug Atish Patra
` (5 preceding siblings ...)
2020-01-28 2:27 ` [PATCH v7 06/10] RISC-V: Add cpu_ops and modify default booting method Atish Patra
@ 2020-01-28 2:27 ` Atish Patra
2020-01-28 4:38 ` Anup Patel
2020-01-28 2:27 ` [PATCH v7 08/10] RISC-V: Add SBI HSM extension Atish Patra
` (2 subsequent siblings)
9 siblings, 1 reply; 22+ messages in thread
From: Atish Patra @ 2020-01-28 2:27 UTC (permalink / raw)
To: linux-kernel
Cc: Albert Ou, Thomas Gleixner, Kees Cook, abner.chang, Vincent Chen,
nickhu, Anup Patel, Paul Walmsley, Heiko Carstens, Mike Rapoport,
clin, Atish Patra, Geert Uytterhoeven, Eric W. Biederman,
Greg Kroah-Hartman, Palmer Dabbelt, Greentime Hu, linux-riscv,
Borislav Petkov, Palmer Dabbelt, Mao Han
The secondary hart booting and relocation code are under .init section.
As a result, it will be freed once kernel booting is done. However,
ordered booting protocol and CPU hotplug always requires these sections
to be present to bringup harts after initial kernel boot.
Move the required sections to a different section and make sure that
they are in memory within first 2MB offset as trampoline page directory
only maps first 2MB.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
arch/riscv/kernel/head.S | 73 +++++++++++++++++++--------------
arch/riscv/kernel/vmlinux.lds.S | 9 +++-
2 files changed, 50 insertions(+), 32 deletions(-)
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index a4242be66966..9d7f084a50cc 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -14,7 +14,7 @@
#include <asm/hwcap.h>
#include <asm/image.h>
-__INIT
+__HEAD
ENTRY(_start)
/*
* Image header expected by Linux boot-loaders. The image header data
@@ -44,9 +44,10 @@ ENTRY(_start)
.balign 4
.ascii RISCV_IMAGE_MAGIC2
.word 0
+END(_start)
-.global _start_kernel
-_start_kernel:
+ __INIT
+ENTRY(_start_kernel)
/* Mask all interrupts */
csrw CSR_IE, zero
csrw CSR_IP, zero
@@ -125,6 +126,37 @@ clear_bss_done:
call parse_dtb
tail start_kernel
+.Lsecondary_start:
+#ifdef CONFIG_SMP
+ /* Set trap vector to spin forever to help debug */
+ la a3, .Lsecondary_park
+ csrw CSR_TVEC, a3
+
+ slli a3, a0, LGREG
+ la a1, __cpu_up_stack_pointer
+ la a2, __cpu_up_task_pointer
+ add a1, a3, a1
+ add a2, a3, a2
+
+ /*
+ * This hart didn't win the lottery, so we wait for the winning hart to
+ * get far enough along the boot process that it should continue.
+ */
+.Lwait_for_cpu_up:
+ /* FIXME: We should WFI to save some energy here. */
+ REG_L sp, (a1)
+ REG_L tp, (a2)
+ beqz sp, .Lwait_for_cpu_up
+ beqz tp, .Lwait_for_cpu_up
+ fence
+
+ tail secondary_start_common
+#endif
+
+END(_start_kernel)
+
+.section ".noinit.text","ax",@progbits
+.align 2
#ifdef CONFIG_MMU
relocate:
/* Relocate return address */
@@ -177,41 +209,27 @@ relocate:
ret
#endif /* CONFIG_MMU */
-
-.Lsecondary_start:
#ifdef CONFIG_SMP
/* Set trap vector to spin forever to help debug */
la a3, .Lsecondary_park
csrw CSR_TVEC, a3
slli a3, a0, LGREG
- la a1, __cpu_up_stack_pointer
- la a2, __cpu_up_task_pointer
- add a1, a3, a1
- add a2, a3, a2
-
- /*
- * This hart didn't win the lottery, so we wait for the winning hart to
- * get far enough along the boot process that it should continue.
- */
-.Lwait_for_cpu_up:
- /* FIXME: We should WFI to save some energy here. */
- REG_L sp, (a1)
- REG_L tp, (a2)
- beqz sp, .Lwait_for_cpu_up
- beqz tp, .Lwait_for_cpu_up
- fence
+ .global secondary_start_common
+secondary_start_common:
#ifdef CONFIG_MMU
/* Enable virtual memory and relocate to virtual address */
la a0, swapper_pg_dir
call relocate
#endif
-
tail smp_callin
-#endif
+#endif /* CONFIG_SMP */
-END(_start)
+.Lsecondary_park:
+ /* We lack SMP support or have too many harts, so park this hart */
+ wfi
+ j .Lsecondary_park
#ifdef CONFIG_RISCV_M_MODE
ENTRY(reset_regs)
@@ -292,13 +310,6 @@ ENTRY(reset_regs)
END(reset_regs)
#endif /* CONFIG_RISCV_M_MODE */
-.section ".text", "ax",@progbits
-.align 2
-.Lsecondary_park:
- /* We lack SMP support or have too many harts, so park this hart */
- wfi
- j .Lsecondary_park
-
__PAGE_ALIGNED_BSS
/* Empty zero page */
.balign PAGE_SIZE
diff --git a/arch/riscv/kernel/vmlinux.lds.S b/arch/riscv/kernel/vmlinux.lds.S
index 12f42f96d46e..c8a88326df9e 100644
--- a/arch/riscv/kernel/vmlinux.lds.S
+++ b/arch/riscv/kernel/vmlinux.lds.S
@@ -10,6 +10,7 @@
#include <asm/cache.h>
#include <asm/thread_info.h>
+#include <linux/sizes.h>
OUTPUT_ARCH(riscv)
ENTRY(_start)
@@ -20,8 +21,14 @@ SECTIONS
/* Beginning of code and text segment */
. = LOAD_OFFSET;
_start = .;
- __init_begin = .;
HEAD_TEXT_SECTION
+ .noinit.text :
+ {
+ *(.noinit.text)
+ }
+ . = ALIGN(SZ_4K);
+
+ __init_begin = .;
INIT_TEXT_SECTION(PAGE_SIZE)
INIT_DATA_SECTION(16)
/* we have to discard exit text and such at runtime, not link time */
--
2.24.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v7 07/10] RISC-V: Move relocate and few other functions out of __init
2020-01-28 2:27 ` [PATCH v7 07/10] RISC-V: Move relocate and few other functions out of __init Atish Patra
@ 2020-01-28 4:38 ` Anup Patel
2020-01-28 19:28 ` Atish Patra
0 siblings, 1 reply; 22+ messages in thread
From: Anup Patel @ 2020-01-28 4:38 UTC (permalink / raw)
To: Atish Patra
Cc: Albert Ou, Thomas Gleixner, Kees Cook, Abner Chang, nickhu,
Greg Kroah-Hartman, Palmer Dabbelt, Heiko Carstens,
linux-kernel@vger.kernel.org List, Mike Rapoport, Chester Lin,
Vincent Chen, Geert Uytterhoeven, Eric W. Biederman,
Paul Walmsley, Greentime Hu, linux-riscv, Borislav Petkov,
Palmer Dabbelt, Mao Han
On Tue, Jan 28, 2020 at 7:58 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> The secondary hart booting and relocation code are under .init section.
> As a result, it will be freed once kernel booting is done. However,
> ordered booting protocol and CPU hotplug always requires these sections
> to be present to bringup harts after initial kernel boot.
>
> Move the required sections to a different section and make sure that
> they are in memory within first 2MB offset as trampoline page directory
> only maps first 2MB.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> arch/riscv/kernel/head.S | 73 +++++++++++++++++++--------------
> arch/riscv/kernel/vmlinux.lds.S | 9 +++-
> 2 files changed, 50 insertions(+), 32 deletions(-)
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index a4242be66966..9d7f084a50cc 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -14,7 +14,7 @@
> #include <asm/hwcap.h>
> #include <asm/image.h>
>
> -__INIT
> +__HEAD
> ENTRY(_start)
> /*
> * Image header expected by Linux boot-loaders. The image header data
> @@ -44,9 +44,10 @@ ENTRY(_start)
> .balign 4
> .ascii RISCV_IMAGE_MAGIC2
> .word 0
> +END(_start)
>
> -.global _start_kernel
> -_start_kernel:
> + __INIT
> +ENTRY(_start_kernel)
> /* Mask all interrupts */
> csrw CSR_IE, zero
> csrw CSR_IP, zero
> @@ -125,6 +126,37 @@ clear_bss_done:
> call parse_dtb
> tail start_kernel
>
> +.Lsecondary_start:
> +#ifdef CONFIG_SMP
> + /* Set trap vector to spin forever to help debug */
> + la a3, .Lsecondary_park
> + csrw CSR_TVEC, a3
> +
> + slli a3, a0, LGREG
> + la a1, __cpu_up_stack_pointer
> + la a2, __cpu_up_task_pointer
> + add a1, a3, a1
> + add a2, a3, a2
> +
> + /*
> + * This hart didn't win the lottery, so we wait for the winning hart to
> + * get far enough along the boot process that it should continue.
> + */
> +.Lwait_for_cpu_up:
> + /* FIXME: We should WFI to save some energy here. */
> + REG_L sp, (a1)
> + REG_L tp, (a2)
> + beqz sp, .Lwait_for_cpu_up
> + beqz tp, .Lwait_for_cpu_up
> + fence
> +
> + tail secondary_start_common
> +#endif
> +
> +END(_start_kernel)
> +
> +.section ".noinit.text","ax",@progbits
> +.align 2
Try to use __HEAD here (if possible).
> #ifdef CONFIG_MMU
> relocate:
> /* Relocate return address */
> @@ -177,41 +209,27 @@ relocate:
>
> ret
> #endif /* CONFIG_MMU */
> -
> -.Lsecondary_start:
> #ifdef CONFIG_SMP
> /* Set trap vector to spin forever to help debug */
> la a3, .Lsecondary_park
> csrw CSR_TVEC, a3
>
> slli a3, a0, LGREG
> - la a1, __cpu_up_stack_pointer
> - la a2, __cpu_up_task_pointer
> - add a1, a3, a1
> - add a2, a3, a2
> -
> - /*
> - * This hart didn't win the lottery, so we wait for the winning hart to
> - * get far enough along the boot process that it should continue.
> - */
> -.Lwait_for_cpu_up:
> - /* FIXME: We should WFI to save some energy here. */
> - REG_L sp, (a1)
> - REG_L tp, (a2)
> - beqz sp, .Lwait_for_cpu_up
> - beqz tp, .Lwait_for_cpu_up
> - fence
> + .global secondary_start_common
> +secondary_start_common:
>
> #ifdef CONFIG_MMU
> /* Enable virtual memory and relocate to virtual address */
> la a0, swapper_pg_dir
> call relocate
> #endif
> -
> tail smp_callin
> -#endif
> +#endif /* CONFIG_SMP */
>
> -END(_start)
> +.Lsecondary_park:
> + /* We lack SMP support or have too many harts, so park this hart */
> + wfi
> + j .Lsecondary_park
>
> #ifdef CONFIG_RISCV_M_MODE
> ENTRY(reset_regs)
> @@ -292,13 +310,6 @@ ENTRY(reset_regs)
> END(reset_regs)
> #endif /* CONFIG_RISCV_M_MODE */
>
> -.section ".text", "ax",@progbits
> -.align 2
> -.Lsecondary_park:
> - /* We lack SMP support or have too many harts, so park this hart */
> - wfi
> - j .Lsecondary_park
> -
> __PAGE_ALIGNED_BSS
> /* Empty zero page */
> .balign PAGE_SIZE
> diff --git a/arch/riscv/kernel/vmlinux.lds.S b/arch/riscv/kernel/vmlinux.lds.S
> index 12f42f96d46e..c8a88326df9e 100644
> --- a/arch/riscv/kernel/vmlinux.lds.S
> +++ b/arch/riscv/kernel/vmlinux.lds.S
> @@ -10,6 +10,7 @@
> #include <asm/cache.h>
> #include <asm/thread_info.h>
>
> +#include <linux/sizes.h>
> OUTPUT_ARCH(riscv)
> ENTRY(_start)
>
> @@ -20,8 +21,14 @@ SECTIONS
> /* Beginning of code and text segment */
> . = LOAD_OFFSET;
> _start = .;
> - __init_begin = .;
> HEAD_TEXT_SECTION
> + .noinit.text :
> + {
> + *(.noinit.text)
> + }
Can we try using HEAD_TEXT_SECTION for SMP booting
related functions instead of new ".noinit.text" section ??
> + . = ALIGN(SZ_4K);
Change this to PAGE aligned:
. = ALIGN(PAGE_SIZE)
> +
> + __init_begin = .;
> INIT_TEXT_SECTION(PAGE_SIZE)
> INIT_DATA_SECTION(16)
> /* we have to discard exit text and such at runtime, not link time */
> --
> 2.24.0
>
Regards,
Anup
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v7 07/10] RISC-V: Move relocate and few other functions out of __init
2020-01-28 4:38 ` Anup Patel
@ 2020-01-28 19:28 ` Atish Patra
0 siblings, 0 replies; 22+ messages in thread
From: Atish Patra @ 2020-01-28 19:28 UTC (permalink / raw)
To: Anup Patel
Cc: Albert Ou, Kees Cook, nickhu, Vincent Chen, Greg Kroah-Hartman,
Palmer Dabbelt, Heiko Carstens,
linux-kernel@vger.kernel.org List, Mike Rapoport, Chester Lin,
Atish Patra, Palmer Dabbelt, Geert Uytterhoeven,
Eric W. Biederman, Paul Walmsley, Greentime Hu, Thomas Gleixner,
Borislav Petkov, Abner Chang, linux-riscv, Mao Han
On Mon, Jan 27, 2020 at 8:38 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Tue, Jan 28, 2020 at 7:58 AM Atish Patra <atish.patra@wdc.com> wrote:
> >
> > The secondary hart booting and relocation code are under .init section.
> > As a result, it will be freed once kernel booting is done. However,
> > ordered booting protocol and CPU hotplug always requires these sections
> > to be present to bringup harts after initial kernel boot.
> >
> > Move the required sections to a different section and make sure that
> > they are in memory within first 2MB offset as trampoline page directory
> > only maps first 2MB.
> >
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > ---
> > arch/riscv/kernel/head.S | 73 +++++++++++++++++++--------------
> > arch/riscv/kernel/vmlinux.lds.S | 9 +++-
> > 2 files changed, 50 insertions(+), 32 deletions(-)
> >
> > diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> > index a4242be66966..9d7f084a50cc 100644
> > --- a/arch/riscv/kernel/head.S
> > +++ b/arch/riscv/kernel/head.S
> > @@ -14,7 +14,7 @@
> > #include <asm/hwcap.h>
> > #include <asm/image.h>
> >
> > -__INIT
> > +__HEAD
> > ENTRY(_start)
> > /*
> > * Image header expected by Linux boot-loaders. The image header data
> > @@ -44,9 +44,10 @@ ENTRY(_start)
> > .balign 4
> > .ascii RISCV_IMAGE_MAGIC2
> > .word 0
> > +END(_start)
> >
> > -.global _start_kernel
> > -_start_kernel:
> > + __INIT
> > +ENTRY(_start_kernel)
> > /* Mask all interrupts */
> > csrw CSR_IE, zero
> > csrw CSR_IP, zero
> > @@ -125,6 +126,37 @@ clear_bss_done:
> > call parse_dtb
> > tail start_kernel
> >
> > +.Lsecondary_start:
> > +#ifdef CONFIG_SMP
> > + /* Set trap vector to spin forever to help debug */
> > + la a3, .Lsecondary_park
> > + csrw CSR_TVEC, a3
> > +
> > + slli a3, a0, LGREG
> > + la a1, __cpu_up_stack_pointer
> > + la a2, __cpu_up_task_pointer
> > + add a1, a3, a1
> > + add a2, a3, a2
> > +
> > + /*
> > + * This hart didn't win the lottery, so we wait for the winning hart to
> > + * get far enough along the boot process that it should continue.
> > + */
> > +.Lwait_for_cpu_up:
> > + /* FIXME: We should WFI to save some energy here. */
> > + REG_L sp, (a1)
> > + REG_L tp, (a2)
> > + beqz sp, .Lwait_for_cpu_up
> > + beqz tp, .Lwait_for_cpu_up
> > + fence
> > +
> > + tail secondary_start_common
> > +#endif
> > +
> > +END(_start_kernel)
> > +
> > +.section ".noinit.text","ax",@progbits
> > +.align 2
>
> Try to use __HEAD here (if possible).
>
> > #ifdef CONFIG_MMU
> > relocate:
> > /* Relocate return address */
> > @@ -177,41 +209,27 @@ relocate:
> >
> > ret
> > #endif /* CONFIG_MMU */
> > -
> > -.Lsecondary_start:
> > #ifdef CONFIG_SMP
> > /* Set trap vector to spin forever to help debug */
> > la a3, .Lsecondary_park
> > csrw CSR_TVEC, a3
> >
> > slli a3, a0, LGREG
> > - la a1, __cpu_up_stack_pointer
> > - la a2, __cpu_up_task_pointer
> > - add a1, a3, a1
> > - add a2, a3, a2
> > -
> > - /*
> > - * This hart didn't win the lottery, so we wait for the winning hart to
> > - * get far enough along the boot process that it should continue.
> > - */
> > -.Lwait_for_cpu_up:
> > - /* FIXME: We should WFI to save some energy here. */
> > - REG_L sp, (a1)
> > - REG_L tp, (a2)
> > - beqz sp, .Lwait_for_cpu_up
> > - beqz tp, .Lwait_for_cpu_up
> > - fence
> > + .global secondary_start_common
> > +secondary_start_common:
> >
> > #ifdef CONFIG_MMU
> > /* Enable virtual memory and relocate to virtual address */
> > la a0, swapper_pg_dir
> > call relocate
> > #endif
> > -
> > tail smp_callin
> > -#endif
> > +#endif /* CONFIG_SMP */
> >
> > -END(_start)
> > +.Lsecondary_park:
> > + /* We lack SMP support or have too many harts, so park this hart */
> > + wfi
> > + j .Lsecondary_park
> >
> > #ifdef CONFIG_RISCV_M_MODE
> > ENTRY(reset_regs)
> > @@ -292,13 +310,6 @@ ENTRY(reset_regs)
> > END(reset_regs)
> > #endif /* CONFIG_RISCV_M_MODE */
> >
> > -.section ".text", "ax",@progbits
> > -.align 2
> > -.Lsecondary_park:
> > - /* We lack SMP support or have too many harts, so park this hart */
> > - wfi
> > - j .Lsecondary_park
> > -
> > __PAGE_ALIGNED_BSS
> > /* Empty zero page */
> > .balign PAGE_SIZE
> > diff --git a/arch/riscv/kernel/vmlinux.lds.S b/arch/riscv/kernel/vmlinux.lds.S
> > index 12f42f96d46e..c8a88326df9e 100644
> > --- a/arch/riscv/kernel/vmlinux.lds.S
> > +++ b/arch/riscv/kernel/vmlinux.lds.S
> > @@ -10,6 +10,7 @@
> > #include <asm/cache.h>
> > #include <asm/thread_info.h>
> >
> > +#include <linux/sizes.h>
> > OUTPUT_ARCH(riscv)
> > ENTRY(_start)
> >
> > @@ -20,8 +21,14 @@ SECTIONS
> > /* Beginning of code and text segment */
> > . = LOAD_OFFSET;
> > _start = .;
> > - __init_begin = .;
> > HEAD_TEXT_SECTION
> > + .noinit.text :
> > + {
> > + *(.noinit.text)
> > + }
>
> Can we try using HEAD_TEXT_SECTION for SMP booting
> related functions instead of new ".noinit.text" section ??
>
Yeah. That is much cleaner as well. I will update it in v2.
> > + . = ALIGN(SZ_4K);
>
> Change this to PAGE aligned:
> . = ALIGN(PAGE_SIZE)
>
Sure. Will do that.
> > +
> > + __init_begin = .;
> > INIT_TEXT_SECTION(PAGE_SIZE)
> > INIT_DATA_SECTION(16)
> > /* we have to discard exit text and such at runtime, not link time */
> > --
> > 2.24.0
> >
>
> Regards,
> Anup
>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v7 08/10] RISC-V: Add SBI HSM extension
2020-01-28 2:27 [PATCH v7 00/10] Add support for SBI v0.2 and CPU hotplug Atish Patra
` (6 preceding siblings ...)
2020-01-28 2:27 ` [PATCH v7 07/10] RISC-V: Move relocate and few other functions out of __init Atish Patra
@ 2020-01-28 2:27 ` Atish Patra
2020-01-28 4:54 ` Anup Patel
2020-01-28 2:27 ` [PATCH v7 09/10] RISC-V: Add supported for ordered booting method using HSM Atish Patra
2020-01-28 2:27 ` [PATCH v7 10/10] RISC-V: Support cpu hotplug Atish Patra
9 siblings, 1 reply; 22+ messages in thread
From: Atish Patra @ 2020-01-28 2:27 UTC (permalink / raw)
To: linux-kernel
Cc: Albert Ou, Thomas Gleixner, Kees Cook, abner.chang, Vincent Chen,
nickhu, Anup Patel, Paul Walmsley, Heiko Carstens, Mike Rapoport,
clin, Atish Patra, Geert Uytterhoeven, Eric W. Biederman,
Greg Kroah-Hartman, Palmer Dabbelt, Greentime Hu, linux-riscv,
Borislav Petkov, Palmer Dabbelt, Mao Han
SBI specification defines HSM extension that allows to start/stop a hart
by a supervisor anytime. The specification is available at
https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
Implement SBI HSM extension.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
arch/riscv/include/asm/sbi.h | 22 ++++++++++++++++
arch/riscv/kernel/sbi.c | 51 ++++++++++++++++++++++++++++++++++++
2 files changed, 73 insertions(+)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index d55d8090ab5c..bed6fa26ec84 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -26,6 +26,7 @@ enum sbi_ext_id {
SBI_EXT_TIME = 0x54494D45,
SBI_EXT_IPI = 0x735049,
SBI_EXT_RFENCE = 0x52464E43,
+ SBI_EXT_HSM = 0x48534D,
};
enum sbi_ext_base_fid {
@@ -56,6 +57,12 @@ enum sbi_ext_rfence_fid {
SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
};
+enum sbi_ext_hsm_fid {
+ SBI_EXT_HSM_HART_START = 0,
+ SBI_EXT_HSM_HART_STOP,
+ SBI_EXT_HSM_HART_STATUS,
+};
+
#define SBI_SPEC_VERSION_DEFAULT 0x1
#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
@@ -70,6 +77,7 @@ enum sbi_ext_rfence_fid {
#define SBI_ERR_INVALID_ADDRESS -5
extern unsigned long sbi_spec_version;
+extern bool sbi_hsm_avail;
struct sbiret {
long error;
long value;
@@ -110,8 +118,18 @@ int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
unsigned long start,
unsigned long size,
unsigned long asid);
+int sbi_hsm_hart_start(unsigned long hartid, unsigned long saddr,
+ unsigned long priv);
+int sbi_hsm_hart_stop(void);
+int sbi_hsm_hart_get_status(unsigned long hartid);
+
int sbi_probe_extension(int ext);
+static inline bool sbi_hsm_is_available(void)
+{
+ return sbi_hsm_avail;
+}
+
/* Check if current SBI specification version is 0.1 or not */
static inline int sbi_spec_is_0_1(void)
{
@@ -137,5 +155,9 @@ void sbi_clear_ipi(void);
void sbi_send_ipi(const unsigned long *hart_mask);
void sbi_remote_fence_i(const unsigned long *hart_mask);
void sbi_init(void);
+static inline bool sbi_hsm_is_available(void)
+{
+ return false;
+}
#endif /* CONFIG_RISCV_SBI */
#endif /* _ASM_RISCV_SBI_H */
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 3c34aba30f6f..9bdc9801784d 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -12,6 +12,8 @@
/* default SBI version is 0.1 */
unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT;
+bool sbi_hsm_avail;
+
EXPORT_SYMBOL(sbi_spec_version);
static void (*__sbi_set_timer)(uint64_t stime);
@@ -496,6 +498,54 @@ static void sbi_power_off(void)
sbi_shutdown();
}
+int sbi_hsm_hart_stop(void)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_STOP, 0, 0, 0, 0, 0, 0);
+
+ if (!ret.error)
+ return ret.value;
+ else
+ return sbi_err_map_linux_errno(ret.error);
+}
+EXPORT_SYMBOL(sbi_hsm_hart_stop);
+
+int sbi_hsm_hart_start(unsigned long hartid, unsigned long saddr,
+ unsigned long priv)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_START,
+ hartid, saddr, priv, 0, 0, 0);
+ if (!ret.error)
+ return ret.value;
+ else
+ return sbi_err_map_linux_errno(ret.error);
+}
+EXPORT_SYMBOL(sbi_hsm_hart_start);
+
+int sbi_hsm_hart_get_status(unsigned long hartid)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_STATUS,
+ hartid, 0, 0, 0, 0, 0);
+ if (!ret.error)
+ return ret.value;
+ else
+ return sbi_err_map_linux_errno(ret.error);
+}
+EXPORT_SYMBOL(sbi_hsm_hart_get_status);
+
+void __init sbi_hsm_ext_init(void)
+{
+ if (sbi_probe_extension(SBI_EXT_HSM) > 0) {
+ pr_info("SBI v0.2 HSM extension detected\n");
+ sbi_hsm_avail = true;
+ }
+}
+
int __init sbi_init(void)
{
int ret;
@@ -532,5 +582,6 @@ int __init sbi_init(void)
__sbi_rfence = __sbi_rfence_v01;
}
+ sbi_hsm_ext_init();
return 0;
}
--
2.24.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v7 08/10] RISC-V: Add SBI HSM extension
2020-01-28 2:27 ` [PATCH v7 08/10] RISC-V: Add SBI HSM extension Atish Patra
@ 2020-01-28 4:54 ` Anup Patel
2020-02-05 0:11 ` Atish Patra
0 siblings, 1 reply; 22+ messages in thread
From: Anup Patel @ 2020-01-28 4:54 UTC (permalink / raw)
To: Atish Patra
Cc: Albert Ou, Thomas Gleixner, Kees Cook, Abner Chang, nickhu,
Greg Kroah-Hartman, Palmer Dabbelt, Heiko Carstens,
linux-kernel@vger.kernel.org List, Mike Rapoport, Chester Lin,
Vincent Chen, Geert Uytterhoeven, Eric W. Biederman,
Paul Walmsley, Greentime Hu, linux-riscv, Borislav Petkov,
Palmer Dabbelt, Mao Han
On Tue, Jan 28, 2020 at 7:58 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> SBI specification defines HSM extension that allows to start/stop a hart
> by a supervisor anytime. The specification is available at
>
> https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
>
> Implement SBI HSM extension.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> arch/riscv/include/asm/sbi.h | 22 ++++++++++++++++
> arch/riscv/kernel/sbi.c | 51 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 73 insertions(+)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index d55d8090ab5c..bed6fa26ec84 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -26,6 +26,7 @@ enum sbi_ext_id {
> SBI_EXT_TIME = 0x54494D45,
> SBI_EXT_IPI = 0x735049,
> SBI_EXT_RFENCE = 0x52464E43,
> + SBI_EXT_HSM = 0x48534D,
> };
>
> enum sbi_ext_base_fid {
> @@ -56,6 +57,12 @@ enum sbi_ext_rfence_fid {
> SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
> };
>
> +enum sbi_ext_hsm_fid {
> + SBI_EXT_HSM_HART_START = 0,
> + SBI_EXT_HSM_HART_STOP,
> + SBI_EXT_HSM_HART_STATUS,
> +};
> +
I think we should also define the possible return values of
SBI_EXT_HSM_HART_STATUS function.
> #define SBI_SPEC_VERSION_DEFAULT 0x1
> #define SBI_SPEC_VERSION_MAJOR_SHIFT 24
> #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
> @@ -70,6 +77,7 @@ enum sbi_ext_rfence_fid {
> #define SBI_ERR_INVALID_ADDRESS -5
>
> extern unsigned long sbi_spec_version;
> +extern bool sbi_hsm_avail;
> struct sbiret {
> long error;
> long value;
> @@ -110,8 +118,18 @@ int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
> unsigned long start,
> unsigned long size,
> unsigned long asid);
> +int sbi_hsm_hart_start(unsigned long hartid, unsigned long saddr,
> + unsigned long priv);
> +int sbi_hsm_hart_stop(void);
> +int sbi_hsm_hart_get_status(unsigned long hartid);
> +
> int sbi_probe_extension(int ext);
>
> +static inline bool sbi_hsm_is_available(void)
> +{
> + return sbi_hsm_avail;
> +}
> +
> /* Check if current SBI specification version is 0.1 or not */
> static inline int sbi_spec_is_0_1(void)
> {
> @@ -137,5 +155,9 @@ void sbi_clear_ipi(void);
> void sbi_send_ipi(const unsigned long *hart_mask);
> void sbi_remote_fence_i(const unsigned long *hart_mask);
> void sbi_init(void);
> +static inline bool sbi_hsm_is_available(void)
> +{
> + return false;
> +}
> #endif /* CONFIG_RISCV_SBI */
> #endif /* _ASM_RISCV_SBI_H */
> diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> index 3c34aba30f6f..9bdc9801784d 100644
> --- a/arch/riscv/kernel/sbi.c
> +++ b/arch/riscv/kernel/sbi.c
> @@ -12,6 +12,8 @@
>
> /* default SBI version is 0.1 */
> unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT;
> +bool sbi_hsm_avail;
> +
> EXPORT_SYMBOL(sbi_spec_version);
>
> static void (*__sbi_set_timer)(uint64_t stime);
> @@ -496,6 +498,54 @@ static void sbi_power_off(void)
> sbi_shutdown();
> }
>
> +int sbi_hsm_hart_stop(void)
> +{
> + struct sbiret ret;
> +
> + ret = sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_STOP, 0, 0, 0, 0, 0, 0);
> +
> + if (!ret.error)
> + return ret.value;
> + else
> + return sbi_err_map_linux_errno(ret.error);
> +}
> +EXPORT_SYMBOL(sbi_hsm_hart_stop);
> +
> +int sbi_hsm_hart_start(unsigned long hartid, unsigned long saddr,
> + unsigned long priv)
> +{
> + struct sbiret ret;
> +
> + ret = sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_START,
> + hartid, saddr, priv, 0, 0, 0);
> + if (!ret.error)
> + return ret.value;
> + else
> + return sbi_err_map_linux_errno(ret.error);
> +}
> +EXPORT_SYMBOL(sbi_hsm_hart_start);
> +
> +int sbi_hsm_hart_get_status(unsigned long hartid)
> +{
> + struct sbiret ret;
> +
> + ret = sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_STATUS,
> + hartid, 0, 0, 0, 0, 0);
> + if (!ret.error)
> + return ret.value;
> + else
> + return sbi_err_map_linux_errno(ret.error);
> +}
> +EXPORT_SYMBOL(sbi_hsm_hart_get_status);
> +
> +void __init sbi_hsm_ext_init(void)
> +{
> + if (sbi_probe_extension(SBI_EXT_HSM) > 0) {
> + pr_info("SBI v0.2 HSM extension detected\n");
> + sbi_hsm_avail = true;
> + }
> +}
> +
If we start adding all present and future extensions in
arch/riscv/kernel/sbi.c then it will blow-up.
IMHO, we should only keep legacy and replacement
extension in arch/riscv/kernel/sbi.c. All other extensions
will be separate based on how they are integrated.
For SBI HSM, all sbi_hsm_xyz() functions should be in
arch/riscv/kernel/cpu_ops_sbi.c which will be only compiled
when CONFIG_RISCV_SBI is enabled.
Maybe merge PATCH8 and PATCH9 ?
Regards,
Anup
> int __init sbi_init(void)
> {
> int ret;
> @@ -532,5 +582,6 @@ int __init sbi_init(void)
> __sbi_rfence = __sbi_rfence_v01;
> }
>
> + sbi_hsm_ext_init();
We don't need sbi_hsm_ext_init() because we can check
and set CPU ops at boot-time in cpu_set_ops()
> return 0;
> }
> --
> 2.24.0
>
Regards,
Anup
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v7 08/10] RISC-V: Add SBI HSM extension
2020-01-28 4:54 ` Anup Patel
@ 2020-02-05 0:11 ` Atish Patra
0 siblings, 0 replies; 22+ messages in thread
From: Atish Patra @ 2020-02-05 0:11 UTC (permalink / raw)
To: Anup Patel
Cc: Albert Ou, Kees Cook, nickhu, Vincent Chen, Greg Kroah-Hartman,
Palmer Dabbelt, Heiko Carstens,
linux-kernel@vger.kernel.org List, Mike Rapoport, Chester Lin,
Atish Patra, Palmer Dabbelt, Geert Uytterhoeven,
Eric W. Biederman, Paul Walmsley, Greentime Hu, Thomas Gleixner,
Borislav Petkov, Abner Chang, linux-riscv, Mao Han
On Mon, Jan 27, 2020 at 8:54 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Tue, Jan 28, 2020 at 7:58 AM Atish Patra <atish.patra@wdc.com> wrote:
> >
> > SBI specification defines HSM extension that allows to start/stop a hart
> > by a supervisor anytime. The specification is available at
> >
> > https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
> >
> > Implement SBI HSM extension.
> >
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > ---
> > arch/riscv/include/asm/sbi.h | 22 ++++++++++++++++
> > arch/riscv/kernel/sbi.c | 51 ++++++++++++++++++++++++++++++++++++
> > 2 files changed, 73 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> > index d55d8090ab5c..bed6fa26ec84 100644
> > --- a/arch/riscv/include/asm/sbi.h
> > +++ b/arch/riscv/include/asm/sbi.h
> > @@ -26,6 +26,7 @@ enum sbi_ext_id {
> > SBI_EXT_TIME = 0x54494D45,
> > SBI_EXT_IPI = 0x735049,
> > SBI_EXT_RFENCE = 0x52464E43,
> > + SBI_EXT_HSM = 0x48534D,
> > };
> >
> > enum sbi_ext_base_fid {
> > @@ -56,6 +57,12 @@ enum sbi_ext_rfence_fid {
> > SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
> > };
> >
> > +enum sbi_ext_hsm_fid {
> > + SBI_EXT_HSM_HART_START = 0,
> > + SBI_EXT_HSM_HART_STOP,
> > + SBI_EXT_HSM_HART_STATUS,
> > +};
> > +
>
> I think we should also define the possible return values of
> SBI_EXT_HSM_HART_STATUS function.
>
Done.
> > #define SBI_SPEC_VERSION_DEFAULT 0x1
> > #define SBI_SPEC_VERSION_MAJOR_SHIFT 24
> > #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
> > @@ -70,6 +77,7 @@ enum sbi_ext_rfence_fid {
> > #define SBI_ERR_INVALID_ADDRESS -5
> >
> > extern unsigned long sbi_spec_version;
> > +extern bool sbi_hsm_avail;
> > struct sbiret {
> > long error;
> > long value;
> > @@ -110,8 +118,18 @@ int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
> > unsigned long start,
> > unsigned long size,
> > unsigned long asid);
> > +int sbi_hsm_hart_start(unsigned long hartid, unsigned long saddr,
> > + unsigned long priv);
> > +int sbi_hsm_hart_stop(void);
> > +int sbi_hsm_hart_get_status(unsigned long hartid);
> > +
> > int sbi_probe_extension(int ext);
> >
> > +static inline bool sbi_hsm_is_available(void)
> > +{
> > + return sbi_hsm_avail;
> > +}
> > +
> > /* Check if current SBI specification version is 0.1 or not */
> > static inline int sbi_spec_is_0_1(void)
> > {
> > @@ -137,5 +155,9 @@ void sbi_clear_ipi(void);
> > void sbi_send_ipi(const unsigned long *hart_mask);
> > void sbi_remote_fence_i(const unsigned long *hart_mask);
> > void sbi_init(void);
> > +static inline bool sbi_hsm_is_available(void)
> > +{
> > + return false;
> > +}
> > #endif /* CONFIG_RISCV_SBI */
> > #endif /* _ASM_RISCV_SBI_H */
> > diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> > index 3c34aba30f6f..9bdc9801784d 100644
> > --- a/arch/riscv/kernel/sbi.c
> > +++ b/arch/riscv/kernel/sbi.c
> > @@ -12,6 +12,8 @@
> >
> > /* default SBI version is 0.1 */
> > unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT;
> > +bool sbi_hsm_avail;
> > +
> > EXPORT_SYMBOL(sbi_spec_version);
> >
> > static void (*__sbi_set_timer)(uint64_t stime);
> > @@ -496,6 +498,54 @@ static void sbi_power_off(void)
> > sbi_shutdown();
> > }
> >
> > +int sbi_hsm_hart_stop(void)
> > +{
> > + struct sbiret ret;
> > +
> > + ret = sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_STOP, 0, 0, 0, 0, 0, 0);
> > +
> > + if (!ret.error)
> > + return ret.value;
> > + else
> > + return sbi_err_map_linux_errno(ret.error);
> > +}
> > +EXPORT_SYMBOL(sbi_hsm_hart_stop);
> > +
> > +int sbi_hsm_hart_start(unsigned long hartid, unsigned long saddr,
> > + unsigned long priv)
> > +{
> > + struct sbiret ret;
> > +
> > + ret = sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_START,
> > + hartid, saddr, priv, 0, 0, 0);
> > + if (!ret.error)
> > + return ret.value;
> > + else
> > + return sbi_err_map_linux_errno(ret.error);
> > +}
> > +EXPORT_SYMBOL(sbi_hsm_hart_start);
> > +
> > +int sbi_hsm_hart_get_status(unsigned long hartid)
> > +{
> > + struct sbiret ret;
> > +
> > + ret = sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_STATUS,
> > + hartid, 0, 0, 0, 0, 0);
> > + if (!ret.error)
> > + return ret.value;
> > + else
> > + return sbi_err_map_linux_errno(ret.error);
> > +}
> > +EXPORT_SYMBOL(sbi_hsm_hart_get_status);
> > +
> > +void __init sbi_hsm_ext_init(void)
> > +{
> > + if (sbi_probe_extension(SBI_EXT_HSM) > 0) {
> > + pr_info("SBI v0.2 HSM extension detected\n");
> > + sbi_hsm_avail = true;
> > + }
> > +}
> > +
>
> If we start adding all present and future extensions in
> arch/riscv/kernel/sbi.c then it will blow-up.
>
> IMHO, we should only keep legacy and replacement
> extension in arch/riscv/kernel/sbi.c. All other extensions
> will be separate based on how they are integrated.
>
> For SBI HSM, all sbi_hsm_xyz() functions should be in
> arch/riscv/kernel/cpu_ops_sbi.c which will be only compiled
> when CONFIG_RISCV_SBI is enabled.
>
> Maybe merge PATCH8 and PATCH9 ?
>
Sure. I am fine with that. However, I think we don't need to move
spinwait ops to its
own file as it won't grow in the future. I have refactored the series
in the following way.
1. Move cpu_sbi_ops and sbi_hsm_xyz to its own file which can be
compiled out with CONFIG_RISCV_SBI.
2. Keep spinwait and other cpu_ops related functions in cpu_ops.c
Let me know if you think that's not a good idea.
> Regards,
> Anup
>
> > int __init sbi_init(void)
> > {
> > int ret;
> > @@ -532,5 +582,6 @@ int __init sbi_init(void)
> > __sbi_rfence = __sbi_rfence_v01;
> > }
> >
> > + sbi_hsm_ext_init();
>
> We don't need sbi_hsm_ext_init() because we can check
> and set CPU ops at boot-time in cpu_set_ops()
>
> > return 0;
> > }
> > --
> > 2.24.0
> >
>
> Regards,
> Anup
>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v7 09/10] RISC-V: Add supported for ordered booting method using HSM
2020-01-28 2:27 [PATCH v7 00/10] Add support for SBI v0.2 and CPU hotplug Atish Patra
` (7 preceding siblings ...)
2020-01-28 2:27 ` [PATCH v7 08/10] RISC-V: Add SBI HSM extension Atish Patra
@ 2020-01-28 2:27 ` Atish Patra
2020-01-28 2:27 ` [PATCH v7 10/10] RISC-V: Support cpu hotplug Atish Patra
9 siblings, 0 replies; 22+ messages in thread
From: Atish Patra @ 2020-01-28 2:27 UTC (permalink / raw)
To: linux-kernel
Cc: Albert Ou, Thomas Gleixner, Kees Cook, abner.chang, Vincent Chen,
nickhu, Anup Patel, Paul Walmsley, Heiko Carstens, Mike Rapoport,
clin, Atish Patra, Geert Uytterhoeven, Eric W. Biederman,
Greg Kroah-Hartman, Palmer Dabbelt, Greentime Hu, linux-riscv,
Borislav Petkov, Palmer Dabbelt, Mao Han
Currently, all harts have to jump Linux in RISC-V. This complicates the
multi-stage boot process as every transient stage also has to ensure all
harts enter to that stage and jump to Linux afterwards. It also obstructs
a clean Kexec implementation.
SBI HSM extension provides alternate solutions where only a single hart
need to boot and enter Linux. The booting hart can bring up secondary
harts one by one afterwards.
Add SBI HSM based cpu_ops that implements an ordered booting method in
RISC-V. This change is also backward compatible with older firmware not
implementing HSM extension. If a latest kernel is used with older
firmware, it will continue to use the default spinning booting method.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
arch/riscv/kernel/cpu_ops.c | 41 ++++++++++++++++++++++++++++++++++++-
arch/riscv/kernel/head.S | 25 ++++++++++++++++++++++
arch/riscv/kernel/smpboot.c | 2 +-
arch/riscv/kernel/traps.c | 2 +-
4 files changed, 67 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c
index 099dbb6ff9f0..454df032066f 100644
--- a/arch/riscv/kernel/cpu_ops.c
+++ b/arch/riscv/kernel/cpu_ops.c
@@ -17,9 +17,13 @@ const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init;
void *__cpu_up_stack_pointer[NR_CPUS];
void *__cpu_up_task_pointer[NR_CPUS];
+extern char secondary_start_sbi[];
+const struct cpu_operations cpu_sbi_ops;
const struct cpu_operations cpu_spinwait_ops;
+#define RISCV_HART_FIRMWARE_STOPPED 0
+
static int spinwait_cpu_prepare(unsigned int cpuid)
{
if (!cpu_spinwait_ops.cpu_start) {
@@ -29,6 +33,32 @@ static int spinwait_cpu_prepare(unsigned int cpuid)
return 0;
}
+static int sbi_cpu_prepare(unsigned int cpuid)
+{
+ if (!cpu_sbi_ops.cpu_start) {
+ pr_err("cpu start method not defined for CPU [%d]\n", cpuid);
+ return -ENODEV;
+ }
+ return 0;
+}
+
+static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle)
+{
+ int rc;
+ int hartid = cpuid_to_hartid_map(cpuid);
+ unsigned long boot_addr = __pa_symbol(secondary_start_sbi);
+
+ /* Make sure tidle is updated */
+ smp_mb();
+ WRITE_ONCE(__cpu_up_stack_pointer[hartid],
+ task_stack_page(tidle) + THREAD_SIZE);
+ WRITE_ONCE(__cpu_up_task_pointer[hartid], tidle);
+
+ rc = sbi_hsm_hart_start(hartid, boot_addr, 0);
+
+ return rc;
+}
+
static int spinwait_cpu_start(unsigned int cpuid, struct task_struct *tidle)
{
int hartid = cpuid_to_hartid_map(cpuid);
@@ -48,6 +78,12 @@ static int spinwait_cpu_start(unsigned int cpuid, struct task_struct *tidle)
return 0;
}
+const struct cpu_operations cpu_sbi_ops = {
+ .name = "sbi",
+ .cpu_prepare = sbi_cpu_prepare,
+ .cpu_start = sbi_cpu_start,
+};
+
const struct cpu_operations cpu_spinwait_ops = {
.name = "spinwait",
.cpu_prepare = spinwait_cpu_prepare,
@@ -56,6 +92,9 @@ const struct cpu_operations cpu_spinwait_ops = {
int __init cpu_set_ops(int cpuid)
{
- cpu_ops[cpuid] = &cpu_spinwait_ops;
+ if (sbi_hsm_is_available())
+ cpu_ops[cpuid] = &cpu_sbi_ops;
+ else
+ cpu_ops[cpuid] = &cpu_spinwait_ops;
return 0;
}
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 9d7f084a50cc..3c93973667c8 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -210,11 +210,36 @@ relocate:
ret
#endif /* CONFIG_MMU */
#ifdef CONFIG_SMP
+ .global secondary_start_sbi
+secondary_start_sbi:
+ /* Mask all interrupts */
+ csrw CSR_IE, zero
+ csrw CSR_IP, zero
+
+ /* Load the global pointer */
+ .option push
+ .option norelax
+ la gp, __global_pointer$
+ .option pop
+
+ /*
+ * Disable FPU to detect illegal usage of
+ * floating point in kernel space
+ */
+ li t0, SR_FS
+ csrc CSR_STATUS, t0
+
/* Set trap vector to spin forever to help debug */
la a3, .Lsecondary_park
csrw CSR_TVEC, a3
slli a3, a0, LGREG
+ la a4, __cpu_up_stack_pointer
+ la a5, __cpu_up_task_pointer
+ add a4, a3, a4
+ add a5, a3, a5
+ REG_L sp, (a4)
+ REG_L tp, (a5)
.global secondary_start_common
secondary_start_common:
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index f2cf541bc895..8ac9115001b9 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -144,7 +144,7 @@ void __init smp_cpus_done(unsigned int max_cpus)
/*
* C entry point for a secondary processor.
*/
-asmlinkage __visible void __init smp_callin(void)
+asmlinkage __visible void smp_callin(void)
{
struct mm_struct *mm = &init_mm;
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index f4cad5163bf2..0063dd7318d6 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -147,7 +147,7 @@ int is_valid_bugaddr(unsigned long pc)
}
#endif /* CONFIG_GENERIC_BUG */
-void __init trap_init(void)
+void trap_init(void)
{
/*
* Set sup0 scratch register to 0, indicating to exception vector
--
2.24.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v7 10/10] RISC-V: Support cpu hotplug
2020-01-28 2:27 [PATCH v7 00/10] Add support for SBI v0.2 and CPU hotplug Atish Patra
` (8 preceding siblings ...)
2020-01-28 2:27 ` [PATCH v7 09/10] RISC-V: Add supported for ordered booting method using HSM Atish Patra
@ 2020-01-28 2:27 ` Atish Patra
2020-01-28 5:00 ` Anup Patel
9 siblings, 1 reply; 22+ messages in thread
From: Atish Patra @ 2020-01-28 2:27 UTC (permalink / raw)
To: linux-kernel
Cc: Albert Ou, Thomas Gleixner, Kees Cook, abner.chang, Vincent Chen,
nickhu, Anup Patel, Paul Walmsley, Heiko Carstens, Mike Rapoport,
clin, Atish Patra, Geert Uytterhoeven, Eric W. Biederman,
Greg Kroah-Hartman, Palmer Dabbelt, Greentime Hu, linux-riscv,
Borislav Petkov, Palmer Dabbelt, Mao Han
This patch enable support for cpu hotplug in RISC-V. It uses SBI HSM
extension to online/offline any hart. As a result, the harts are
returned to firmware once they are offline. If the harts are brought
online afterwards, they re-enter Linux kernel as if a secondary hart
booted for the first time. All booting requirements are honored during
this process.
Tested both on QEMU and HighFive Unleashed board with. Test result follows.
---------------------------------------------------
Offline cpu 2
---------------------------------------------------
$ echo 0 > /sys/devices/system/cpu/cpu2/online
[ 32.828684] CPU2: off
$ cat /proc/cpuinfo
processor : 0
hart : 0
isa : rv64imafdcsu
mmu : sv48
processor : 1
hart : 1
isa : rv64imafdcsu
mmu : sv48
processor : 3
hart : 3
isa : rv64imafdcsu
mmu : sv48
processor : 4
hart : 4
isa : rv64imafdcsu
mmu : sv48
processor : 5
hart : 5
isa : rv64imafdcsu
mmu : sv48
processor : 6
hart : 6
isa : rv64imafdcsu
mmu : sv48
processor : 7
hart : 7
isa : rv64imafdcsu
mmu : sv48
---------------------------------------------------
online cpu 2
---------------------------------------------------
$ echo 1 > /sys/devices/system/cpu/cpu2/online
$ cat /proc/cpuinfo
processor : 0
hart : 0
isa : rv64imafdcsu
mmu : sv48
processor : 1
hart : 1
isa : rv64imafdcsu
mmu : sv48
processor : 2
hart : 2
isa : rv64imafdcsu
mmu : sv48
processor : 3
hart : 3
isa : rv64imafdcsu
mmu : sv48
processor : 4
hart : 4
isa : rv64imafdcsu
mmu : sv48
processor : 5
hart : 5
isa : rv64imafdcsu
mmu : sv48
processor : 6
hart : 6
isa : rv64imafdcsu
mmu : sv48
processor : 7
hart : 7
isa : rv64imafdcsu
mmu : sv48
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
arch/riscv/Kconfig | 12 ++++-
arch/riscv/include/asm/cpu_ops.h | 5 ++
arch/riscv/include/asm/smp.h | 7 +++
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/cpu-hotplug.c | 84 ++++++++++++++++++++++++++++++++
arch/riscv/kernel/cpu_ops.c | 34 +++++++++++++
arch/riscv/kernel/setup.c | 26 ++++++++++
7 files changed, 168 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/kernel/cpu-hotplug.c
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 518da42be545..99fb481dc805 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -22,7 +22,6 @@ config RISCV
select CLONE_BACKWARDS
select COMMON_CLK
select GENERIC_CLOCKEVENTS
- select GENERIC_CPU_DEVICES
select GENERIC_IRQ_SHOW
select GENERIC_PCI_IOMAP
select GENERIC_SCHED_CLOCK
@@ -247,6 +246,17 @@ config NR_CPUS
depends on SMP
default "8"
+config HOTPLUG_CPU
+ bool "Support for hot-pluggable CPUs"
+ depends on SMP
+ select GENERIC_IRQ_MIGRATION
+ help
+
+ Say Y here to experiment with turning CPUs off and on. CPUs
+ can be controlled through /sys/devices/system/cpu.
+
+ Say N if you want to disable CPU hotplug.
+
choice
prompt "CPU Tuning"
default TUNE_GENERIC
diff --git a/arch/riscv/include/asm/cpu_ops.h b/arch/riscv/include/asm/cpu_ops.h
index 27e9dfee5460..d53d7086f627 100644
--- a/arch/riscv/include/asm/cpu_ops.h
+++ b/arch/riscv/include/asm/cpu_ops.h
@@ -23,6 +23,11 @@ struct cpu_operations {
int (*cpu_prepare)(unsigned int cpu);
int (*cpu_start)(unsigned int cpu,
struct task_struct *tidle);
+#ifdef CONFIG_HOTPLUG_CPU
+ int (*cpu_disable)(unsigned int cpu);
+ void (*cpu_stop)(void);
+ int (*cpu_is_stopped)(unsigned int cpu);
+#endif
};
extern const struct cpu_operations *cpu_ops[NR_CPUS];
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 023f74fb8b3b..8d9c50c0f91c 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -43,6 +43,13 @@ void riscv_cpuid_to_hartid_mask(const struct cpumask *in, struct cpumask *out);
*/
#define raw_smp_processor_id() (current_thread_info()->cpu)
+#if defined CONFIG_HOTPLUG_CPU
+int __cpu_disable(void);
+void __cpu_die(unsigned int cpu);
+void cpu_stop(void);
+#else
+#endif /* CONFIG_HOTPLUG_CPU */
+
#else
static inline void show_ipi_stats(struct seq_file *p, int prec)
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index d77def5b4e87..6fe35a719de1 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -43,5 +43,6 @@ obj-$(CONFIG_PERF_EVENTS) += perf_event.o
obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o
obj-$(CONFIG_HAVE_PERF_REGS) += perf_regs.o
obj-$(CONFIG_RISCV_SBI) += sbi.o
+obj-$(CONFIG_HOTPLUG_CPU) += cpu-hotplug.o
clean:
diff --git a/arch/riscv/kernel/cpu-hotplug.c b/arch/riscv/kernel/cpu-hotplug.c
new file mode 100644
index 000000000000..835b0747803e
--- /dev/null
+++ b/arch/riscv/kernel/cpu-hotplug.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Western Digital Corporation or its affiliates.
+ */
+
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/err.h>
+#include <linux/irq.h>
+#include <linux/cpu.h>
+#include <linux/sched/hotplug.h>
+#include <asm/irq.h>
+#include <asm/cpu_ops.h>
+#include <asm/sbi.h>
+
+void cpu_stop(void);
+bool can_hotplug_cpu(void)
+{
+ return true;
+}
+
+void arch_cpu_idle_dead(void)
+{
+ cpu_stop();
+}
+
+/*
+ * __cpu_disable runs on the processor to be shutdown.
+ */
+int __cpu_disable(void)
+{
+ int ret = 0;
+ unsigned int cpu = smp_processor_id();
+
+ if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_stop)
+ return -EOPNOTSUPP;
+
+ if (cpu_ops[cpu]->cpu_disable)
+ ret = cpu_ops[cpu]->cpu_disable(cpu);
+
+ if (ret)
+ return ret;
+
+ remove_cpu_topology(cpu);
+ set_cpu_online(cpu, false);
+ irq_migrate_all_off_this_cpu();
+
+ return ret;
+}
+
+/*
+ * Called on the thread which is asking for a CPU to be shutdown.
+ */
+void __cpu_die(unsigned int cpu)
+{
+ int ret = 0;
+
+ if (!cpu_wait_death(cpu, 5)) {
+ pr_err("CPU %u: didn't die\n", cpu);
+ return;
+ }
+ pr_notice("CPU%u: off\n", cpu);
+
+ /* Verify from the firmware if the cpu is really stopped*/
+ if (cpu_ops[cpu]->cpu_is_stopped)
+ ret = cpu_ops[cpu]->cpu_is_stopped(cpu);
+ if (ret)
+ pr_warn("CPU%d may not have stopped: %d\n", cpu, ret);
+}
+
+/*
+ * Called from the idle thread for the CPU which has been shutdown.
+ */
+void cpu_stop(void)
+{
+ idle_task_exit();
+
+ (void)cpu_report_death();
+
+ cpu_ops[smp_processor_id()]->cpu_stop();
+ /* It should never reach here */
+ BUG();
+}
diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c
index 454df032066f..9b315137b945 100644
--- a/arch/riscv/kernel/cpu_ops.c
+++ b/arch/riscv/kernel/cpu_ops.c
@@ -59,6 +59,34 @@ static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle)
return rc;
}
+#ifdef CONFIG_HOTPLUG_CPU
+static int sbi_cpu_disable(unsigned int cpuid)
+{
+ if (!cpu_sbi_ops.cpu_stop)
+ return -EOPNOTSUPP;
+ return 0;
+}
+
+static void sbi_cpu_stop(void)
+{
+ int ret;
+
+ ret = sbi_hsm_hart_stop();
+ pr_crit("Unable to stop the cpu %u (%d)\n", smp_processor_id(), ret);
+}
+
+static int sbi_cpu_is_stopped(unsigned int cpuid)
+{
+ int rc;
+ int hartid = cpuid_to_hartid_map(cpuid);
+
+ rc = sbi_hsm_hart_get_status(hartid);
+
+ if (rc == RISCV_HART_FIRMWARE_STOPPED)
+ return 0;
+ return rc;
+}
+#endif
static int spinwait_cpu_start(unsigned int cpuid, struct task_struct *tidle)
{
int hartid = cpuid_to_hartid_map(cpuid);
@@ -82,6 +110,11 @@ const struct cpu_operations cpu_sbi_ops = {
.name = "sbi",
.cpu_prepare = sbi_cpu_prepare,
.cpu_start = sbi_cpu_start,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_disable = sbi_cpu_disable,
+ .cpu_stop = sbi_cpu_stop,
+ .cpu_is_stopped = sbi_cpu_is_stopped,
+#endif
};
const struct cpu_operations cpu_spinwait_ops = {
@@ -90,6 +123,7 @@ const struct cpu_operations cpu_spinwait_ops = {
.cpu_start = spinwait_cpu_start,
};
+
int __init cpu_set_ops(int cpuid)
{
if (sbi_hsm_is_available())
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index 8208d1109ddb..dfab3bd40f2a 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -43,6 +43,7 @@ struct screen_info screen_info = {
/* The lucky hart to first increment this variable will boot the other cores */
atomic_t hart_lottery;
unsigned long boot_cpu_hartid;
+static DEFINE_PER_CPU(struct cpu, cpu_devices);
void __init parse_dtb(void)
{
@@ -90,3 +91,28 @@ void __init setup_arch(char **cmdline_p)
riscv_fill_hwcap();
}
+
+static inline bool can_hotplug_cpu(unsigned int cpu)
+{
+#ifdef CONFIG_HOTPLUG_CPU
+ if (cpu_ops[cpu]->cpu_stop)
+ return true;
+#endif
+ return false;
+}
+
+static int __init topology_init(void)
+{
+ int i;
+
+ pr_err("%s: In\n", __func__);
+ for_each_possible_cpu(i) {
+ struct cpu *cpu = &per_cpu(cpu_devices, i);
+
+ cpu->hotpluggable = can_hotplug_cpu(i);
+ register_cpu(cpu, i);
+ }
+
+ return 0;
+}
+subsys_initcall(topology_init);
--
2.24.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v7 10/10] RISC-V: Support cpu hotplug
2020-01-28 2:27 ` [PATCH v7 10/10] RISC-V: Support cpu hotplug Atish Patra
@ 2020-01-28 5:00 ` Anup Patel
2020-01-28 19:32 ` Atish Patra
0 siblings, 1 reply; 22+ messages in thread
From: Anup Patel @ 2020-01-28 5:00 UTC (permalink / raw)
To: Atish Patra
Cc: Albert Ou, Thomas Gleixner, Kees Cook, Abner Chang, nickhu,
Greg Kroah-Hartman, Palmer Dabbelt, Heiko Carstens,
linux-kernel@vger.kernel.org List, Mike Rapoport, Chester Lin,
Vincent Chen, Geert Uytterhoeven, Eric W. Biederman,
Paul Walmsley, Greentime Hu, linux-riscv, Borislav Petkov,
Palmer Dabbelt, Mao Han
On Tue, Jan 28, 2020 at 7:58 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> This patch enable support for cpu hotplug in RISC-V. It uses SBI HSM
> extension to online/offline any hart. As a result, the harts are
> returned to firmware once they are offline. If the harts are brought
> online afterwards, they re-enter Linux kernel as if a secondary hart
> booted for the first time. All booting requirements are honored during
> this process.
>
> Tested both on QEMU and HighFive Unleashed board with. Test result follows.
>
> ---------------------------------------------------
> Offline cpu 2
> ---------------------------------------------------
> $ echo 0 > /sys/devices/system/cpu/cpu2/online
> [ 32.828684] CPU2: off
> $ cat /proc/cpuinfo
> processor : 0
> hart : 0
> isa : rv64imafdcsu
> mmu : sv48
>
> processor : 1
> hart : 1
> isa : rv64imafdcsu
> mmu : sv48
>
> processor : 3
> hart : 3
> isa : rv64imafdcsu
> mmu : sv48
>
> processor : 4
> hart : 4
> isa : rv64imafdcsu
> mmu : sv48
>
> processor : 5
> hart : 5
> isa : rv64imafdcsu
> mmu : sv48
>
> processor : 6
> hart : 6
> isa : rv64imafdcsu
> mmu : sv48
>
> processor : 7
> hart : 7
> isa : rv64imafdcsu
> mmu : sv48
>
> ---------------------------------------------------
> online cpu 2
> ---------------------------------------------------
> $ echo 1 > /sys/devices/system/cpu/cpu2/online
> $ cat /proc/cpuinfo
> processor : 0
> hart : 0
> isa : rv64imafdcsu
> mmu : sv48
>
> processor : 1
> hart : 1
> isa : rv64imafdcsu
> mmu : sv48
>
> processor : 2
> hart : 2
> isa : rv64imafdcsu
> mmu : sv48
>
> processor : 3
> hart : 3
> isa : rv64imafdcsu
> mmu : sv48
>
> processor : 4
> hart : 4
> isa : rv64imafdcsu
> mmu : sv48
>
> processor : 5
> hart : 5
> isa : rv64imafdcsu
> mmu : sv48
>
> processor : 6
> hart : 6
> isa : rv64imafdcsu
> mmu : sv48
>
> processor : 7
> hart : 7
> isa : rv64imafdcsu
> mmu : sv48
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> arch/riscv/Kconfig | 12 ++++-
> arch/riscv/include/asm/cpu_ops.h | 5 ++
> arch/riscv/include/asm/smp.h | 7 +++
> arch/riscv/kernel/Makefile | 1 +
> arch/riscv/kernel/cpu-hotplug.c | 84 ++++++++++++++++++++++++++++++++
> arch/riscv/kernel/cpu_ops.c | 34 +++++++++++++
> arch/riscv/kernel/setup.c | 26 ++++++++++
> 7 files changed, 168 insertions(+), 1 deletion(-)
> create mode 100644 arch/riscv/kernel/cpu-hotplug.c
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 518da42be545..99fb481dc805 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -22,7 +22,6 @@ config RISCV
> select CLONE_BACKWARDS
> select COMMON_CLK
> select GENERIC_CLOCKEVENTS
> - select GENERIC_CPU_DEVICES
> select GENERIC_IRQ_SHOW
> select GENERIC_PCI_IOMAP
> select GENERIC_SCHED_CLOCK
> @@ -247,6 +246,17 @@ config NR_CPUS
> depends on SMP
> default "8"
>
> +config HOTPLUG_CPU
> + bool "Support for hot-pluggable CPUs"
> + depends on SMP
> + select GENERIC_IRQ_MIGRATION
> + help
> +
> + Say Y here to experiment with turning CPUs off and on. CPUs
> + can be controlled through /sys/devices/system/cpu.
> +
> + Say N if you want to disable CPU hotplug.
> +
> choice
> prompt "CPU Tuning"
> default TUNE_GENERIC
> diff --git a/arch/riscv/include/asm/cpu_ops.h b/arch/riscv/include/asm/cpu_ops.h
> index 27e9dfee5460..d53d7086f627 100644
> --- a/arch/riscv/include/asm/cpu_ops.h
> +++ b/arch/riscv/include/asm/cpu_ops.h
> @@ -23,6 +23,11 @@ struct cpu_operations {
> int (*cpu_prepare)(unsigned int cpu);
> int (*cpu_start)(unsigned int cpu,
> struct task_struct *tidle);
> +#ifdef CONFIG_HOTPLUG_CPU
> + int (*cpu_disable)(unsigned int cpu);
> + void (*cpu_stop)(void);
> + int (*cpu_is_stopped)(unsigned int cpu);
> +#endif
> };
>
> extern const struct cpu_operations *cpu_ops[NR_CPUS];
> diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
> index 023f74fb8b3b..8d9c50c0f91c 100644
> --- a/arch/riscv/include/asm/smp.h
> +++ b/arch/riscv/include/asm/smp.h
> @@ -43,6 +43,13 @@ void riscv_cpuid_to_hartid_mask(const struct cpumask *in, struct cpumask *out);
> */
> #define raw_smp_processor_id() (current_thread_info()->cpu)
>
> +#if defined CONFIG_HOTPLUG_CPU
> +int __cpu_disable(void);
> +void __cpu_die(unsigned int cpu);
> +void cpu_stop(void);
> +#else
> +#endif /* CONFIG_HOTPLUG_CPU */
> +
> #else
>
> static inline void show_ipi_stats(struct seq_file *p, int prec)
> diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
> index d77def5b4e87..6fe35a719de1 100644
> --- a/arch/riscv/kernel/Makefile
> +++ b/arch/riscv/kernel/Makefile
> @@ -43,5 +43,6 @@ obj-$(CONFIG_PERF_EVENTS) += perf_event.o
> obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o
> obj-$(CONFIG_HAVE_PERF_REGS) += perf_regs.o
> obj-$(CONFIG_RISCV_SBI) += sbi.o
> +obj-$(CONFIG_HOTPLUG_CPU) += cpu-hotplug.o
>
> clean:
> diff --git a/arch/riscv/kernel/cpu-hotplug.c b/arch/riscv/kernel/cpu-hotplug.c
> new file mode 100644
> index 000000000000..835b0747803e
> --- /dev/null
> +++ b/arch/riscv/kernel/cpu-hotplug.c
> @@ -0,0 +1,84 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 Western Digital Corporation or its affiliates.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/mm.h>
> +#include <linux/sched.h>
> +#include <linux/err.h>
> +#include <linux/irq.h>
> +#include <linux/cpu.h>
> +#include <linux/sched/hotplug.h>
> +#include <asm/irq.h>
> +#include <asm/cpu_ops.h>
> +#include <asm/sbi.h>
> +
> +void cpu_stop(void);
> +bool can_hotplug_cpu(void)
> +{
> + return true;
> +}
> +
> +void arch_cpu_idle_dead(void)
> +{
> + cpu_stop();
> +}
> +
> +/*
> + * __cpu_disable runs on the processor to be shutdown.
> + */
> +int __cpu_disable(void)
> +{
> + int ret = 0;
> + unsigned int cpu = smp_processor_id();
> +
> + if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_stop)
> + return -EOPNOTSUPP;
> +
> + if (cpu_ops[cpu]->cpu_disable)
> + ret = cpu_ops[cpu]->cpu_disable(cpu);
> +
> + if (ret)
> + return ret;
> +
> + remove_cpu_topology(cpu);
> + set_cpu_online(cpu, false);
> + irq_migrate_all_off_this_cpu();
> +
> + return ret;
> +}
> +
> +/*
> + * Called on the thread which is asking for a CPU to be shutdown.
> + */
> +void __cpu_die(unsigned int cpu)
> +{
> + int ret = 0;
> +
> + if (!cpu_wait_death(cpu, 5)) {
> + pr_err("CPU %u: didn't die\n", cpu);
> + return;
> + }
> + pr_notice("CPU%u: off\n", cpu);
> +
> + /* Verify from the firmware if the cpu is really stopped*/
> + if (cpu_ops[cpu]->cpu_is_stopped)
> + ret = cpu_ops[cpu]->cpu_is_stopped(cpu);
> + if (ret)
> + pr_warn("CPU%d may not have stopped: %d\n", cpu, ret);
> +}
> +
> +/*
> + * Called from the idle thread for the CPU which has been shutdown.
> + */
> +void cpu_stop(void)
> +{
> + idle_task_exit();
> +
> + (void)cpu_report_death();
> +
> + cpu_ops[smp_processor_id()]->cpu_stop();
> + /* It should never reach here */
> + BUG();
> +}
> diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c
> index 454df032066f..9b315137b945 100644
> --- a/arch/riscv/kernel/cpu_ops.c
> +++ b/arch/riscv/kernel/cpu_ops.c
> @@ -59,6 +59,34 @@ static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle)
> return rc;
> }
>
> +#ifdef CONFIG_HOTPLUG_CPU
> +static int sbi_cpu_disable(unsigned int cpuid)
> +{
> + if (!cpu_sbi_ops.cpu_stop)
> + return -EOPNOTSUPP;
> + return 0;
> +}
> +
> +static void sbi_cpu_stop(void)
> +{
> + int ret;
> +
> + ret = sbi_hsm_hart_stop();
> + pr_crit("Unable to stop the cpu %u (%d)\n", smp_processor_id(), ret);
> +}
> +
> +static int sbi_cpu_is_stopped(unsigned int cpuid)
> +{
> + int rc;
> + int hartid = cpuid_to_hartid_map(cpuid);
> +
> + rc = sbi_hsm_hart_get_status(hartid);
> +
> + if (rc == RISCV_HART_FIRMWARE_STOPPED)
> + return 0;
> + return rc;
> +}
> +#endif
> static int spinwait_cpu_start(unsigned int cpuid, struct task_struct *tidle)
> {
> int hartid = cpuid_to_hartid_map(cpuid);
> @@ -82,6 +110,11 @@ const struct cpu_operations cpu_sbi_ops = {
> .name = "sbi",
> .cpu_prepare = sbi_cpu_prepare,
> .cpu_start = sbi_cpu_start,
> +#ifdef CONFIG_HOTPLUG_CPU
> + .cpu_disable = sbi_cpu_disable,
> + .cpu_stop = sbi_cpu_stop,
> + .cpu_is_stopped = sbi_cpu_is_stopped,
> +#endif
> };
>
> const struct cpu_operations cpu_spinwait_ops = {
> @@ -90,6 +123,7 @@ const struct cpu_operations cpu_spinwait_ops = {
> .cpu_start = spinwait_cpu_start,
> };
>
> +
> int __init cpu_set_ops(int cpuid)
> {
> if (sbi_hsm_is_available())
> diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> index 8208d1109ddb..dfab3bd40f2a 100644
> --- a/arch/riscv/kernel/setup.c
> +++ b/arch/riscv/kernel/setup.c
> @@ -43,6 +43,7 @@ struct screen_info screen_info = {
> /* The lucky hart to first increment this variable will boot the other cores */
> atomic_t hart_lottery;
> unsigned long boot_cpu_hartid;
> +static DEFINE_PER_CPU(struct cpu, cpu_devices);
>
> void __init parse_dtb(void)
> {
> @@ -90,3 +91,28 @@ void __init setup_arch(char **cmdline_p)
>
> riscv_fill_hwcap();
> }
> +
> +static inline bool can_hotplug_cpu(unsigned int cpu)
> +{
> +#ifdef CONFIG_HOTPLUG_CPU
> + if (cpu_ops[cpu]->cpu_stop)
> + return true;
> +#endif
> + return false;
> +}
> +
> +static int __init topology_init(void)
> +{
> + int i;
> +
> + pr_err("%s: In\n", __func__);
Remove this pr_err()
> + for_each_possible_cpu(i) {
> + struct cpu *cpu = &per_cpu(cpu_devices, i);
> +
> + cpu->hotpluggable = can_hotplug_cpu(i);
> + register_cpu(cpu, i);
> + }
> +
> + return 0;
> +}
> +subsys_initcall(topology_init);
> --
> 2.24.0
>
Regards,
Anup
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v7 10/10] RISC-V: Support cpu hotplug
2020-01-28 5:00 ` Anup Patel
@ 2020-01-28 19:32 ` Atish Patra
0 siblings, 0 replies; 22+ messages in thread
From: Atish Patra @ 2020-01-28 19:32 UTC (permalink / raw)
To: Anup Patel
Cc: Albert Ou, Kees Cook, nickhu, Vincent Chen, Greg Kroah-Hartman,
Palmer Dabbelt, Heiko Carstens,
linux-kernel@vger.kernel.org List, Mike Rapoport, Chester Lin,
Atish Patra, Palmer Dabbelt, Geert Uytterhoeven,
Eric W. Biederman, Paul Walmsley, Greentime Hu, Thomas Gleixner,
Borislav Petkov, Abner Chang, linux-riscv, Mao Han
On Mon, Jan 27, 2020 at 9:01 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Tue, Jan 28, 2020 at 7:58 AM Atish Patra <atish.patra@wdc.com> wrote:
> >
> > This patch enable support for cpu hotplug in RISC-V. It uses SBI HSM
> > extension to online/offline any hart. As a result, the harts are
> > returned to firmware once they are offline. If the harts are brought
> > online afterwards, they re-enter Linux kernel as if a secondary hart
> > booted for the first time. All booting requirements are honored during
> > this process.
> >
> > Tested both on QEMU and HighFive Unleashed board with. Test result follows.
> >
> > ---------------------------------------------------
> > Offline cpu 2
> > ---------------------------------------------------
> > $ echo 0 > /sys/devices/system/cpu/cpu2/online
> > [ 32.828684] CPU2: off
> > $ cat /proc/cpuinfo
> > processor : 0
> > hart : 0
> > isa : rv64imafdcsu
> > mmu : sv48
> >
> > processor : 1
> > hart : 1
> > isa : rv64imafdcsu
> > mmu : sv48
> >
> > processor : 3
> > hart : 3
> > isa : rv64imafdcsu
> > mmu : sv48
> >
> > processor : 4
> > hart : 4
> > isa : rv64imafdcsu
> > mmu : sv48
> >
> > processor : 5
> > hart : 5
> > isa : rv64imafdcsu
> > mmu : sv48
> >
> > processor : 6
> > hart : 6
> > isa : rv64imafdcsu
> > mmu : sv48
> >
> > processor : 7
> > hart : 7
> > isa : rv64imafdcsu
> > mmu : sv48
> >
> > ---------------------------------------------------
> > online cpu 2
> > ---------------------------------------------------
> > $ echo 1 > /sys/devices/system/cpu/cpu2/online
> > $ cat /proc/cpuinfo
> > processor : 0
> > hart : 0
> > isa : rv64imafdcsu
> > mmu : sv48
> >
> > processor : 1
> > hart : 1
> > isa : rv64imafdcsu
> > mmu : sv48
> >
> > processor : 2
> > hart : 2
> > isa : rv64imafdcsu
> > mmu : sv48
> >
> > processor : 3
> > hart : 3
> > isa : rv64imafdcsu
> > mmu : sv48
> >
> > processor : 4
> > hart : 4
> > isa : rv64imafdcsu
> > mmu : sv48
> >
> > processor : 5
> > hart : 5
> > isa : rv64imafdcsu
> > mmu : sv48
> >
> > processor : 6
> > hart : 6
> > isa : rv64imafdcsu
> > mmu : sv48
> >
> > processor : 7
> > hart : 7
> > isa : rv64imafdcsu
> > mmu : sv48
> >
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > ---
> > arch/riscv/Kconfig | 12 ++++-
> > arch/riscv/include/asm/cpu_ops.h | 5 ++
> > arch/riscv/include/asm/smp.h | 7 +++
> > arch/riscv/kernel/Makefile | 1 +
> > arch/riscv/kernel/cpu-hotplug.c | 84 ++++++++++++++++++++++++++++++++
> > arch/riscv/kernel/cpu_ops.c | 34 +++++++++++++
> > arch/riscv/kernel/setup.c | 26 ++++++++++
> > 7 files changed, 168 insertions(+), 1 deletion(-)
> > create mode 100644 arch/riscv/kernel/cpu-hotplug.c
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 518da42be545..99fb481dc805 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -22,7 +22,6 @@ config RISCV
> > select CLONE_BACKWARDS
> > select COMMON_CLK
> > select GENERIC_CLOCKEVENTS
> > - select GENERIC_CPU_DEVICES
> > select GENERIC_IRQ_SHOW
> > select GENERIC_PCI_IOMAP
> > select GENERIC_SCHED_CLOCK
> > @@ -247,6 +246,17 @@ config NR_CPUS
> > depends on SMP
> > default "8"
> >
> > +config HOTPLUG_CPU
> > + bool "Support for hot-pluggable CPUs"
> > + depends on SMP
> > + select GENERIC_IRQ_MIGRATION
> > + help
> > +
> > + Say Y here to experiment with turning CPUs off and on. CPUs
> > + can be controlled through /sys/devices/system/cpu.
> > +
> > + Say N if you want to disable CPU hotplug.
> > +
> > choice
> > prompt "CPU Tuning"
> > default TUNE_GENERIC
> > diff --git a/arch/riscv/include/asm/cpu_ops.h b/arch/riscv/include/asm/cpu_ops.h
> > index 27e9dfee5460..d53d7086f627 100644
> > --- a/arch/riscv/include/asm/cpu_ops.h
> > +++ b/arch/riscv/include/asm/cpu_ops.h
> > @@ -23,6 +23,11 @@ struct cpu_operations {
> > int (*cpu_prepare)(unsigned int cpu);
> > int (*cpu_start)(unsigned int cpu,
> > struct task_struct *tidle);
> > +#ifdef CONFIG_HOTPLUG_CPU
> > + int (*cpu_disable)(unsigned int cpu);
> > + void (*cpu_stop)(void);
> > + int (*cpu_is_stopped)(unsigned int cpu);
> > +#endif
> > };
> >
> > extern const struct cpu_operations *cpu_ops[NR_CPUS];
> > diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
> > index 023f74fb8b3b..8d9c50c0f91c 100644
> > --- a/arch/riscv/include/asm/smp.h
> > +++ b/arch/riscv/include/asm/smp.h
> > @@ -43,6 +43,13 @@ void riscv_cpuid_to_hartid_mask(const struct cpumask *in, struct cpumask *out);
> > */
> > #define raw_smp_processor_id() (current_thread_info()->cpu)
> >
> > +#if defined CONFIG_HOTPLUG_CPU
> > +int __cpu_disable(void);
> > +void __cpu_die(unsigned int cpu);
> > +void cpu_stop(void);
> > +#else
> > +#endif /* CONFIG_HOTPLUG_CPU */
> > +
> > #else
> >
> > static inline void show_ipi_stats(struct seq_file *p, int prec)
> > diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
> > index d77def5b4e87..6fe35a719de1 100644
> > --- a/arch/riscv/kernel/Makefile
> > +++ b/arch/riscv/kernel/Makefile
> > @@ -43,5 +43,6 @@ obj-$(CONFIG_PERF_EVENTS) += perf_event.o
> > obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o
> > obj-$(CONFIG_HAVE_PERF_REGS) += perf_regs.o
> > obj-$(CONFIG_RISCV_SBI) += sbi.o
> > +obj-$(CONFIG_HOTPLUG_CPU) += cpu-hotplug.o
> >
> > clean:
> > diff --git a/arch/riscv/kernel/cpu-hotplug.c b/arch/riscv/kernel/cpu-hotplug.c
> > new file mode 100644
> > index 000000000000..835b0747803e
> > --- /dev/null
> > +++ b/arch/riscv/kernel/cpu-hotplug.c
> > @@ -0,0 +1,84 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2018 Western Digital Corporation or its affiliates.
> > + */
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/mm.h>
> > +#include <linux/sched.h>
> > +#include <linux/err.h>
> > +#include <linux/irq.h>
> > +#include <linux/cpu.h>
> > +#include <linux/sched/hotplug.h>
> > +#include <asm/irq.h>
> > +#include <asm/cpu_ops.h>
> > +#include <asm/sbi.h>
> > +
> > +void cpu_stop(void);
> > +bool can_hotplug_cpu(void)
> > +{
> > + return true;
> > +}
> > +
> > +void arch_cpu_idle_dead(void)
> > +{
> > + cpu_stop();
> > +}
> > +
> > +/*
> > + * __cpu_disable runs on the processor to be shutdown.
> > + */
> > +int __cpu_disable(void)
> > +{
> > + int ret = 0;
> > + unsigned int cpu = smp_processor_id();
> > +
> > + if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_stop)
> > + return -EOPNOTSUPP;
> > +
> > + if (cpu_ops[cpu]->cpu_disable)
> > + ret = cpu_ops[cpu]->cpu_disable(cpu);
> > +
> > + if (ret)
> > + return ret;
> > +
> > + remove_cpu_topology(cpu);
> > + set_cpu_online(cpu, false);
> > + irq_migrate_all_off_this_cpu();
> > +
> > + return ret;
> > +}
> > +
> > +/*
> > + * Called on the thread which is asking for a CPU to be shutdown.
> > + */
> > +void __cpu_die(unsigned int cpu)
> > +{
> > + int ret = 0;
> > +
> > + if (!cpu_wait_death(cpu, 5)) {
> > + pr_err("CPU %u: didn't die\n", cpu);
> > + return;
> > + }
> > + pr_notice("CPU%u: off\n", cpu);
> > +
> > + /* Verify from the firmware if the cpu is really stopped*/
> > + if (cpu_ops[cpu]->cpu_is_stopped)
> > + ret = cpu_ops[cpu]->cpu_is_stopped(cpu);
> > + if (ret)
> > + pr_warn("CPU%d may not have stopped: %d\n", cpu, ret);
> > +}
> > +
> > +/*
> > + * Called from the idle thread for the CPU which has been shutdown.
> > + */
> > +void cpu_stop(void)
> > +{
> > + idle_task_exit();
> > +
> > + (void)cpu_report_death();
> > +
> > + cpu_ops[smp_processor_id()]->cpu_stop();
> > + /* It should never reach here */
> > + BUG();
> > +}
> > diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c
> > index 454df032066f..9b315137b945 100644
> > --- a/arch/riscv/kernel/cpu_ops.c
> > +++ b/arch/riscv/kernel/cpu_ops.c
> > @@ -59,6 +59,34 @@ static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle)
> > return rc;
> > }
> >
> > +#ifdef CONFIG_HOTPLUG_CPU
> > +static int sbi_cpu_disable(unsigned int cpuid)
> > +{
> > + if (!cpu_sbi_ops.cpu_stop)
> > + return -EOPNOTSUPP;
> > + return 0;
> > +}
> > +
> > +static void sbi_cpu_stop(void)
> > +{
> > + int ret;
> > +
> > + ret = sbi_hsm_hart_stop();
> > + pr_crit("Unable to stop the cpu %u (%d)\n", smp_processor_id(), ret);
> > +}
> > +
> > +static int sbi_cpu_is_stopped(unsigned int cpuid)
> > +{
> > + int rc;
> > + int hartid = cpuid_to_hartid_map(cpuid);
> > +
> > + rc = sbi_hsm_hart_get_status(hartid);
> > +
> > + if (rc == RISCV_HART_FIRMWARE_STOPPED)
> > + return 0;
> > + return rc;
> > +}
> > +#endif
> > static int spinwait_cpu_start(unsigned int cpuid, struct task_struct *tidle)
> > {
> > int hartid = cpuid_to_hartid_map(cpuid);
> > @@ -82,6 +110,11 @@ const struct cpu_operations cpu_sbi_ops = {
> > .name = "sbi",
> > .cpu_prepare = sbi_cpu_prepare,
> > .cpu_start = sbi_cpu_start,
> > +#ifdef CONFIG_HOTPLUG_CPU
> > + .cpu_disable = sbi_cpu_disable,
> > + .cpu_stop = sbi_cpu_stop,
> > + .cpu_is_stopped = sbi_cpu_is_stopped,
> > +#endif
> > };
> >
> > const struct cpu_operations cpu_spinwait_ops = {
> > @@ -90,6 +123,7 @@ const struct cpu_operations cpu_spinwait_ops = {
> > .cpu_start = spinwait_cpu_start,
> > };
> >
> > +
> > int __init cpu_set_ops(int cpuid)
> > {
> > if (sbi_hsm_is_available())
> > diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> > index 8208d1109ddb..dfab3bd40f2a 100644
> > --- a/arch/riscv/kernel/setup.c
> > +++ b/arch/riscv/kernel/setup.c
> > @@ -43,6 +43,7 @@ struct screen_info screen_info = {
> > /* The lucky hart to first increment this variable will boot the other cores */
> > atomic_t hart_lottery;
> > unsigned long boot_cpu_hartid;
> > +static DEFINE_PER_CPU(struct cpu, cpu_devices);
> >
> > void __init parse_dtb(void)
> > {
> > @@ -90,3 +91,28 @@ void __init setup_arch(char **cmdline_p)
> >
> > riscv_fill_hwcap();
> > }
> > +
> > +static inline bool can_hotplug_cpu(unsigned int cpu)
> > +{
> > +#ifdef CONFIG_HOTPLUG_CPU
> > + if (cpu_ops[cpu]->cpu_stop)
> > + return true;
> > +#endif
> > + return false;
> > +}
> > +
> > +static int __init topology_init(void)
> > +{
> > + int i;
> > +
> > + pr_err("%s: In\n", __func__);
>
> Remove this pr_err()
>
Oops. My bad. I forgot to remove this.
> > + for_each_possible_cpu(i) {
> > + struct cpu *cpu = &per_cpu(cpu_devices, i);
> > +
> > + cpu->hotpluggable = can_hotplug_cpu(i);
> > + register_cpu(cpu, i);
> > + }
> > +
> > + return 0;
> > +}
> > +subsys_initcall(topology_init);
> > --
> > 2.24.0
> >
>
> Regards,
> Anup
>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 22+ messages in thread