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[92.110.144.95]) by smtp.gmail.com with ESMTPSA id f11sm3863972wml.3.2020.02.20.02.48.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 20 Feb 2020 02:48:13 -0800 (PST) Date: Thu, 20 Feb 2020 11:48:11 +0100 From: "Wladimir J. van der Laan" To: Sean Anderson Subject: Re: [PATCH 08/10] riscv: Add Kendryte K210 device tree Message-ID: <20200220104811.eb5goi52qrft74vj@aurora.visucore.com> References: <19e78a77-4b7f-a057-eb6e-7384f3fc67c1@gmail.com> <8108cb8e-a909-24b0-f1c4-24a5bebf4e65@gmail.com> <20200219090612.7onbaoygy6waumnw@aurora.visucore.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200220_024816_224455_0A5DE866 X-CRM114-Status: GOOD ( 10.00 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Carlos Eduardo de Paula , Anup Patel , Damien Le Moal , Palmer Dabbelt , Paul Walmsley , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org Archived-At: List-Archive: > > BTW speaking of which, does anyone know what's up with the K210's DMA > > controller? It looks like it can only transfer 32-bit values from and to > > peripherals? At least the kendryte-standalone-sdk goes to great lengths to > > first allocate a 32-bit buffer then manually copy it to say, bytes or 16-bit > > words. Seems quite a silly workaround with a lot of overhead. > > Do you have a link to that section? It's not really one section but all over the place in all clients of the DMA. See for example the SPI here: https://github.com/kendryte/kendryte-standalone-sdk/blob/develop/lib/drivers/spi.c#L372 Or serial (this one tripped me up): https://github.com/kendryte/kendryte-standalone-sdk/blob/develop/lib/drivers/uart.c#L265 https://github.com/kendryte/kendryte-standalone-sdk/blob/develop/lib/drivers/uart.c#L163 One can fairly reliably find them by looking for 'malloc' in the drivers. A few months back I did some experiments with different values for transfer sizes and such and wasn't able to get the DMA controller to do this, myself. The "FIX_CACHE" define is new, BTW. They don't DMA directly from/to cached memory anymore but use an intermediate copy in uncached special I/O memory in the 4xxxxxxx range. I haven't had problems with e.g. manually DMAing to the screen through SPI myself but there might be a coherency edge case (their commit messages are not exactly enlightening). Kind regards, Wladimir