Linux-RISC-V Archive on lore.kernel.org
 help / color / Atom feed
* [PATCH v2 0/3] convert sifive's prci, plic and pwm bindings to yaml
@ 2020-09-29 15:32 Sagar Kadam
  2020-09-29 15:32 ` [PATCH v2 1/3] dt-bindings: fu540: prci: convert PRCI bindings to json-schema Sagar Kadam
                   ` (2 more replies)
  0 siblings, 3 replies; 8+ messages in thread
From: Sagar Kadam @ 2020-09-29 15:32 UTC (permalink / raw)
  To: linux-clk
  Cc: devicetree, aou, jason, linux-pwm, sboyd, maz, mturquette,
	u.kleine-koenig, linux-kernel, yash.shah, robh+dt, palmer,
	Sagar Kadam, paul.walmsley, thierry.reding, linux-riscv,
	lee.jones, tglx

The prci, plic and pwm controller bindings are in txt format. Here,
we convert them to yaml format.

These patches are tested on commit a1b8638ba132 ("Linux 5.9-rc7")
I have added the log of dt_binding_check for these IP block's
on 5.9-rc7 kernel here [1] in case someone want's to refer it.

[1] https://paste.ubuntu.com/p/7BRfJXckkV/

Additionally the default log of dt_binding_check on linux-5.9-rc7 without
these patches can be found here [2].

[2] https://paste.ubuntu.com/p/ys5XNn38VP/

Patch History:
============================
v2:
-Incorporated suggestions as per discussion from here [3]
 [3] https://patchwork.kernel.org/cover/11769499/
-Rebased patches to 5.9-rc7

V1: Base version.

Sagar Kadam (3):
  dt-bindings: fu540: prci: convert PRCI bindings to json-schema
  dt-bindings: riscv: convert plic bindings to json-schema
  dt-bindings: riscv: convert pwm bindings to json-schema

 .../bindings/clock/sifive/fu540-prci.txt           | 46 ----------
 .../bindings/clock/sifive/fu540-prci.yaml          | 60 +++++++++++++
 .../interrupt-controller/sifive,plic-1.0.0.txt     | 58 -------------
 .../interrupt-controller/sifive,plic-1.0.0.yaml    | 97 ++++++++++++++++++++++
 .../devicetree/bindings/pwm/pwm-sifive.txt         | 33 --------
 .../devicetree/bindings/pwm/pwm-sifive.yaml        | 69 +++++++++++++++
 6 files changed, 226 insertions(+), 137 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt
 create mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
 delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt
 create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.yaml

-- 
2.7.4


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v2 1/3] dt-bindings: fu540: prci: convert PRCI bindings to json-schema
  2020-09-29 15:32 [PATCH v2 0/3] convert sifive's prci, plic and pwm bindings to yaml Sagar Kadam
@ 2020-09-29 15:32 ` Sagar Kadam
  2020-10-06 18:42   ` Rob Herring
  2020-09-29 15:32 ` [PATCH v2 2/3] dt-bindings: riscv: convert plic " Sagar Kadam
  2020-09-29 15:32 ` [PATCH v2 3/3] dt-bindings: riscv: convert pwm " Sagar Kadam
  2 siblings, 1 reply; 8+ messages in thread
From: Sagar Kadam @ 2020-09-29 15:32 UTC (permalink / raw)
  To: linux-clk
  Cc: devicetree, aou, jason, linux-pwm, sboyd, maz, mturquette,
	u.kleine-koenig, linux-kernel, yash.shah, robh+dt, palmer,
	Sagar Kadam, paul.walmsley, thierry.reding, linux-riscv,
	lee.jones, tglx

FU540-C000 SoC from SiFive has a PRCI block, here we convert
the device tree bindings from txt to YAML.

Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com>
---
 .../bindings/clock/sifive/fu540-prci.txt           | 46 -----------------
 .../bindings/clock/sifive/fu540-prci.yaml          | 60 ++++++++++++++++++++++
 2 files changed, 60 insertions(+), 46 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt
 create mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml

diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt
deleted file mode 100644
index 349808f..0000000
--- a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-SiFive FU540 PRCI bindings
-
-On the FU540 family of SoCs, most system-wide clock and reset integration
-is via the PRCI IP block.
-
-Required properties:
-- compatible: Should be "sifive,<chip>-prci".  Only one value is
-	supported: "sifive,fu540-c000-prci"
-- reg: Should describe the PRCI's register target physical address region
-- clocks: Should point to the hfclk device tree node and the rtcclk
-          device tree node.  The RTC clock here is not a time-of-day clock,
-	  but is instead a high-stability clock source for system timers
-	  and cycle counters.
-- #clock-cells: Should be <1>
-
-The clock consumer should specify the desired clock via the clock ID
-macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
-These macros begin with PRCI_CLK_.
-
-The hfclk and rtcclk nodes are required, and represent physical
-crystals or resonators located on the PCB.  These nodes should be present
-underneath /, rather than /soc.
-
-Examples:
-
-/* under /, in PCB-specific DT data */
-hfclk: hfclk {
-	#clock-cells = <0>;
-	compatible = "fixed-clock";
-	clock-frequency = <33333333>;
-	clock-output-names = "hfclk";
-};
-rtcclk: rtcclk {
-	#clock-cells = <0>;
-	compatible = "fixed-clock";
-	clock-frequency = <1000000>;
-	clock-output-names = "rtcclk";
-};
-
-/* under /soc, in SoC-specific DT data */
-prci: clock-controller@10000000 {
-	compatible = "sifive,fu540-c000-prci";
-	reg = <0x0 0x10000000 0x0 0x1000>;
-	clocks = <&hfclk>, <&rtcclk>;
-	#clock-cells = <1>;
-};
diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml
new file mode 100644
index 0000000..c3be1b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 SiFive, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
+
+maintainers:
+  - Sagar Kadam <sagar.kadam@sifive.com>
+  - Paul Walmsley  <paul.walmsley@sifive.com>
+
+description:
+  On the FU540 family of SoCs, most system-wide clock and reset integration
+  is via the PRCI IP block.
+  The clock consumer should specify the desired clock via the clock ID
+  macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
+  These macros begin with PRCI_CLK_.
+
+  The hfclk and rtcclk nodes are required, and represent physical
+  crystals or resonators located on the PCB.  These nodes should be present
+  underneath /, rather than /soc.
+
+properties:
+  compatible:
+    const: sifive,fu540-c000-prci
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: high frequency clock.
+      - description: RTL clock.
+
+  clock-names:
+    items:
+      - const: hfclk
+      - const: rtcclk
+
+  "#clock-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    prci: clock-controller@10000000 {
+      compatible = "sifive,fu540-c000-prci";
+      reg = <0x10000000 0x1000>;
+      clocks = <&hfclk>, <&rtcclk>;
+      #clock-cells = <1>;
+    };
-- 
2.7.4


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v2 2/3] dt-bindings: riscv: convert plic bindings to json-schema
  2020-09-29 15:32 [PATCH v2 0/3] convert sifive's prci, plic and pwm bindings to yaml Sagar Kadam
  2020-09-29 15:32 ` [PATCH v2 1/3] dt-bindings: fu540: prci: convert PRCI bindings to json-schema Sagar Kadam
@ 2020-09-29 15:32 ` Sagar Kadam
  2020-10-06 18:44   ` Rob Herring
  2020-09-29 15:32 ` [PATCH v2 3/3] dt-bindings: riscv: convert pwm " Sagar Kadam
  2 siblings, 1 reply; 8+ messages in thread
From: Sagar Kadam @ 2020-09-29 15:32 UTC (permalink / raw)
  To: linux-clk
  Cc: devicetree, aou, jason, linux-pwm, sboyd, maz, mturquette,
	u.kleine-koenig, linux-kernel, yash.shah, robh+dt, palmer,
	Sagar Kadam, paul.walmsley, thierry.reding, linux-riscv,
	lee.jones, tglx

Convert device tree bindings for SiFive's PLIC to YAML format

Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com>
---
 .../interrupt-controller/sifive,plic-1.0.0.txt     | 58 -------------
 .../interrupt-controller/sifive,plic-1.0.0.yaml    | 97 ++++++++++++++++++++++
 2 files changed, 97 insertions(+), 58 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt
deleted file mode 100644
index 6adf7a6..0000000
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-SiFive Platform-Level Interrupt Controller (PLIC)
--------------------------------------------------
-
-SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
-(PLIC) high-level specification in the RISC-V Privileged Architecture
-specification.  The PLIC connects all external interrupts in the system to all
-hart contexts in the system, via the external interrupt source in each hart.
-
-A hart context is a privilege mode in a hardware execution thread.  For example,
-in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
-privilege modes per hart; machine mode and supervisor mode.
-
-Each interrupt can be enabled on per-context basis.  Any context can claim
-a pending enabled interrupt and then release it once it has been handled.
-
-Each interrupt has a configurable priority.  Higher priority interrupts are
-serviced first.  Each context can specify a priority threshold. Interrupts
-with priority below this threshold will not cause the PLIC to raise its
-interrupt line leading to the context.
-
-While the PLIC supports both edge-triggered and level-triggered interrupts,
-interrupt handlers are oblivious to this distinction and therefore it is not
-specified in the PLIC device-tree binding.
-
-While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
-"sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
-contains a specific memory layout, which is documented in chapter 8 of the
-SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
-
-Required properties:
-- compatible : "sifive,plic-1.0.0" and a string identifying the actual
-  detailed implementation in case that specific bugs need to be worked around.
-- #address-cells : should be <0> or more.
-- #interrupt-cells : should be <1> or more.
-- interrupt-controller : Identifies the node as an interrupt controller.
-- reg : Should contain 1 register range (address and length).
-- interrupts-extended : Specifies which contexts are connected to the PLIC,
-  with "-1" specifying that a context is not present.  Each node pointed
-  to should be a riscv,cpu-intc node, which has a riscv node as parent.
-- riscv,ndev: Specifies how many external interrupts are supported by
-  this controller.
-
-Example:
-
-	plic: interrupt-controller@c000000 {
-		#address-cells = <0>;
-		#interrupt-cells = <1>;
-		compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic";
-		interrupt-controller;
-		interrupts-extended = <
-			&cpu0-intc 11
-			&cpu1-intc 11 &cpu1-intc 9
-			&cpu2-intc 11 &cpu2-intc 9
-			&cpu3-intc 11 &cpu3-intc 9
-			&cpu4-intc 11 &cpu4-intc 9>;
-		reg = <0xc000000 0x4000000>;
-		riscv,ndev = <10>;
-	};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
new file mode 100644
index 0000000..b9a61c9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+# Copyright (C) 2020 SiFive, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive Platform-Level Interrupt Controller (PLIC)
+
+description:
+  SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
+  (PLIC) high-level specification in the RISC-V Privileged Architecture
+  specification. The PLIC connects all external interrupts in the system to all
+  hart contexts in the system, via the external interrupt source in each hart.
+
+  A hart context is a privilege mode in a hardware execution thread. For example,
+  in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
+  privilege modes per hart; machine mode and supervisor mode.
+
+  Each interrupt can be enabled on per-context basis. Any context can claim
+  a pending enabled interrupt and then release it once it has been handled.
+
+  Each interrupt has a configurable priority. Higher priority interrupts are
+  serviced first.  Each context can specify a priority threshold. Interrupts
+  with priority below this threshold will not cause the PLIC to raise its
+  interrupt line leading to the context.
+
+  While the PLIC supports both edge-triggered and level-triggered interrupts,
+  interrupt handlers are oblivious to this distinction and therefore it is not
+  specified in the PLIC device-tree binding.
+
+  While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
+  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
+  contains a specific memory layout, which is documented in chapter 8 of the
+  SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
+
+maintainers:
+  - Sagar Kadam <sagar.kadam@sifive.com>
+  - Paul Walmsley  <paul.walmsley@sifive.com>
+  - Palmer Dabbelt <palmer@dabbelt.com>
+
+properties:
+  compatible:
+    items:
+      - const: sifive,fu540-c000-plic
+      - const: sifive,plic-1.0.0
+
+  reg:
+    maxItems: 1
+
+  '#address-cells':
+    const: 0
+
+  '#interrupt-cells':
+    const: 1
+
+  interrupt-controller: true
+
+  interrupts-extended:
+    minItems: 1
+    description:
+      Specifies which contexts are connected to the PLIC, with "-1" specifying
+      that a context is not present. Each node pointed to should be a
+      riscv,cpu-intc node, which has a riscv node as parent.
+
+  riscv,ndev:
+    $ref: "/schemas/types.yaml#/definitions/uint32"
+    description:
+      Specifies how many external interrupts are supported by this controller.
+
+required:
+  - compatible
+  - '#address-cells'
+  - '#interrupt-cells'
+  - interrupt-controller
+  - reg
+  - interrupts-extended
+  - riscv,ndev
+
+additionalProperties: false
+
+examples:
+  - |
+    plic: interrupt-controller@c000000 {
+      #address-cells = <0>;
+      #interrupt-cells = <1>;
+      compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
+      interrupt-controller;
+      interrupts-extended = <
+        &cpu0_intc 11
+        &cpu1_intc 11 &cpu1_intc 9
+        &cpu2_intc 11 &cpu2_intc 9
+        &cpu3_intc 11 &cpu3_intc 9
+        &cpu4_intc 11 &cpu4_intc 9>;
+      reg = <0xc000000 0x4000000>;
+      riscv,ndev = <10>;
+    };
-- 
2.7.4


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v2 3/3] dt-bindings: riscv: convert pwm bindings to json-schema
  2020-09-29 15:32 [PATCH v2 0/3] convert sifive's prci, plic and pwm bindings to yaml Sagar Kadam
  2020-09-29 15:32 ` [PATCH v2 1/3] dt-bindings: fu540: prci: convert PRCI bindings to json-schema Sagar Kadam
  2020-09-29 15:32 ` [PATCH v2 2/3] dt-bindings: riscv: convert plic " Sagar Kadam
@ 2020-09-29 15:32 ` Sagar Kadam
  2020-10-06 18:45   ` Rob Herring
  2 siblings, 1 reply; 8+ messages in thread
From: Sagar Kadam @ 2020-09-29 15:32 UTC (permalink / raw)
  To: linux-clk
  Cc: devicetree, aou, jason, linux-pwm, sboyd, maz, mturquette,
	u.kleine-koenig, linux-kernel, yash.shah, robh+dt, palmer,
	Sagar Kadam, paul.walmsley, thierry.reding, linux-riscv,
	lee.jones, tglx

Convert device tree bindings for SiFive's PWM controller to YAML
format.

Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com>
---
 .../devicetree/bindings/pwm/pwm-sifive.txt         | 33 -----------
 .../devicetree/bindings/pwm/pwm-sifive.yaml        | 69 ++++++++++++++++++++++
 2 files changed, 69 insertions(+), 33 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt
 create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.yaml

diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
deleted file mode 100644
index 3d1dd7b0..0000000
--- a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-SiFive PWM controller
-
-Unlike most other PWM controllers, the SiFive PWM controller currently only
-supports one period for all channels in the PWM. All PWMs need to run at
-the same period. The period also has significant restrictions on the values
-it can achieve, which the driver rounds to the nearest achievable period.
-PWM RTL that corresponds to the IP block version numbers can be found
-here:
-
-https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
-
-Required properties:
-- compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>".
-  Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive
-  PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
-  SiFive PWM v0 IP block with no chip integration tweaks.
-  Please refer to sifive-blocks-ip-versioning.txt for details.
-- reg: physical base address and length of the controller's registers
-- clocks: Should contain a clock identifier for the PWM's parent clock.
-- #pwm-cells: Should be 3. See pwm.yaml in this directory
-  for a description of the cell format.
-- interrupts: one interrupt per PWM channel
-
-Examples:
-
-pwm:  pwm@10020000 {
-	compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
-	reg = <0x0 0x10020000 0x0 0x1000>;
-	clocks = <&tlclk>;
-	interrupt-parent = <&plic>;
-	interrupts = <42 43 44 45>;
-	#pwm-cells = <3>;
-};
diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
new file mode 100644
index 0000000..5ac2527
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 SiFive, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive PWM controller
+
+maintainers:
+  - Yash Shah <yash.shah@sifive.com>
+  - Sagar Kadam <sagar.kadam@sifive.com>
+  - Paul Walmsley <paul.walmsley@sifive.com>
+
+description:
+  Unlike most other PWM controllers, the SiFive PWM controller currently
+  only supports one period for all channels in the PWM. All PWMs need to
+  run at the same period. The period also has significant restrictions on
+  the values it can achieve, which the driver rounds to the nearest
+  achievable period. PWM RTL that corresponds to the IP block version
+  numbers can be found here -
+
+  https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
+
+properties:
+  compatible:
+    items:
+      - const: sifive,fu540-c000-pwm
+      - const: sifive,pwm0
+    description:
+      Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
+      compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0
+      as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
+      SiFive PWM v0 IP block with no chip integration tweaks.
+      Please refer to sifive-blocks-ip-versioning.txt for details.
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  "#pwm-cells":
+    const: 3
+
+  interrupts:
+    maxItems: 4
+    description:
+      Each PWM instance in FU540-C000 has 4 comparators. One interrupt per comparator.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - "#pwm-cells"
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    pwm:  pwm@10020000 {
+      compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
+      reg = <0x10020000 0x1000>;
+      clocks = <&tlclk>;
+      interrupt-parent = <&plic>;
+      interrupts = <42>, <43>, <44>, <45>;
+      #pwm-cells = <3>;
+    };
-- 
2.7.4


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v2 1/3] dt-bindings: fu540: prci: convert PRCI bindings to json-schema
  2020-09-29 15:32 ` [PATCH v2 1/3] dt-bindings: fu540: prci: convert PRCI bindings to json-schema Sagar Kadam
@ 2020-10-06 18:42   ` Rob Herring
  2020-10-07  3:38     ` Sagar Kadam
  0 siblings, 1 reply; 8+ messages in thread
From: Rob Herring @ 2020-10-06 18:42 UTC (permalink / raw)
  To: Sagar Kadam
  Cc: linux-pwm, aou, jason, devicetree, sboyd, maz, mturquette,
	paul.walmsley, linux-kernel, robh+dt, linux-clk, yash.shah,
	thierry.reding, palmer, u.kleine-koenig, linux-riscv, lee.jones,
	tglx

On Tue, 29 Sep 2020 21:02:09 +0530, Sagar Kadam wrote:
> FU540-C000 SoC from SiFive has a PRCI block, here we convert
> the device tree bindings from txt to YAML.
> 
> Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com>
> ---
>  .../bindings/clock/sifive/fu540-prci.txt           | 46 -----------------
>  .../bindings/clock/sifive/fu540-prci.yaml          | 60 ++++++++++++++++++++++
>  2 files changed, 60 insertions(+), 46 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt
>  create mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml
> 

Applied, thanks!

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v2 2/3] dt-bindings: riscv: convert plic bindings to json-schema
  2020-09-29 15:32 ` [PATCH v2 2/3] dt-bindings: riscv: convert plic " Sagar Kadam
@ 2020-10-06 18:44   ` Rob Herring
  0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2020-10-06 18:44 UTC (permalink / raw)
  To: Sagar Kadam
  Cc: devicetree, aou, tglx, jason, linux-pwm, sboyd, maz, mturquette,
	u.kleine-koenig, linux-kernel, yash.shah, robh+dt,
	thierry.reding, paul.walmsley, palmer, linux-riscv, lee.jones,
	linux-clk

On Tue, 29 Sep 2020 21:02:10 +0530, Sagar Kadam wrote:
> Convert device tree bindings for SiFive's PLIC to YAML format
> 
> Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com>
> ---
>  .../interrupt-controller/sifive,plic-1.0.0.txt     | 58 -------------
>  .../interrupt-controller/sifive,plic-1.0.0.yaml    | 97 ++++++++++++++++++++++
>  2 files changed, 97 insertions(+), 58 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> 

Applied, thanks!

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v2 3/3] dt-bindings: riscv: convert pwm bindings to json-schema
  2020-09-29 15:32 ` [PATCH v2 3/3] dt-bindings: riscv: convert pwm " Sagar Kadam
@ 2020-10-06 18:45   ` Rob Herring
  0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2020-10-06 18:45 UTC (permalink / raw)
  To: Sagar Kadam
  Cc: linux-riscv, devicetree, aou, jason, linux-pwm, sboyd, maz,
	mturquette, u.kleine-koenig, linux-kernel, robh+dt, yash.shah,
	thierry.reding, palmer, paul.walmsley, tglx, lee.jones,
	linux-clk

On Tue, 29 Sep 2020 21:02:11 +0530, Sagar Kadam wrote:
> Convert device tree bindings for SiFive's PWM controller to YAML
> format.
> 
> Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com>
> ---
>  .../devicetree/bindings/pwm/pwm-sifive.txt         | 33 -----------
>  .../devicetree/bindings/pwm/pwm-sifive.yaml        | 69 ++++++++++++++++++++++
>  2 files changed, 69 insertions(+), 33 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt
>  create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
> 

Applied, thanks!

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 8+ messages in thread

* RE: [PATCH v2 1/3] dt-bindings: fu540: prci: convert PRCI bindings to json-schema
  2020-10-06 18:42   ` Rob Herring
@ 2020-10-07  3:38     ` Sagar Kadam
  0 siblings, 0 replies; 8+ messages in thread
From: Sagar Kadam @ 2020-10-07  3:38 UTC (permalink / raw)
  To: Rob Herring
  Cc: linux-pwm, aou, jason, devicetree, sboyd, maz, mturquette,
	Paul Walmsley ( Sifive),
	linux-kernel, robh+dt, linux-clk, Yash Shah, thierry.reding,
	palmer, u.kleine-koenig, linux-riscv, lee.jones, tglx


> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Wednesday, October 7, 2020 12:13 AM
> To: Sagar Kadam <sagar.kadam@openfive.com>
> Cc: aou@eecs.berkeley.edu; linux-riscv@lists.infradead.org;
> tglx@linutronix.de; linux-pwm@vger.kernel.org; palmer@dabbelt.com;
> jason@lakedaemon.net; Yash Shah <yash.shah@openfive.com>;
> thierry.reding@gmail.com; lee.jones@linaro.org; u.kleine-
> koenig@pengutronix.de; robh+dt@kernel.org; Paul Walmsley ( Sifive)
> <paul.walmsley@sifive.com>; linux-kernel@vger.kernel.org; linux-
> clk@vger.kernel.org; maz@kernel.org; mturquette@baylibre.com;
> devicetree@vger.kernel.org; sboyd@kernel.org
> Subject: Re: [PATCH v2 1/3] dt-bindings: fu540: prci: convert PRCI bindings to
> json-schema
> 
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
> 
> On Tue, 29 Sep 2020 21:02:09 +0530, Sagar Kadam wrote:
> > FU540-C000 SoC from SiFive has a PRCI block, here we convert the
> > device tree bindings from txt to YAML.
> >
> > Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com>
> > ---
> >  .../bindings/clock/sifive/fu540-prci.txt           | 46 -----------------
> >  .../bindings/clock/sifive/fu540-prci.yaml          | 60
> ++++++++++++++++++++++
> >  2 files changed, 60 insertions(+), 46 deletions(-)  delete mode
> > 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt
> >  create mode 100644
> > Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml
> >
> 
> Applied, thanks!

Thanks Rob for applying these patches.

BR,
Sagar

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, back to index

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-29 15:32 [PATCH v2 0/3] convert sifive's prci, plic and pwm bindings to yaml Sagar Kadam
2020-09-29 15:32 ` [PATCH v2 1/3] dt-bindings: fu540: prci: convert PRCI bindings to json-schema Sagar Kadam
2020-10-06 18:42   ` Rob Herring
2020-10-07  3:38     ` Sagar Kadam
2020-09-29 15:32 ` [PATCH v2 2/3] dt-bindings: riscv: convert plic " Sagar Kadam
2020-10-06 18:44   ` Rob Herring
2020-09-29 15:32 ` [PATCH v2 3/3] dt-bindings: riscv: convert pwm " Sagar Kadam
2020-10-06 18:45   ` Rob Herring

Linux-RISC-V Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-riscv/0 linux-riscv/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-riscv linux-riscv/ https://lore.kernel.org/linux-riscv \
		linux-riscv@lists.infradead.org
	public-inbox-index linux-riscv

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.infradead.lists.linux-riscv


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git