* [RFC PATCH 0/3] Add Microchip PolarFire Soc Support
@ 2020-10-28 23:27 Atish Patra
2020-10-28 23:27 ` [RFC PATCH 1/3] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra
` (3 more replies)
0 siblings, 4 replies; 38+ messages in thread
From: Atish Patra @ 2020-10-28 23:27 UTC (permalink / raw)
To: linux-kernel
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
Atish Patra, Rob Herring, Alistair Francis, Paul Walmsley,
Palmer Dabbelt, linux-riscv, padmarao.begari
This series adds minimal support for Microchip Polar Fire Soc Icicle kit.
It is rebased on v5.10-rc1 and depends on clock support.
Only MMC and ethernet drivers are enabled via this series.
The idea here is to add the foundational patches so that other drivers
can be added to on top of this.
This series has been tested on Qemu and Polar Fire Soc Icicle kit.
The following qemu series is necessary to test it on Qemu.
The series can also be found at the following github repo.
I noticed the latest version of mmc driver[2] hangs on the board with
the latest clock driver. That's why, I have tested with the old clock
driver available in the above github repo.
[1] https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg08582.html
[2] https://www.spinics.net/lists/devicetree/msg383626.html
Atish Patra (3):
RISC-V: Add Microchip PolarFire SoC kconfig option
RISC-V: Initial DTS for Microchip ICICLE board
RISC-V: Enable Microchip PolarFire ICICLE SoC
arch/riscv/Kconfig.socs | 7 +
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/microchip/Makefile | 2 +
.../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
arch/riscv/configs/defconfig | 4 +
5 files changed, 327 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/Makefile
create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
--
2.25.1
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^ permalink raw reply [flat|nested] 38+ messages in thread
* [RFC PATCH 1/3] RISC-V: Add Microchip PolarFire SoC kconfig option
2020-10-28 23:27 [RFC PATCH 0/3] Add Microchip PolarFire Soc Support Atish Patra
@ 2020-10-28 23:27 ` Atish Patra
2020-10-30 9:08 ` Anup Patel
` (2 more replies)
2020-10-28 23:27 ` [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra
` (2 subsequent siblings)
3 siblings, 3 replies; 38+ messages in thread
From: Atish Patra @ 2020-10-28 23:27 UTC (permalink / raw)
To: linux-kernel
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
Atish Patra, Rob Herring, Alistair Francis, Paul Walmsley,
Palmer Dabbelt, linux-riscv, padmarao.begari
Add Microchip PolarFire kconfig option which selects SoC specific
and common drivers that is required for this SoC.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
arch/riscv/Kconfig.socs | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 8a55f6156661..74d07250ecc5 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -22,6 +22,13 @@ config SOC_VIRT
help
This enables support for QEMU Virt Machine.
+config SOC_MICROCHIP_POLARFIRE
+ bool "Microchip PolarFire SoCs"
+ select MCHP_CLK_PFSOC
+ select SIFIVE_PLIC
+ help
+ This enables support for Microchip PolarFire SoC platforms.
+
config SOC_KENDRYTE
bool "Kendryte K210 SoC"
depends on !MMU
--
2.25.1
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^ permalink raw reply related [flat|nested] 38+ messages in thread
* [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-10-28 23:27 [RFC PATCH 0/3] Add Microchip PolarFire Soc Support Atish Patra
2020-10-28 23:27 ` [RFC PATCH 1/3] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra
@ 2020-10-28 23:27 ` Atish Patra
2020-10-29 10:24 ` Ben Dooks
` (2 more replies)
2020-10-28 23:27 ` [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra
2020-11-06 7:14 ` [RFC PATCH 0/3] Add Microchip PolarFire Soc Support Palmer Dabbelt
3 siblings, 3 replies; 38+ messages in thread
From: Atish Patra @ 2020-10-28 23:27 UTC (permalink / raw)
To: linux-kernel
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
Atish Patra, Rob Herring, Alistair Francis, Paul Walmsley,
Palmer Dabbelt, linux-riscv, padmarao.begari
Add initial DTS for Microchip ICICLE board having only
essential devcies (clocks, sdhci, ethernet, serial, etc).
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/microchip/Makefile | 2 +
.../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
3 files changed, 316 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/Makefile
create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ca1f8cbd78c0..3ea94ea0a18a 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += sifive
subdir-y += kendryte
+subdir-y += microchip
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
new file mode 100644
index 000000000000..55ad77521304
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
new file mode 100644
index 000000000000..5848920af55c
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
@@ -0,0 +1,313 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ 1000000
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip PolarFire-SoC";
+ compatible = "microchip,polarfire-soc";
+
+ chosen {
+ stdout-path = &serial0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <RTCCLK_FREQ>;
+
+ cpu@0 {
+ clock-frequency = <0>;
+ compatible = "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu@1 {
+ clock-frequency = <0>;
+ compatible = "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu@2 {
+ clock-frequency = <0>;
+ compatible = "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <2>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu@3 {
+ clock-frequency = <0>;
+ compatible = "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <3>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+
+ cpu3_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu@4 {
+ clock-frequency = <0>;
+ compatible = "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <4>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+ cpu4_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x40000000>;
+ clocks = <&clkcfg 26>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ cache-controller@2010000 {
+ compatible = "sifive,fu540-c000-ccache", "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <1024>;
+ cache-size = <2097152>;
+ cache-unified;
+ interrupt-parent = <&plic>;
+ interrupts = <1 2 3>;
+ reg = <0x0 0x2010000 0x0 0x1000>;
+ };
+
+ clint@2000000 {
+ compatible = "riscv,clint0";
+ reg = <0x0 0x2000000 0x0 0xC000>;
+ interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
+ &cpu1_intc 3 &cpu1_intc 7
+ &cpu2_intc 3 &cpu2_intc 7
+ &cpu3_intc 3 &cpu3_intc 7
+ &cpu4_intc 3 &cpu4_intc 7>;
+ };
+
+ plic: interrupt-controller@c000000 {
+ #interrupt-cells = <1>;
+ compatible = "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ riscv,ndev = <53>;
+ interrupt-controller;
+ interrupts-extended = <&cpu0_intc 11
+ &cpu1_intc 11 &cpu1_intc 9
+ &cpu2_intc 11 &cpu2_intc 9
+ &cpu3_intc 11 &cpu3_intc 9
+ &cpu4_intc 11 &cpu4_intc 9>;
+ };
+
+ dma@3000000 {
+ compatible = "sifive,fu540-c000-pdma";
+ reg = <0x0 0x3000000 0x0 0x8000>;
+ interrupt-parent = <&plic>;
+ interrupts = <23 24 25 26 27 28 29 30>;
+ #dma-cells = <1>;
+ };
+
+ refclk: refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <600000000>;
+ clock-output-names = "msspllclk";
+ };
+
+ clkcfg: clkcfg@20002000 {
+ compatible = "microchip,pfsoc-clkcfg";
+ reg = <0x0 0x20002000 0x0 0x1000>;
+ reg-names = "mss_sysreg";
+ clocks = <&refclk>;
+ #clock-cells = <1>;
+ clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", "MMUART2clk", "MMUART3clk", "MMUART4clk", "SPI0clk", "SPI1clk", "I2C0clk", "I2C1clk", "CAN0clk", "CAN1clk", "USBclk", "RESERVED", "RTCclk", "QSPIclk", "GPIO0clk", "GPIO1clk", "GPIO2clk", "DDRCclk", "FIC0clk", "FIC1clk", "FIC2clk", "FIC3clk", "ATHENAclk", "CFMclk";
+ };
+
+ serial0: serial@20000000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x20000000 0x0 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupt-parent = <&plic>;
+ interrupts = <90>;
+ current-speed = <115200>;
+ clocks = <&clkcfg 8>;
+ status = "okay";
+ };
+
+ serial1: serial@20100000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x20100000 0x0 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupt-parent = <&plic>;
+ interrupts = <91>;
+ current-speed = <115200>;
+ clocks = <&clkcfg 9>;
+ status = "okay";
+ };
+
+ serial2: serial@20102000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x20102000 0x0 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupt-parent = <&plic>;
+ interrupts = <92>;
+ current-speed = <115200>;
+ clocks = <&clkcfg 10>;
+ status = "okay";
+ };
+
+ serial3: serial@20104000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x20104000 0x0 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupt-parent = <&plic>;
+ interrupts = <93>;
+ current-speed = <115200>;
+ clocks = <&clkcfg 11>;
+ status = "okay";
+ };
+
+ sdcard: sdhc@20008000 {
+ compatible = "cdns,sd4hc";
+ reg = <0x0 0x20008000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <88>;
+ pinctrl-names = "default";
+ clocks = <&clkcfg 6>;
+ bus-width = <4>;
+ disable-wp;
+ no-1-8-v;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ max-frequency = <200000000>;
+ status = "okay";
+ };
+
+ emac1: ethernet@20112000 {
+ compatible = "cdns,macb";
+ reg = <0x0 0x20112000 0x0 0x2000>;
+ interrupt-parent = <&plic>;
+ interrupts = <70 71 72 73>;
+ mac-address = [56 34 12 00 FC 00];
+ phy-mode = "sgmii";
+ clocks = <&clkcfg 5>, <&clkcfg 2>;
+ clock-names = "pclk", "hclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy1: ethernet-phy@9 {
+ reg = <9>;
+ ti,fifo-depth = <0x01>;
+ };
+ };
+
+ uio_axi_lsram@2030000000 {
+ compatible = "generic-uio";
+ reg = <0x20 0x30000000 0 0x80000000 >;
+ status = "okay";
+ };
+ };
+};
--
2.25.1
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^ permalink raw reply related [flat|nested] 38+ messages in thread
* [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC
2020-10-28 23:27 [RFC PATCH 0/3] Add Microchip PolarFire Soc Support Atish Patra
2020-10-28 23:27 ` [RFC PATCH 1/3] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra
2020-10-28 23:27 ` [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra
@ 2020-10-28 23:27 ` Atish Patra
2020-10-30 9:09 ` Anup Patel
` (2 more replies)
2020-11-06 7:14 ` [RFC PATCH 0/3] Add Microchip PolarFire Soc Support Palmer Dabbelt
3 siblings, 3 replies; 38+ messages in thread
From: Atish Patra @ 2020-10-28 23:27 UTC (permalink / raw)
To: linux-kernel
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
Atish Patra, Rob Herring, Alistair Francis, Paul Walmsley,
Palmer Dabbelt, linux-riscv, padmarao.begari
Enable Microchip PolarFire ICICLE soc config in defconfig.
It allows the default upstream kernel to boot on PolarFire ICICLE board.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
arch/riscv/configs/defconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index d222d353d86d..2660fa05451e 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -16,6 +16,7 @@ CONFIG_EXPERT=y
CONFIG_BPF_SYSCALL=y
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_VIRT=y
+CONFIG_SOC_MICROCHIP_POLARFIRE=y
CONFIG_SMP=y
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
@@ -79,6 +80,9 @@ CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_UAS=y
+CONFIG_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_MMC=y
CONFIG_MMC_SPI=y
CONFIG_RTC_CLASS=y
--
2.25.1
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^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-10-28 23:27 ` [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra
@ 2020-10-29 10:24 ` Ben Dooks
2020-10-30 7:11 ` Atish Patra
2020-11-04 2:41 ` Bin Meng
2020-10-30 9:05 ` Anup Patel
2020-11-06 7:14 ` Palmer Dabbelt
2 siblings, 2 replies; 38+ messages in thread
From: Ben Dooks @ 2020-10-29 10:24 UTC (permalink / raw)
To: Atish Patra, linux-kernel
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
Rob Herring, Alistair Francis, Paul Walmsley, Palmer Dabbelt,
linux-riscv, padmarao.begari
On 28/10/2020 23:27, Atish Patra wrote:
> Add initial DTS for Microchip ICICLE board having only
> essential devcies (clocks, sdhci, ethernet, serial, etc).
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/microchip/Makefile | 2 +
> .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
> 3 files changed, 316 insertions(+)
> create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ca1f8cbd78c0..3ea94ea0a18a 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> subdir-y += sifive
> subdir-y += kendryte
> +subdir-y += microchip
>
> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
> new file mode 100644
> index 000000000000..55ad77521304
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
> diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> new file mode 100644
> index 000000000000..5848920af55c
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> @@ -0,0 +1,313 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/* Copyright (c) 2020 Microchip Technology Inc */
> +
> +/dts-v1/;
> +
> +/* Clock frequency (in Hz) of the rtcclk */
> +#define RTCCLK_FREQ 1000000
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + model = "Microchip PolarFire-SoC";
> + compatible = "microchip,polarfire-soc";
> +
> + chosen {
> + stdout-path = &serial0;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <RTCCLK_FREQ>;
> +
> + cpu@0 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <16384>;
> + reg = <0>;
> + riscv,isa = "rv64imac";
> + status = "disabled";
> +
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> +
> + cpu@1 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <1>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + status = "okay";
> +
> + cpu1_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> +
> + cpu@2 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <2>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + status = "okay";
> +
> + cpu2_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> +
> + cpu@3 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <3>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + status = "okay";
> +
> + cpu3_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> +
> + cpu@4 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <4>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + status = "okay";
> + cpu4_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0x0 0x40000000>;
> + clocks = <&clkcfg 26>;
> + };
U-boot doesn't seem to be updating this properly.
The board should have 2GiB, confirmed by looking at the device's
chip markings. We only see 1GiB memory. The 0x80000000 bus window
is only capable of dealing with 1GiB memory. The higher 64-bit one
can have 16GiB mapped.
Do we need a second node for the second GiB of memory?
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + cache-controller@2010000 {
> + compatible = "sifive,fu540-c000-ccache", "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <1024>;
> + cache-size = <2097152>;
> + cache-unified;
> + interrupt-parent = <&plic>;
> + interrupts = <1 2 3>;
> + reg = <0x0 0x2010000 0x0 0x1000>;
> + };
> +
> + clint@2000000 {
> + compatible = "riscv,clint0";
> + reg = <0x0 0x2000000 0x0 0xC000>;
> + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
> + &cpu1_intc 3 &cpu1_intc 7
> + &cpu2_intc 3 &cpu2_intc 7
> + &cpu3_intc 3 &cpu3_intc 7
> + &cpu4_intc 3 &cpu4_intc 7>;
> + };
> +
> + plic: interrupt-controller@c000000 {
> + #interrupt-cells = <1>;
> + compatible = "sifive,plic-1.0.0";
> + reg = <0x0 0xc000000 0x0 0x4000000>;
> + riscv,ndev = <53>;
> + interrupt-controller;
> + interrupts-extended = <&cpu0_intc 11
> + &cpu1_intc 11 &cpu1_intc 9
> + &cpu2_intc 11 &cpu2_intc 9
> + &cpu3_intc 11 &cpu3_intc 9
> + &cpu4_intc 11 &cpu4_intc 9>;
> + };
> +
> + dma@3000000 {
> + compatible = "sifive,fu540-c000-pdma";
> + reg = <0x0 0x3000000 0x0 0x8000>;
> + interrupt-parent = <&plic>;
> + interrupts = <23 24 25 26 27 28 29 30>;
> + #dma-cells = <1>;
> + };
> +
> + refclk: refclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <600000000>;
> + clock-output-names = "msspllclk";
> + };
> +
> + clkcfg: clkcfg@20002000 {
> + compatible = "microchip,pfsoc-clkcfg";
> + reg = <0x0 0x20002000 0x0 0x1000>;
> + reg-names = "mss_sysreg";
> + clocks = <&refclk>;
> + #clock-cells = <1>;
> + clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", "MMUART2clk", "MMUART3clk", "MMUART4clk", "SPI0clk", "SPI1clk", "I2C0clk", "I2C1clk", "CAN0clk", "CAN1clk", "USBclk", "RESERVED", "RTCclk", "QSPIclk", "GPIO0clk", "GPIO1clk", "GPIO2clk", "DDRCclk", "FIC0clk", "FIC1clk", "FIC2clk", "FIC3clk", "ATHENAclk", "CFMclk";
Any chance of making this list multi-line, it is difficult to read as-is.
> + };
> +
> + serial0: serial@20000000 {
> + compatible = "ns16550a";
> + reg = <0x0 0x20000000 0x0 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupt-parent = <&plic>;
> + interrupts = <90>;
> + current-speed = <115200>;
> + clocks = <&clkcfg 8>;
> + status = "okay";
> + };
> +
> + serial1: serial@20100000 {
> + compatible = "ns16550a";
> + reg = <0x0 0x20100000 0x0 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupt-parent = <&plic>;
> + interrupts = <91>;
> + current-speed = <115200>;
> + clocks = <&clkcfg 9>;
> + status = "okay";
> + };
> +
> + serial2: serial@20102000 {
> + compatible = "ns16550a";
> + reg = <0x0 0x20102000 0x0 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupt-parent = <&plic>;
> + interrupts = <92>;
> + current-speed = <115200>;
> + clocks = <&clkcfg 10>;
> + status = "okay";
> + };
> +
> + serial3: serial@20104000 {
> + compatible = "ns16550a";
> + reg = <0x0 0x20104000 0x0 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupt-parent = <&plic>;
> + interrupts = <93>;
> + current-speed = <115200>;
> + clocks = <&clkcfg 11>;
> + status = "okay";
> + };
> +
> + sdcard: sdhc@20008000 {
> + compatible = "cdns,sd4hc";
> + reg = <0x0 0x20008000 0x0 0x1000>;
> + interrupt-parent = <&plic>;
> + interrupts = <88>;
> + pinctrl-names = "default";
> + clocks = <&clkcfg 6>;
> + bus-width = <4>;
> + disable-wp;
> + no-1-8-v;
> + cap-mmc-highspeed;
> + cap-sd-highspeed;
> + card-detect-delay = <200>;
> + sd-uhs-sdr12;
> + sd-uhs-sdr25;
> + sd-uhs-sdr50;
> + sd-uhs-sdr104;
> + max-frequency = <200000000>;
> + status = "okay";
> + };
Given eMMC is the default device, shouldn't that be default for the
device tree too? Even if not, having the emmc node here would be a
good thing as it is different to the SD node.
> +
> + emac1: ethernet@20112000 {
> + compatible = "cdns,macb";
> + reg = <0x0 0x20112000 0x0 0x2000>;
> + interrupt-parent = <&plic>;
> + interrupts = <70 71 72 73>;
> + mac-address = [56 34 12 00 FC 00];
> + phy-mode = "sgmii";
> + clocks = <&clkcfg 5>, <&clkcfg 2>;
> + clock-names = "pclk", "hclk";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + phy1: ethernet-phy@9 {
> + reg = <9>;
> + ti,fifo-depth = <0x01>;
> + };
> + };
Aren't there two ethernet ports on the board?
Also, at the moment u-boot is not filling the MAC address parameter
in so we've got at two boards on the network with the same MAC until
we override it in the device tree for the second.
> +
> + uio_axi_lsram@2030000000 {
> + compatible = "generic-uio";
> + reg = <0x20 0x30000000 0 0x80000000 >;
> + status = "okay";
> + };
> + };
> +};
>
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
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linux-riscv@lists.infradead.org
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-10-29 10:24 ` Ben Dooks
@ 2020-10-30 7:11 ` Atish Patra
2020-10-30 21:19 ` Ben Dooks
2020-11-04 2:41 ` Bin Meng
1 sibling, 1 reply; 38+ messages in thread
From: Atish Patra @ 2020-10-30 7:11 UTC (permalink / raw)
To: Ben Dooks
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel@vger.kernel.org List, Atish Patra, Rob Herring,
Alistair Francis, Paul Walmsley, Palmer Dabbelt, linux-riscv,
Padmarao Begari
On Thu, Oct 29, 2020 at 3:24 AM Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>
> On 28/10/2020 23:27, Atish Patra wrote:
> > Add initial DTS for Microchip ICICLE board having only
> > essential devcies (clocks, sdhci, ethernet, serial, etc).
> >
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > ---
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/microchip/Makefile | 2 +
> > .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
> > 3 files changed, 316 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> > create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >
> > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > index ca1f8cbd78c0..3ea94ea0a18a 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -1,5 +1,6 @@
> > # SPDX-License-Identifier: GPL-2.0
> > subdir-y += sifive
> > subdir-y += kendryte
> > +subdir-y += microchip
> >
> > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> > diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
> > new file mode 100644
> > index 000000000000..55ad77521304
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
> > diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> > new file mode 100644
> > index 000000000000..5848920af55c
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> > @@ -0,0 +1,313 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +
> > +/* Clock frequency (in Hz) of the rtcclk */
> > +#define RTCCLK_FREQ 1000000
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + model = "Microchip PolarFire-SoC";
> > + compatible = "microchip,polarfire-soc";
> > +
> > + chosen {
> > + stdout-path = &serial0;
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <RTCCLK_FREQ>;
> > +
> > + cpu@0 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <128>;
> > + i-cache-size = <16384>;
> > + reg = <0>;
> > + riscv,isa = "rv64imac";
> > + status = "disabled";
> > +
> > + cpu0_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > +
> > + cpu@1 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <1>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > +
> > + cpu1_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > +
> > + cpu@2 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <2>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > +
> > + cpu2_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > +
> > + cpu@3 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <3>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > +
> > + cpu3_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > +
> > + cpu@4 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <4>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > + cpu4_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + };
> > +
> > + memory@80000000 {
> > + device_type = "memory";
> > + reg = <0x0 0x80000000 0x0 0x40000000>;
> > + clocks = <&clkcfg 26>;
> > + };
>
> U-boot doesn't seem to be updating this properly.
>
> The board should have 2GiB, confirmed by looking at the device's
> chip markings. We only see 1GiB memory. The 0x80000000 bus window
> is only capable of dealing with 1GiB memory. The higher 64-bit one
> can have 16GiB mapped.
>
> Do we need a second node for the second GiB of memory?
>
We could just modify the reg size but to allow more memory. I tried
that for Linux but it didn't boot.
Probably, DDR init code in HSS only initialized 1GB of memory.
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + compatible = "simple-bus";
> > + ranges;
> > +
> > + cache-controller@2010000 {
> > + compatible = "sifive,fu540-c000-ccache", "cache";
> > + cache-block-size = <64>;
> > + cache-level = <2>;
> > + cache-sets = <1024>;
> > + cache-size = <2097152>;
> > + cache-unified;
> > + interrupt-parent = <&plic>;
> > + interrupts = <1 2 3>;
> > + reg = <0x0 0x2010000 0x0 0x1000>;
> > + };
> > +
> > + clint@2000000 {
> > + compatible = "riscv,clint0";
> > + reg = <0x0 0x2000000 0x0 0xC000>;
> > + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
> > + &cpu1_intc 3 &cpu1_intc 7
> > + &cpu2_intc 3 &cpu2_intc 7
> > + &cpu3_intc 3 &cpu3_intc 7
> > + &cpu4_intc 3 &cpu4_intc 7>;
> > + };
> > +
> > + plic: interrupt-controller@c000000 {
> > + #interrupt-cells = <1>;
> > + compatible = "sifive,plic-1.0.0";
> > + reg = <0x0 0xc000000 0x0 0x4000000>;
> > + riscv,ndev = <53>;
> > + interrupt-controller;
> > + interrupts-extended = <&cpu0_intc 11
> > + &cpu1_intc 11 &cpu1_intc 9
> > + &cpu2_intc 11 &cpu2_intc 9
> > + &cpu3_intc 11 &cpu3_intc 9
> > + &cpu4_intc 11 &cpu4_intc 9>;
> > + };
> > +
> > + dma@3000000 {
> > + compatible = "sifive,fu540-c000-pdma";
> > + reg = <0x0 0x3000000 0x0 0x8000>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <23 24 25 26 27 28 29 30>;
> > + #dma-cells = <1>;
> > + };
> > +
> > + refclk: refclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <600000000>;
> > + clock-output-names = "msspllclk";
> > + };
> > +
> > + clkcfg: clkcfg@20002000 {
> > + compatible = "microchip,pfsoc-clkcfg";
> > + reg = <0x0 0x20002000 0x0 0x1000>;
> > + reg-names = "mss_sysreg";
> > + clocks = <&refclk>;
> > + #clock-cells = <1>;
> > + clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", "MMUART2clk", "MMUART3clk", "MMUART4clk", "SPI0clk", "SPI1clk", "I2C0clk", "I2C1clk", "CAN0clk", "CAN1clk", "USBclk", "RESERVED", "RTCclk", "QSPIclk", "GPIO0clk", "GPIO1clk", "GPIO2clk", "DDRCclk", "FIC0clk", "FIC1clk", "FIC2clk", "FIC3clk", "ATHENAclk", "CFMclk";
>
> Any chance of making this list multi-line, it is difficult to read as-is.
>
Yes. We can also get rid of a few names that are not used. I will fix it in v2.
> > + };
> > +
> > + serial0: serial@20000000 {
> > + compatible = "ns16550a";
> > + reg = <0x0 0x20000000 0x0 0x400>;
> > + reg-io-width = <4>;
> > + reg-shift = <2>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <90>;
> > + current-speed = <115200>;
> > + clocks = <&clkcfg 8>;
> > + status = "okay";
> > + };
> > +
> > + serial1: serial@20100000 {
> > + compatible = "ns16550a";
> > + reg = <0x0 0x20100000 0x0 0x400>;
> > + reg-io-width = <4>;
> > + reg-shift = <2>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <91>;
> > + current-speed = <115200>;
> > + clocks = <&clkcfg 9>;
> > + status = "okay";
> > + };
> > +
> > + serial2: serial@20102000 {
> > + compatible = "ns16550a";
> > + reg = <0x0 0x20102000 0x0 0x400>;
> > + reg-io-width = <4>;
> > + reg-shift = <2>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <92>;
> > + current-speed = <115200>;
> > + clocks = <&clkcfg 10>;
> > + status = "okay";
> > + };
> > +
> > + serial3: serial@20104000 {
> > + compatible = "ns16550a";
> > + reg = <0x0 0x20104000 0x0 0x400>;
> > + reg-io-width = <4>;
> > + reg-shift = <2>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <93>;
> > + current-speed = <115200>;
> > + clocks = <&clkcfg 11>;
> > + status = "okay";
> > + };
> > +
> > + sdcard: sdhc@20008000 {
> > + compatible = "cdns,sd4hc";
> > + reg = <0x0 0x20008000 0x0 0x1000>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <88>;
> > + pinctrl-names = "default";
> > + clocks = <&clkcfg 6>;
> > + bus-width = <4>;
> > + disable-wp;
> > + no-1-8-v;
> > + cap-mmc-highspeed;
> > + cap-sd-highspeed;
> > + card-detect-delay = <200>;
> > + sd-uhs-sdr12;
> > + sd-uhs-sdr25;
> > + sd-uhs-sdr50;
> > + sd-uhs-sdr104;
> > + max-frequency = <200000000>;
> > + status = "okay";
> > + };
>
> Given eMMC is the default device, shouldn't that be default for the
> device tree too? Even if not, having the emmc node here would be a
> good thing as it is different to the SD node.
>
I tested this device tree with sdcard. That's why, I just picked the
sdcard node.
I am not sure if both eMMC & sdcard node can co-exist. The polar fire
soc github repo
seems to point that both of them have the same address and only 1 can be enabled
at that time. That may not be true now as the github repo has not been
updated in
couple of months.
@Cyril : Can we enable both eMMC & sdcard at the same time ?
> > +
> > + emac1: ethernet@20112000 {
> > + compatible = "cdns,macb";
> > + reg = <0x0 0x20112000 0x0 0x2000>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <70 71 72 73>;
> > + mac-address = [56 34 12 00 FC 00];
> > + phy-mode = "sgmii";
> > + clocks = <&clkcfg 5>, <&clkcfg 2>;
> > + clock-names = "pclk", "hclk";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + phy1: ethernet-phy@9 {
> > + reg = <9>;
> > + ti,fifo-depth = <0x01>;
> > + };
> > + };
>
> Aren't there two ethernet ports on the board?
>
Yes. I hadn't tested that out. I will test it and add the 2nd one as well.
> Also, at the moment u-boot is not filling the MAC address parameter
> in so we've got at two boards on the network with the same MAC until
> we override it in the device tree for the second.
>
Looking at latest U-Boot patches, it seems it updates the mac address
from the serial number.
> > +
> > + uio_axi_lsram@2030000000 {
> > + compatible = "generic-uio";
> > + reg = <0x20 0x30000000 0 0x80000000 >;
> > + status = "okay";
> > + };
> > + };
> > +};
> >
>
>
> --
> Ben Dooks http://www.codethink.co.uk/
> Senior Engineer Codethink - Providing Genius
>
> https://www.codethink.co.uk/privacy.html
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
--
Regards,
Atish
_______________________________________________
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-10-28 23:27 ` [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra
2020-10-29 10:24 ` Ben Dooks
@ 2020-10-30 9:05 ` Anup Patel
2020-10-30 20:27 ` Atish Patra
` (2 more replies)
2020-11-06 7:14 ` Palmer Dabbelt
2 siblings, 3 replies; 38+ messages in thread
From: Anup Patel @ 2020-10-30 9:05 UTC (permalink / raw)
To: Atish Patra
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel@vger.kernel.org List, Rob Herring, Alistair Francis,
Paul Walmsley, Palmer Dabbelt, linux-riscv, Padmarao Begari
On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> Add initial DTS for Microchip ICICLE board having only
> essential devcies (clocks, sdhci, ethernet, serial, etc).
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/microchip/Makefile | 2 +
> .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
I suggest we split this DTS into two parts:
1. SOC (microchip-polarfire.dtsi)
2. Board (microchip-icicle-kit-a000.dts)
This will be much cleaner and aligned with what is done
on other architectures.
> 3 files changed, 316 insertions(+)
> create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ca1f8cbd78c0..3ea94ea0a18a 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> subdir-y += sifive
> subdir-y += kendryte
> +subdir-y += microchip
>
> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
> new file mode 100644
> index 000000000000..55ad77521304
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
> diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> new file mode 100644
> index 000000000000..5848920af55c
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> @@ -0,0 +1,313 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/* Copyright (c) 2020 Microchip Technology Inc */
> +
> +/dts-v1/;
> +
> +/* Clock frequency (in Hz) of the rtcclk */
> +#define RTCCLK_FREQ 1000000
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + model = "Microchip PolarFire-SoC";
> + compatible = "microchip,polarfire-soc";
> +
> + chosen {
> + stdout-path = &serial0;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <RTCCLK_FREQ>;
> +
> + cpu@0 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <16384>;
> + reg = <0>;
> + riscv,isa = "rv64imac";
> + status = "disabled";
> +
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> +
> + cpu@1 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <1>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + status = "okay";
> +
> + cpu1_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> +
> + cpu@2 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <2>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + status = "okay";
> +
> + cpu2_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> +
> + cpu@3 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <3>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + status = "okay";
> +
> + cpu3_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> +
> + cpu@4 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <4>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + status = "okay";
> + cpu4_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0x0 0x40000000>;
> + clocks = <&clkcfg 26>;
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + cache-controller@2010000 {
> + compatible = "sifive,fu540-c000-ccache", "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <1024>;
> + cache-size = <2097152>;
> + cache-unified;
> + interrupt-parent = <&plic>;
> + interrupts = <1 2 3>;
> + reg = <0x0 0x2010000 0x0 0x1000>;
> + };
> +
> + clint@2000000 {
> + compatible = "riscv,clint0";
> + reg = <0x0 0x2000000 0x0 0xC000>;
> + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
> + &cpu1_intc 3 &cpu1_intc 7
> + &cpu2_intc 3 &cpu2_intc 7
> + &cpu3_intc 3 &cpu3_intc 7
> + &cpu4_intc 3 &cpu4_intc 7>;
> + };
> +
> + plic: interrupt-controller@c000000 {
> + #interrupt-cells = <1>;
> + compatible = "sifive,plic-1.0.0";
> + reg = <0x0 0xc000000 0x0 0x4000000>;
> + riscv,ndev = <53>;
> + interrupt-controller;
> + interrupts-extended = <&cpu0_intc 11
> + &cpu1_intc 11 &cpu1_intc 9
> + &cpu2_intc 11 &cpu2_intc 9
> + &cpu3_intc 11 &cpu3_intc 9
> + &cpu4_intc 11 &cpu4_intc 9>;
> + };
> +
> + dma@3000000 {
> + compatible = "sifive,fu540-c000-pdma";
> + reg = <0x0 0x3000000 0x0 0x8000>;
> + interrupt-parent = <&plic>;
> + interrupts = <23 24 25 26 27 28 29 30>;
> + #dma-cells = <1>;
> + };
> +
> + refclk: refclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <600000000>;
> + clock-output-names = "msspllclk";
> + };
> +
> + clkcfg: clkcfg@20002000 {
> + compatible = "microchip,pfsoc-clkcfg";
> + reg = <0x0 0x20002000 0x0 0x1000>;
> + reg-names = "mss_sysreg";
> + clocks = <&refclk>;
> + #clock-cells = <1>;
> + clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", "MMUART2clk", "MMUART3clk", "MMUART4clk", "SPI0clk", "SPI1clk", "I2C0clk", "I2C1clk", "CAN0clk", "CAN1clk", "USBclk", "RESERVED", "RTCclk", "QSPIclk", "GPIO0clk", "GPIO1clk", "GPIO2clk", "DDRCclk", "FIC0clk", "FIC1clk", "FIC2clk", "FIC3clk", "ATHENAclk", "CFMclk";
> + };
> +
> + serial0: serial@20000000 {
> + compatible = "ns16550a";
> + reg = <0x0 0x20000000 0x0 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupt-parent = <&plic>;
> + interrupts = <90>;
> + current-speed = <115200>;
> + clocks = <&clkcfg 8>;
> + status = "okay";
> + };
> +
> + serial1: serial@20100000 {
> + compatible = "ns16550a";
> + reg = <0x0 0x20100000 0x0 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupt-parent = <&plic>;
> + interrupts = <91>;
> + current-speed = <115200>;
> + clocks = <&clkcfg 9>;
> + status = "okay";
> + };
> +
> + serial2: serial@20102000 {
> + compatible = "ns16550a";
> + reg = <0x0 0x20102000 0x0 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupt-parent = <&plic>;
> + interrupts = <92>;
> + current-speed = <115200>;
> + clocks = <&clkcfg 10>;
> + status = "okay";
> + };
> +
> + serial3: serial@20104000 {
> + compatible = "ns16550a";
> + reg = <0x0 0x20104000 0x0 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupt-parent = <&plic>;
> + interrupts = <93>;
> + current-speed = <115200>;
> + clocks = <&clkcfg 11>;
> + status = "okay";
> + };
> +
> + sdcard: sdhc@20008000 {
> + compatible = "cdns,sd4hc";
> + reg = <0x0 0x20008000 0x0 0x1000>;
> + interrupt-parent = <&plic>;
> + interrupts = <88>;
> + pinctrl-names = "default";
> + clocks = <&clkcfg 6>;
> + bus-width = <4>;
> + disable-wp;
> + no-1-8-v;
> + cap-mmc-highspeed;
> + cap-sd-highspeed;
> + card-detect-delay = <200>;
> + sd-uhs-sdr12;
> + sd-uhs-sdr25;
> + sd-uhs-sdr50;
> + sd-uhs-sdr104;
> + max-frequency = <200000000>;
> + status = "okay";
> + };
> +
> + emac1: ethernet@20112000 {
> + compatible = "cdns,macb";
> + reg = <0x0 0x20112000 0x0 0x2000>;
> + interrupt-parent = <&plic>;
> + interrupts = <70 71 72 73>;
> + mac-address = [56 34 12 00 FC 00];
> + phy-mode = "sgmii";
> + clocks = <&clkcfg 5>, <&clkcfg 2>;
> + clock-names = "pclk", "hclk";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + phy1: ethernet-phy@9 {
> + reg = <9>;
> + ti,fifo-depth = <0x01>;
> + };
> + };
> +
> + uio_axi_lsram@2030000000 {
> + compatible = "generic-uio";
> + reg = <0x20 0x30000000 0 0x80000000 >;
> + status = "okay";
> + };
> + };
> +};
> --
> 2.25.1
>
Regards,
Anup
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 1/3] RISC-V: Add Microchip PolarFire SoC kconfig option
2020-10-28 23:27 ` [RFC PATCH 1/3] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra
@ 2020-10-30 9:08 ` Anup Patel
2020-11-03 9:55 ` Bin Meng
2020-11-06 7:14 ` Palmer Dabbelt
2 siblings, 0 replies; 38+ messages in thread
From: Anup Patel @ 2020-10-30 9:08 UTC (permalink / raw)
To: Atish Patra
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel@vger.kernel.org List, Rob Herring, Alistair Francis,
Paul Walmsley, Palmer Dabbelt, linux-riscv, Padmarao Begari
On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> Add Microchip PolarFire kconfig option which selects SoC specific
> and common drivers that is required for this SoC.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> arch/riscv/Kconfig.socs | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 8a55f6156661..74d07250ecc5 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -22,6 +22,13 @@ config SOC_VIRT
> help
> This enables support for QEMU Virt Machine.
>
> +config SOC_MICROCHIP_POLARFIRE
> + bool "Microchip PolarFire SoCs"
> + select MCHP_CLK_PFSOC
> + select SIFIVE_PLIC
> + help
> + This enables support for Microchip PolarFire SoC platforms.
> +
> config SOC_KENDRYTE
> bool "Kendryte K210 SoC"
> depends on !MMU
> --
> 2.25.1
>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
_______________________________________________
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linux-riscv@lists.infradead.org
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC
2020-10-28 23:27 ` [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra
@ 2020-10-30 9:09 ` Anup Patel
2020-10-30 21:21 ` Ben Dooks
2020-11-03 10:03 ` Bin Meng
2020-11-06 7:14 ` Palmer Dabbelt
2 siblings, 1 reply; 38+ messages in thread
From: Anup Patel @ 2020-10-30 9:09 UTC (permalink / raw)
To: Atish Patra
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel@vger.kernel.org List, Rob Herring, Alistair Francis,
Paul Walmsley, Palmer Dabbelt, linux-riscv, Padmarao Begari
On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> Enable Microchip PolarFire ICICLE soc config in defconfig.
> It allows the default upstream kernel to boot on PolarFire ICICLE board.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> arch/riscv/configs/defconfig | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index d222d353d86d..2660fa05451e 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -16,6 +16,7 @@ CONFIG_EXPERT=y
> CONFIG_BPF_SYSCALL=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_VIRT=y
> +CONFIG_SOC_MICROCHIP_POLARFIRE=y
> CONFIG_SMP=y
> CONFIG_JUMP_LABEL=y
> CONFIG_MODULES=y
> @@ -79,6 +80,9 @@ CONFIG_USB_OHCI_HCD=y
> CONFIG_USB_OHCI_HCD_PLATFORM=y
> CONFIG_USB_STORAGE=y
> CONFIG_USB_UAS=y
> +CONFIG_SDHCI=y
> +CONFIG_MMC_SDHCI_PLTFM=y
> +CONFIG_MMC_SDHCI_CADENCE=y
> CONFIG_MMC=y
> CONFIG_MMC_SPI=y
> CONFIG_RTC_CLASS=y
> --
> 2.25.1
>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-10-30 9:05 ` Anup Patel
@ 2020-10-30 20:27 ` Atish Patra
2020-11-03 10:59 ` Ben Dooks
2020-10-30 21:20 ` Ben Dooks
2020-11-03 10:00 ` Bin Meng
2 siblings, 1 reply; 38+ messages in thread
From: Atish Patra @ 2020-10-30 20:27 UTC (permalink / raw)
To: Anup Patel
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel@vger.kernel.org List, Atish Patra, Rob Herring,
Alistair Francis, Paul Walmsley, Palmer Dabbelt, linux-riscv,
Padmarao Begari
On Fri, Oct 30, 2020 at 2:05 AM Anup Patel <anup@brainfault.org> wrote:
>
> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <atish.patra@wdc.com> wrote:
> >
> > Add initial DTS for Microchip ICICLE board having only
> > essential devcies (clocks, sdhci, ethernet, serial, etc).
> >
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > ---
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/microchip/Makefile | 2 +
> > .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
>
> I suggest we split this DTS into two parts:
> 1. SOC (microchip-polarfire.dtsi)
> 2. Board (microchip-icicle-kit-a000.dts)
>
> This will be much cleaner and aligned with what is done
> on other architectures.
>
Sure. I will do that in v2.
> > 3 files changed, 316 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> > create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >
> > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > index ca1f8cbd78c0..3ea94ea0a18a 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -1,5 +1,6 @@
> > # SPDX-License-Identifier: GPL-2.0
> > subdir-y += sifive
> > subdir-y += kendryte
> > +subdir-y += microchip
> >
> > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> > diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
> > new file mode 100644
> > index 000000000000..55ad77521304
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
> > diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> > new file mode 100644
> > index 000000000000..5848920af55c
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> > @@ -0,0 +1,313 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +
> > +/* Clock frequency (in Hz) of the rtcclk */
> > +#define RTCCLK_FREQ 1000000
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + model = "Microchip PolarFire-SoC";
> > + compatible = "microchip,polarfire-soc";
> > +
> > + chosen {
> > + stdout-path = &serial0;
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <RTCCLK_FREQ>;
> > +
> > + cpu@0 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <128>;
> > + i-cache-size = <16384>;
> > + reg = <0>;
> > + riscv,isa = "rv64imac";
> > + status = "disabled";
> > +
> > + cpu0_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > +
> > + cpu@1 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <1>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > +
> > + cpu1_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > +
> > + cpu@2 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <2>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > +
> > + cpu2_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > +
> > + cpu@3 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <3>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > +
> > + cpu3_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > +
> > + cpu@4 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <4>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > + cpu4_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + };
> > +
> > + memory@80000000 {
> > + device_type = "memory";
> > + reg = <0x0 0x80000000 0x0 0x40000000>;
> > + clocks = <&clkcfg 26>;
> > + };
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + compatible = "simple-bus";
> > + ranges;
> > +
> > + cache-controller@2010000 {
> > + compatible = "sifive,fu540-c000-ccache", "cache";
> > + cache-block-size = <64>;
> > + cache-level = <2>;
> > + cache-sets = <1024>;
> > + cache-size = <2097152>;
> > + cache-unified;
> > + interrupt-parent = <&plic>;
> > + interrupts = <1 2 3>;
> > + reg = <0x0 0x2010000 0x0 0x1000>;
> > + };
> > +
> > + clint@2000000 {
> > + compatible = "riscv,clint0";
> > + reg = <0x0 0x2000000 0x0 0xC000>;
> > + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
> > + &cpu1_intc 3 &cpu1_intc 7
> > + &cpu2_intc 3 &cpu2_intc 7
> > + &cpu3_intc 3 &cpu3_intc 7
> > + &cpu4_intc 3 &cpu4_intc 7>;
> > + };
> > +
> > + plic: interrupt-controller@c000000 {
> > + #interrupt-cells = <1>;
> > + compatible = "sifive,plic-1.0.0";
> > + reg = <0x0 0xc000000 0x0 0x4000000>;
> > + riscv,ndev = <53>;
> > + interrupt-controller;
> > + interrupts-extended = <&cpu0_intc 11
> > + &cpu1_intc 11 &cpu1_intc 9
> > + &cpu2_intc 11 &cpu2_intc 9
> > + &cpu3_intc 11 &cpu3_intc 9
> > + &cpu4_intc 11 &cpu4_intc 9>;
> > + };
> > +
> > + dma@3000000 {
> > + compatible = "sifive,fu540-c000-pdma";
> > + reg = <0x0 0x3000000 0x0 0x8000>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <23 24 25 26 27 28 29 30>;
> > + #dma-cells = <1>;
> > + };
> > +
> > + refclk: refclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <600000000>;
> > + clock-output-names = "msspllclk";
> > + };
> > +
> > + clkcfg: clkcfg@20002000 {
> > + compatible = "microchip,pfsoc-clkcfg";
> > + reg = <0x0 0x20002000 0x0 0x1000>;
> > + reg-names = "mss_sysreg";
> > + clocks = <&refclk>;
> > + #clock-cells = <1>;
> > + clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", "MMUART2clk", "MMUART3clk", "MMUART4clk", "SPI0clk", "SPI1clk", "I2C0clk", "I2C1clk", "CAN0clk", "CAN1clk", "USBclk", "RESERVED", "RTCclk", "QSPIclk", "GPIO0clk", "GPIO1clk", "GPIO2clk", "DDRCclk", "FIC0clk", "FIC1clk", "FIC2clk", "FIC3clk", "ATHENAclk", "CFMclk";
> > + };
> > +
> > + serial0: serial@20000000 {
> > + compatible = "ns16550a";
> > + reg = <0x0 0x20000000 0x0 0x400>;
> > + reg-io-width = <4>;
> > + reg-shift = <2>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <90>;
> > + current-speed = <115200>;
> > + clocks = <&clkcfg 8>;
> > + status = "okay";
> > + };
> > +
> > + serial1: serial@20100000 {
> > + compatible = "ns16550a";
> > + reg = <0x0 0x20100000 0x0 0x400>;
> > + reg-io-width = <4>;
> > + reg-shift = <2>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <91>;
> > + current-speed = <115200>;
> > + clocks = <&clkcfg 9>;
> > + status = "okay";
> > + };
> > +
> > + serial2: serial@20102000 {
> > + compatible = "ns16550a";
> > + reg = <0x0 0x20102000 0x0 0x400>;
> > + reg-io-width = <4>;
> > + reg-shift = <2>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <92>;
> > + current-speed = <115200>;
> > + clocks = <&clkcfg 10>;
> > + status = "okay";
> > + };
> > +
> > + serial3: serial@20104000 {
> > + compatible = "ns16550a";
> > + reg = <0x0 0x20104000 0x0 0x400>;
> > + reg-io-width = <4>;
> > + reg-shift = <2>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <93>;
> > + current-speed = <115200>;
> > + clocks = <&clkcfg 11>;
> > + status = "okay";
> > + };
> > +
> > + sdcard: sdhc@20008000 {
> > + compatible = "cdns,sd4hc";
> > + reg = <0x0 0x20008000 0x0 0x1000>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <88>;
> > + pinctrl-names = "default";
> > + clocks = <&clkcfg 6>;
> > + bus-width = <4>;
> > + disable-wp;
> > + no-1-8-v;
> > + cap-mmc-highspeed;
> > + cap-sd-highspeed;
> > + card-detect-delay = <200>;
> > + sd-uhs-sdr12;
> > + sd-uhs-sdr25;
> > + sd-uhs-sdr50;
> > + sd-uhs-sdr104;
> > + max-frequency = <200000000>;
> > + status = "okay";
> > + };
> > +
> > + emac1: ethernet@20112000 {
> > + compatible = "cdns,macb";
> > + reg = <0x0 0x20112000 0x0 0x2000>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <70 71 72 73>;
> > + mac-address = [56 34 12 00 FC 00];
> > + phy-mode = "sgmii";
> > + clocks = <&clkcfg 5>, <&clkcfg 2>;
> > + clock-names = "pclk", "hclk";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + phy1: ethernet-phy@9 {
> > + reg = <9>;
> > + ti,fifo-depth = <0x01>;
> > + };
> > + };
> > +
> > + uio_axi_lsram@2030000000 {
> > + compatible = "generic-uio";
> > + reg = <0x20 0x30000000 0 0x80000000 >;
> > + status = "okay";
> > + };
> > + };
> > +};
> > --
> > 2.25.1
> >
>
> Regards,
> Anup
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-10-30 7:11 ` Atish Patra
@ 2020-10-30 21:19 ` Ben Dooks
2020-11-03 15:07 ` Atish Patra
0 siblings, 1 reply; 38+ messages in thread
From: Ben Dooks @ 2020-10-30 21:19 UTC (permalink / raw)
To: Atish Patra
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel@vger.kernel.org List, Atish Patra, Rob Herring,
Alistair Francis, Paul Walmsley, Palmer Dabbelt, linux-riscv,
Padmarao Begari
On 30/10/2020 07:11, Atish Patra wrote:
> On Thu, Oct 29, 2020 at 3:24 AM Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>>
>> On 28/10/2020 23:27, Atish Patra wrote:
>>> Add initial DTS for Microchip ICICLE board having only
>>> essential devcies (clocks, sdhci, ethernet, serial, etc).
>>>
>>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
>>> ---
>>> arch/riscv/boot/dts/Makefile | 1 +
>>> arch/riscv/boot/dts/microchip/Makefile | 2 +
>>> .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
>>> 3 files changed, 316 insertions(+)
>>> create mode 100644 arch/riscv/boot/dts/microchip/Makefile
>>> create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>>>
>>> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
>>> index ca1f8cbd78c0..3ea94ea0a18a 100644
>>> --- a/arch/riscv/boot/dts/Makefile
>>> +++ b/arch/riscv/boot/dts/Makefile
>>> @@ -1,5 +1,6 @@
>>> # SPDX-License-Identifier: GPL-2.0
>>> subdir-y += sifive
>>> subdir-y += kendryte
>>> +subdir-y += microchip
>>>
>>> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
>>> diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
>>> new file mode 100644
>>> index 000000000000..55ad77521304
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/dts/microchip/Makefile
>>> @@ -0,0 +1,2 @@
>>> +# SPDX-License-Identifier: GPL-2.0
>>> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
>>> diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>>> new file mode 100644
>>> index 000000000000..5848920af55c
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>>> @@ -0,0 +1,313 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/* Copyright (c) 2020 Microchip Technology Inc */
>>> +
>>> +/dts-v1/;
>>> +
>>> +/* Clock frequency (in Hz) of the rtcclk */
>>> +#define RTCCLK_FREQ 1000000
>>> +
>>> +/ {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + model = "Microchip PolarFire-SoC";
>>> + compatible = "microchip,polarfire-soc";
>>> +
>>> + chosen {
>>> + stdout-path = &serial0;
>>> + };
>>> +
>>> + cpus {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + timebase-frequency = <RTCCLK_FREQ>;
>>> +
>>> + cpu@0 {
>>> + clock-frequency = <0>;
>>> + compatible = "sifive,rocket0", "riscv";
>>> + device_type = "cpu";
>>> + i-cache-block-size = <64>;
>>> + i-cache-sets = <128>;
>>> + i-cache-size = <16384>;
>>> + reg = <0>;
>>> + riscv,isa = "rv64imac";
>>> + status = "disabled";
>>> +
>>> + cpu0_intc: interrupt-controller {
>>> + #interrupt-cells = <1>;
>>> + compatible = "riscv,cpu-intc";
>>> + interrupt-controller;
>>> + };
>>> + };
>>> +
>>> + cpu@1 {
>>> + clock-frequency = <0>;
>>> + compatible = "sifive,rocket0", "riscv";
>>> + d-cache-block-size = <64>;
>>> + d-cache-sets = <64>;
>>> + d-cache-size = <32768>;
>>> + d-tlb-sets = <1>;
>>> + d-tlb-size = <32>;
>>> + device_type = "cpu";
>>> + i-cache-block-size = <64>;
>>> + i-cache-sets = <64>;
>>> + i-cache-size = <32768>;
>>> + i-tlb-sets = <1>;
>>> + i-tlb-size = <32>;
>>> + mmu-type = "riscv,sv39";
>>> + reg = <1>;
>>> + riscv,isa = "rv64imafdc";
>>> + tlb-split;
>>> + status = "okay";
>>> +
>>> + cpu1_intc: interrupt-controller {
>>> + #interrupt-cells = <1>;
>>> + compatible = "riscv,cpu-intc";
>>> + interrupt-controller;
>>> + };
>>> + };
>>> +
>>> + cpu@2 {
>>> + clock-frequency = <0>;
>>> + compatible = "sifive,rocket0", "riscv";
>>> + d-cache-block-size = <64>;
>>> + d-cache-sets = <64>;
>>> + d-cache-size = <32768>;
>>> + d-tlb-sets = <1>;
>>> + d-tlb-size = <32>;
>>> + device_type = "cpu";
>>> + i-cache-block-size = <64>;
>>> + i-cache-sets = <64>;
>>> + i-cache-size = <32768>;
>>> + i-tlb-sets = <1>;
>>> + i-tlb-size = <32>;
>>> + mmu-type = "riscv,sv39";
>>> + reg = <2>;
>>> + riscv,isa = "rv64imafdc";
>>> + tlb-split;
>>> + status = "okay";
>>> +
>>> + cpu2_intc: interrupt-controller {
>>> + #interrupt-cells = <1>;
>>> + compatible = "riscv,cpu-intc";
>>> + interrupt-controller;
>>> + };
>>> + };
>>> +
>>> + cpu@3 {
>>> + clock-frequency = <0>;
>>> + compatible = "sifive,rocket0", "riscv";
>>> + d-cache-block-size = <64>;
>>> + d-cache-sets = <64>;
>>> + d-cache-size = <32768>;
>>> + d-tlb-sets = <1>;
>>> + d-tlb-size = <32>;
>>> + device_type = "cpu";
>>> + i-cache-block-size = <64>;
>>> + i-cache-sets = <64>;
>>> + i-cache-size = <32768>;
>>> + i-tlb-sets = <1>;
>>> + i-tlb-size = <32>;
>>> + mmu-type = "riscv,sv39";
>>> + reg = <3>;
>>> + riscv,isa = "rv64imafdc";
>>> + tlb-split;
>>> + status = "okay";
>>> +
>>> + cpu3_intc: interrupt-controller {
>>> + #interrupt-cells = <1>;
>>> + compatible = "riscv,cpu-intc";
>>> + interrupt-controller;
>>> + };
>>> + };
>>> +
>>> + cpu@4 {
>>> + clock-frequency = <0>;
>>> + compatible = "sifive,rocket0", "riscv";
>>> + d-cache-block-size = <64>;
>>> + d-cache-sets = <64>;
>>> + d-cache-size = <32768>;
>>> + d-tlb-sets = <1>;
>>> + d-tlb-size = <32>;
>>> + device_type = "cpu";
>>> + i-cache-block-size = <64>;
>>> + i-cache-sets = <64>;
>>> + i-cache-size = <32768>;
>>> + i-tlb-sets = <1>;
>>> + i-tlb-size = <32>;
>>> + mmu-type = "riscv,sv39";
>>> + reg = <4>;
>>> + riscv,isa = "rv64imafdc";
>>> + tlb-split;
>>> + status = "okay";
>>> + cpu4_intc: interrupt-controller {
>>> + #interrupt-cells = <1>;
>>> + compatible = "riscv,cpu-intc";
>>> + interrupt-controller;
>>> + };
>>> + };
>>> + };
>>> +
>>> + memory@80000000 {
>>> + device_type = "memory";
>>> + reg = <0x0 0x80000000 0x0 0x40000000>;
>>> + clocks = <&clkcfg 26>;
>>> + };
>>
>> U-boot doesn't seem to be updating this properly.
>>
>> The board should have 2GiB, confirmed by looking at the device's
>> chip markings. We only see 1GiB memory. The 0x80000000 bus window
>> is only capable of dealing with 1GiB memory. The higher 64-bit one
>> can have 16GiB mapped.
>>
>> Do we need a second node for the second GiB of memory?
>>
> We could just modify the reg size but to allow more memory. I tried
> that for Linux but it didn't boot.
> Probably, DDR init code in HSS only initialized 1GB of memory.
Yes, it is only looking at the low window which is 1GiB max.
If it used the upper window it would get the 16GiB.
I don't know how no-one noticed this issue before shipping a board
out with this. I have updated the firmware on my second board but
this only seems to currently fix a reboot issue with the eMMC.
>>> +
>>> + soc {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + compatible = "simple-bus";
>>> + ranges;
>>> +
>>> + cache-controller@2010000 {
>>> + compatible = "sifive,fu540-c000-ccache", "cache";
>>> + cache-block-size = <64>;
>>> + cache-level = <2>;
>>> + cache-sets = <1024>;
>>> + cache-size = <2097152>;
>>> + cache-unified;
>>> + interrupt-parent = <&plic>;
>>> + interrupts = <1 2 3>;
>>> + reg = <0x0 0x2010000 0x0 0x1000>;
>>> + };
>>> +
>>> + clint@2000000 {
>>> + compatible = "riscv,clint0";
>>> + reg = <0x0 0x2000000 0x0 0xC000>;
>>> + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
>>> + &cpu1_intc 3 &cpu1_intc 7
>>> + &cpu2_intc 3 &cpu2_intc 7
>>> + &cpu3_intc 3 &cpu3_intc 7
>>> + &cpu4_intc 3 &cpu4_intc 7>;
>>> + };
>>> +
>>> + plic: interrupt-controller@c000000 {
>>> + #interrupt-cells = <1>;
>>> + compatible = "sifive,plic-1.0.0";
>>> + reg = <0x0 0xc000000 0x0 0x4000000>;
>>> + riscv,ndev = <53>;
>>> + interrupt-controller;
>>> + interrupts-extended = <&cpu0_intc 11
>>> + &cpu1_intc 11 &cpu1_intc 9
>>> + &cpu2_intc 11 &cpu2_intc 9
>>> + &cpu3_intc 11 &cpu3_intc 9
>>> + &cpu4_intc 11 &cpu4_intc 9>;
>>> + };
>>> +
>>> + dma@3000000 {
>>> + compatible = "sifive,fu540-c000-pdma";
>>> + reg = <0x0 0x3000000 0x0 0x8000>;
>>> + interrupt-parent = <&plic>;
>>> + interrupts = <23 24 25 26 27 28 29 30>;
>>> + #dma-cells = <1>;
>>> + };
>>> +
>>> + refclk: refclk {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <600000000>;
>>> + clock-output-names = "msspllclk";
>>> + };
>>> +
>>> + clkcfg: clkcfg@20002000 {
>>> + compatible = "microchip,pfsoc-clkcfg";
>>> + reg = <0x0 0x20002000 0x0 0x1000>;
>>> + reg-names = "mss_sysreg";
>>> + clocks = <&refclk>;
>>> + #clock-cells = <1>;
>>> + clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", "MMUART2clk", "MMUART3clk", "MMUART4clk", "SPI0clk", "SPI1clk", "I2C0clk", "I2C1clk", "CAN0clk", "CAN1clk", "USBclk", "RESERVED", "RTCclk", "QSPIclk", "GPIO0clk", "GPIO1clk", "GPIO2clk", "DDRCclk", "FIC0clk", "FIC1clk", "FIC2clk", "FIC3clk", "ATHENAclk", "CFMclk";
>>
>> Any chance of making this list multi-line, it is difficult to read as-is.
>>
>
> Yes. We can also get rid of a few names that are not used. I will fix it in v2.
>
>>> + };
>>> +
>>> + serial0: serial@20000000 {
>>> + compatible = "ns16550a";
>>> + reg = <0x0 0x20000000 0x0 0x400>;
>>> + reg-io-width = <4>;
>>> + reg-shift = <2>;
>>> + interrupt-parent = <&plic>;
>>> + interrupts = <90>;
>>> + current-speed = <115200>;
>>> + clocks = <&clkcfg 8>;
>>> + status = "okay";
>>> + };
>>> +
>>> + serial1: serial@20100000 {
>>> + compatible = "ns16550a";
>>> + reg = <0x0 0x20100000 0x0 0x400>;
>>> + reg-io-width = <4>;
>>> + reg-shift = <2>;
>>> + interrupt-parent = <&plic>;
>>> + interrupts = <91>;
>>> + current-speed = <115200>;
>>> + clocks = <&clkcfg 9>;
>>> + status = "okay";
>>> + };
>>> +
>>> + serial2: serial@20102000 {
>>> + compatible = "ns16550a";
>>> + reg = <0x0 0x20102000 0x0 0x400>;
>>> + reg-io-width = <4>;
>>> + reg-shift = <2>;
>>> + interrupt-parent = <&plic>;
>>> + interrupts = <92>;
>>> + current-speed = <115200>;
>>> + clocks = <&clkcfg 10>;
>>> + status = "okay";
>>> + };
>>> +
>>> + serial3: serial@20104000 {
>>> + compatible = "ns16550a";
>>> + reg = <0x0 0x20104000 0x0 0x400>;
>>> + reg-io-width = <4>;
>>> + reg-shift = <2>;
>>> + interrupt-parent = <&plic>;
>>> + interrupts = <93>;
>>> + current-speed = <115200>;
>>> + clocks = <&clkcfg 11>;
>>> + status = "okay";
>>> + };
>>> +
>>> + sdcard: sdhc@20008000 {
>>> + compatible = "cdns,sd4hc";
>>> + reg = <0x0 0x20008000 0x0 0x1000>;
>>> + interrupt-parent = <&plic>;
>>> + interrupts = <88>;
>>> + pinctrl-names = "default";
>>> + clocks = <&clkcfg 6>;
>>> + bus-width = <4>;
>>> + disable-wp;
>>> + no-1-8-v;
>>> + cap-mmc-highspeed;
>>> + cap-sd-highspeed;
>>> + card-detect-delay = <200>;
>>> + sd-uhs-sdr12;
>>> + sd-uhs-sdr25;
>>> + sd-uhs-sdr50;
>>> + sd-uhs-sdr104;
>>> + max-frequency = <200000000>;
>>> + status = "okay";
>>> + };
>>
>> Given eMMC is the default device, shouldn't that be default for the
>> device tree too? Even if not, having the emmc node here would be a
>> good thing as it is different to the SD node.
>>
>
> I tested this device tree with sdcard. That's why, I just picked the
> sdcard node.
> I am not sure if both eMMC & sdcard node can co-exist. The polar fire
> soc github repo
> seems to point that both of them have the same address and only 1 can be enabled
> at that time. That may not be true now as the github repo has not been
> updated in
> couple of months.
>
> @Cyril : Can we enable both eMMC & sdcard at the same time ?
I would put /both/ in but only enable the one in use for the moment.
Our boards are booting of eMMC as supplied, so this isn't going to work
as well. The eMMC is 8bit wide, and thus is only delivering 11MB/sec
instead of 22MB/sec. This performance is still not great, but losing
half the data-rate is just not good.
>>> +
>>> + emac1: ethernet@20112000 {
>>> + compatible = "cdns,macb";
>>> + reg = <0x0 0x20112000 0x0 0x2000>;
>>> + interrupt-parent = <&plic>;
>>> + interrupts = <70 71 72 73>;
>>> + mac-address = [56 34 12 00 FC 00];
>>> + phy-mode = "sgmii";
>>> + clocks = <&clkcfg 5>, <&clkcfg 2>;
>>> + clock-names = "pclk", "hclk";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + phy1: ethernet-phy@9 {
>>> + reg = <9>;
>>> + ti,fifo-depth = <0x01>;
>>> + };
>>> + };
>>
>> Aren't there two ethernet ports on the board?
>>
>
> Yes. I hadn't tested that out. I will test it and add the 2nd one as well.
>
>> Also, at the moment u-boot is not filling the MAC address parameter
>> in so we've got at two boards on the network with the same MAC until
>> we override it in the device tree for the second.
>>
>
> Looking at latest U-Boot patches, it seems it updates the mac address
> from the serial number.
Ok, the one supplied on the boards does not. And the boards /both/ have
the same MAC address!
>>> +
>>> + uio_axi_lsram@2030000000 {
>>> + compatible = "generic-uio";
>>> + reg = <0x20 0x30000000 0 0x80000000 >;
>>> + status = "okay";
>>> + };
>>> + };
>>> +};
>>>
>>
>>
>> --
>> Ben Dooks http://www.codethink.co.uk/
>> Senior Engineer Codethink - Providing Genius
>>
>> https://www.codethink.co.uk/privacy.html
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
>
>
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-10-30 9:05 ` Anup Patel
2020-10-30 20:27 ` Atish Patra
@ 2020-10-30 21:20 ` Ben Dooks
2020-11-03 10:00 ` Bin Meng
2 siblings, 0 replies; 38+ messages in thread
From: Ben Dooks @ 2020-10-30 21:20 UTC (permalink / raw)
To: Anup Patel, Atish Patra
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel@vger.kernel.org List, Rob Herring, Alistair Francis,
Paul Walmsley, Palmer Dabbelt, linux-riscv, Padmarao Begari
On 30/10/2020 09:05, Anup Patel wrote:
> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <atish.patra@wdc.com> wrote:
>>
>> Add initial DTS for Microchip ICICLE board having only
>> essential devcies (clocks, sdhci, ethernet, serial, etc).
>>
>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
>> ---
>> arch/riscv/boot/dts/Makefile | 1 +
>> arch/riscv/boot/dts/microchip/Makefile | 2 +
>> .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
>
> I suggest we split this DTS into two parts:
> 1. SOC (microchip-polarfire.dtsi)
> 2. Board (microchip-icicle-kit-a000.dts)
I was just going to suggest that.
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC
2020-10-30 9:09 ` Anup Patel
@ 2020-10-30 21:21 ` Ben Dooks
0 siblings, 0 replies; 38+ messages in thread
From: Ben Dooks @ 2020-10-30 21:21 UTC (permalink / raw)
To: Anup Patel, Atish Patra
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel@vger.kernel.org List, Rob Herring, Alistair Francis,
Paul Walmsley, Palmer Dabbelt, linux-riscv, Padmarao Begari
On 30/10/2020 09:09, Anup Patel wrote:
> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <atish.patra@wdc.com> wrote:
>>
>> Enable Microchip PolarFire ICICLE soc config in defconfig.
>> It allows the default upstream kernel to boot on PolarFire ICICLE board.
>>
>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
>> ---
Is there going to be a git tree with all the necessary support for the
polarfire/icicle boards? I so far have updated yocto patches, a rebase
to v5.9 and the v17 PCIe patches (which still don't work for us)
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 1/3] RISC-V: Add Microchip PolarFire SoC kconfig option
2020-10-28 23:27 ` [RFC PATCH 1/3] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra
2020-10-30 9:08 ` Anup Patel
@ 2020-11-03 9:55 ` Bin Meng
2020-11-06 7:14 ` Palmer Dabbelt
2 siblings, 0 replies; 38+ messages in thread
From: Bin Meng @ 2020-11-03 9:55 UTC (permalink / raw)
To: Atish Patra
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel, Rob Herring, Alistair Francis, Paul Walmsley,
Palmer Dabbelt, linux-riscv, Padmarao Begari
On Thu, Oct 29, 2020 at 6:00 PM Atish Patra <atish.patra@wdc.com> wrote:
>
> Add Microchip PolarFire kconfig option which selects SoC specific
> and common drivers that is required for this SoC.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> arch/riscv/Kconfig.socs | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 8a55f6156661..74d07250ecc5 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -22,6 +22,13 @@ config SOC_VIRT
> help
> This enables support for QEMU Virt Machine.
>
> +config SOC_MICROCHIP_POLARFIRE
Please put this in the alphabetical order
> + bool "Microchip PolarFire SoCs"
> + select MCHP_CLK_PFSOC
> + select SIFIVE_PLIC
> + help
> + This enables support for Microchip PolarFire SoC platforms.
> +
> config SOC_KENDRYTE
> bool "Kendryte K210 SoC"
> depends on !MMU
> --
Otherwise LGTM
Reviewed-by: Bin Meng <bin.meng@windriver.com>
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-10-30 9:05 ` Anup Patel
2020-10-30 20:27 ` Atish Patra
2020-10-30 21:20 ` Ben Dooks
@ 2020-11-03 10:00 ` Bin Meng
2020-11-03 18:19 ` Cyril.Jean
2 siblings, 1 reply; 38+ messages in thread
From: Bin Meng @ 2020-11-03 10:00 UTC (permalink / raw)
To: Anup Patel
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel@vger.kernel.org List, Atish Patra, Rob Herring,
Alistair Francis, Paul Walmsley, Palmer Dabbelt, linux-riscv,
Padmarao Begari
On Fri, Oct 30, 2020 at 5:08 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <atish.patra@wdc.com> wrote:
> >
> > Add initial DTS for Microchip ICICLE board having only
> > essential devcies (clocks, sdhci, ethernet, serial, etc).
> >
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > ---
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/microchip/Makefile | 2 +
> > .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
>
> I suggest we split this DTS into two parts:
> 1. SOC (microchip-polarfire.dtsi)
> 2. Board (microchip-icicle-kit-a000.dts)
I also doubt what is the correct board name. I suspect the -a000 comes
from the SiFive board name convention, but does not apply to the
Icicle Kit board.
@Cyril, please confirm.
>
> This will be much cleaner and aligned with what is done
> on other architectures.
>
> > 3 files changed, 316 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> > create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >
Regards,
Bin
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC
2020-10-28 23:27 ` [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra
2020-10-30 9:09 ` Anup Patel
@ 2020-11-03 10:03 ` Bin Meng
2020-11-06 7:14 ` Palmer Dabbelt
2 siblings, 0 replies; 38+ messages in thread
From: Bin Meng @ 2020-11-03 10:03 UTC (permalink / raw)
To: Atish Patra
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel, Rob Herring, Alistair Francis, Paul Walmsley,
Palmer Dabbelt, linux-riscv, Padmarao Begari
On Thu, Oct 29, 2020 at 6:00 PM Atish Patra <atish.patra@wdc.com> wrote:
>
> Enable Microchip PolarFire ICICLE soc config in defconfig.
> It allows the default upstream kernel to boot on PolarFire ICICLE board.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> arch/riscv/configs/defconfig | 4 ++++
> 1 file changed, 4 insertions(+)
>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-10-30 20:27 ` Atish Patra
@ 2020-11-03 10:59 ` Ben Dooks
2020-11-03 15:08 ` Atish Patra
0 siblings, 1 reply; 38+ messages in thread
From: Ben Dooks @ 2020-11-03 10:59 UTC (permalink / raw)
To: Atish Patra, Anup Patel
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel@vger.kernel.org List, Atish Patra, Rob Herring,
Alistair Francis, Paul Walmsley, Palmer Dabbelt, linux-riscv,
Padmarao Begari
On 30/10/2020 20:27, Atish Patra wrote:
> On Fri, Oct 30, 2020 at 2:05 AM Anup Patel <anup@brainfault.org> wrote:
>>
>> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <atish.patra@wdc.com> wrote:
>>>
>>> Add initial DTS for Microchip ICICLE board having only
>>> essential devcies (clocks, sdhci, ethernet, serial, etc).
>>>
>>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
>>> ---
>>> arch/riscv/boot/dts/Makefile | 1 +
>>> arch/riscv/boot/dts/microchip/Makefile | 2 +
>>> .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
>>
>> I suggest we split this DTS into two parts:
>> 1. SOC (microchip-polarfire.dtsi)
>> 2. Board (microchip-icicle-kit-a000.dts)
>>
>> This will be much cleaner and aligned with what is done
>> on other architectures.
>>
>
> Sure. I will do that in v2.
>
>>> 3 files changed, 316 insertions(+)
>>> create mode 100644 arch/riscv/boot/dts/microchip/Makefile
>>> create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>>>
>>> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
>>> index ca1f8cbd78c0..3ea94ea0a18a 100644
>>> --- a/arch/riscv/boot/dts/Makefile
>>> +++ b/arch/riscv/boot/dts/Makefile
>>> @@ -1,5 +1,6 @@
>>> # SPDX-License-Identifier: GPL-2.0
>>> subdir-y += sifive
>>> subdir-y += kendryte
>>> +subdir-y += microchip
>>>
>>> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
>>> diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
>>> new file mode 100644
>>> index 000000000000..55ad77521304
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/dts/microchip/Makefile
>>> @@ -0,0 +1,2 @@
>>> +# SPDX-License-Identifier: GPL-2.0
>>> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
>>> diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>>> new file mode 100644
>>> index 000000000000..5848920af55c
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>>> @@ -0,0 +1,313 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/* Copyright (c) 2020 Microchip Technology Inc */
>>> +
>>> +/dts-v1/;
>>> +
>>> +/* Clock frequency (in Hz) of the rtcclk */
>>> +#define RTCCLK_FREQ 1000000
>>> +
>>> +/ {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + model = "Microchip PolarFire-SoC";
>>> + compatible = "microchip,polarfire-soc";
>>> +
>>> + chosen {
>>> + stdout-path = &serial0;
>>> + };
>>> +
>>> + cpus {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + timebase-frequency = <RTCCLK_FREQ>;
>>> +
>>> + cpu@0 {
>>> + clock-frequency = <0>;
>>> + compatible = "sifive,rocket0", "riscv";
>>> + device_type = "cpu";
>>> + i-cache-block-size = <64>;
>>> + i-cache-sets = <128>;
>>> + i-cache-size = <16384>;
>>> + reg = <0>;
>>> + riscv,isa = "rv64imac";
>>> + status = "disabled";
>>> +
>>> + cpu0_intc: interrupt-controller {
>>> + #interrupt-cells = <1>;
>>> + compatible = "riscv,cpu-intc";
>>> + interrupt-controller;
>>> + };
>>> + };
>>> +
>>> + cpu@1 {
>>> + clock-frequency = <0>;
>>> + compatible = "sifive,rocket0", "riscv";
>>> + d-cache-block-size = <64>;
>>> + d-cache-sets = <64>;
>>> + d-cache-size = <32768>;
>>> + d-tlb-sets = <1>;
>>> + d-tlb-size = <32>;
>>> + device_type = "cpu";
>>> + i-cache-block-size = <64>;
>>> + i-cache-sets = <64>;
>>> + i-cache-size = <32768>;
>>> + i-tlb-sets = <1>;
>>> + i-tlb-size = <32>;
>>> + mmu-type = "riscv,sv39";
>>> + reg = <1>;
>>> + riscv,isa = "rv64imafdc";
>>> + tlb-split;
>>> + status = "okay";
>>> +
>>> + cpu1_intc: interrupt-controller {
>>> + #interrupt-cells = <1>;
>>> + compatible = "riscv,cpu-intc";
>>> + interrupt-controller;
>>> + };
>>> + };
>>> +
>>> + cpu@2 {
>>> + clock-frequency = <0>;
>>> + compatible = "sifive,rocket0", "riscv";
>>> + d-cache-block-size = <64>;
>>> + d-cache-sets = <64>;
>>> + d-cache-size = <32768>;
>>> + d-tlb-sets = <1>;
>>> + d-tlb-size = <32>;
>>> + device_type = "cpu";
>>> + i-cache-block-size = <64>;
>>> + i-cache-sets = <64>;
>>> + i-cache-size = <32768>;
>>> + i-tlb-sets = <1>;
>>> + i-tlb-size = <32>;
>>> + mmu-type = "riscv,sv39";
>>> + reg = <2>;
>>> + riscv,isa = "rv64imafdc";
>>> + tlb-split;
>>> + status = "okay";
>>> +
>>> + cpu2_intc: interrupt-controller {
>>> + #interrupt-cells = <1>;
>>> + compatible = "riscv,cpu-intc";
>>> + interrupt-controller;
>>> + };
>>> + };
>>> +
>>> + cpu@3 {
>>> + clock-frequency = <0>;
>>> + compatible = "sifive,rocket0", "riscv";
>>> + d-cache-block-size = <64>;
>>> + d-cache-sets = <64>;
>>> + d-cache-size = <32768>;
>>> + d-tlb-sets = <1>;
>>> + d-tlb-size = <32>;
>>> + device_type = "cpu";
>>> + i-cache-block-size = <64>;
>>> + i-cache-sets = <64>;
>>> + i-cache-size = <32768>;
>>> + i-tlb-sets = <1>;
>>> + i-tlb-size = <32>;
>>> + mmu-type = "riscv,sv39";
>>> + reg = <3>;
>>> + riscv,isa = "rv64imafdc";
>>> + tlb-split;
>>> + status = "okay";
>>> +
>>> + cpu3_intc: interrupt-controller {
>>> + #interrupt-cells = <1>;
>>> + compatible = "riscv,cpu-intc";
>>> + interrupt-controller;
>>> + };
>>> + };
>>> +
>>> + cpu@4 {
>>> + clock-frequency = <0>;
>>> + compatible = "sifive,rocket0", "riscv";
>>> + d-cache-block-size = <64>;
>>> + d-cache-sets = <64>;
>>> + d-cache-size = <32768>;
>>> + d-tlb-sets = <1>;
>>> + d-tlb-size = <32>;
>>> + device_type = "cpu";
>>> + i-cache-block-size = <64>;
>>> + i-cache-sets = <64>;
>>> + i-cache-size = <32768>;
>>> + i-tlb-sets = <1>;
>>> + i-tlb-size = <32>;
>>> + mmu-type = "riscv,sv39";
>>> + reg = <4>;
>>> + riscv,isa = "rv64imafdc";
>>> + tlb-split;
>>> + status = "okay";
>>> + cpu4_intc: interrupt-controller {
>>> + #interrupt-cells = <1>;
>>> + compatible = "riscv,cpu-intc";
>>> + interrupt-controller;
>>> + };
>>> + };
>>> + };
>>> +
>>> + memory@80000000 {
>>> + device_type = "memory";
>>> + reg = <0x0 0x80000000 0x0 0x40000000>;
>>> + clocks = <&clkcfg 26>;
>>> + };
>>> +
>>> + soc {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + compatible = "simple-bus";
>>> + ranges;
>>> +
>>> + cache-controller@2010000 {
>>> + compatible = "sifive,fu540-c000-ccache", "cache";
>>> + cache-block-size = <64>;
>>> + cache-level = <2>;
>>> + cache-sets = <1024>;
>>> + cache-size = <2097152>;
>>> + cache-unified;
>>> + interrupt-parent = <&plic>;
>>> + interrupts = <1 2 3>;
>>> + reg = <0x0 0x2010000 0x0 0x1000>;
>>> + };
>>> +
>>> + clint@2000000 {
>>> + compatible = "riscv,clint0";
>>> + reg = <0x0 0x2000000 0x0 0xC000>;
>>> + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
>>> + &cpu1_intc 3 &cpu1_intc 7
>>> + &cpu2_intc 3 &cpu2_intc 7
>>> + &cpu3_intc 3 &cpu3_intc 7
>>> + &cpu4_intc 3 &cpu4_intc 7>;
>>> + };
>>> +
>>> + plic: interrupt-controller@c000000 {
>>> + #interrupt-cells = <1>;
>>> + compatible = "sifive,plic-1.0.0";
>>> + reg = <0x0 0xc000000 0x0 0x4000000>;
>>> + riscv,ndev = <53>;
>>> + interrupt-controller;
>>> + interrupts-extended = <&cpu0_intc 11
>>> + &cpu1_intc 11 &cpu1_intc 9
>>> + &cpu2_intc 11 &cpu2_intc 9
>>> + &cpu3_intc 11 &cpu3_intc 9
>>> + &cpu4_intc 11 &cpu4_intc 9>;
>>> + };
>>> +
>>> + dma@3000000 {
>>> + compatible = "sifive,fu540-c000-pdma";
>>> + reg = <0x0 0x3000000 0x0 0x8000>;
>>> + interrupt-parent = <&plic>;
>>> + interrupts = <23 24 25 26 27 28 29 30>;
>>> + #dma-cells = <1>;
>>> + };
>>> +
>>> + refclk: refclk {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <600000000>;
>>> + clock-output-names = "msspllclk";
>>> + };
>>> +
>>> + clkcfg: clkcfg@20002000 {
>>> + compatible = "microchip,pfsoc-clkcfg";
>>> + reg = <0x0 0x20002000 0x0 0x1000>;
>>> + reg-names = "mss_sysreg";
>>> + clocks = <&refclk>;
>>> + #clock-cells = <1>;
>>> + clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", "MMUART2clk", "MMUART3clk", "MMUART4clk", "SPI0clk", "SPI1clk", "I2C0clk", "I2C1clk", "CAN0clk", "CAN1clk", "USBclk", "RESERVED", "RTCclk", "QSPIclk", "GPIO0clk", "GPIO1clk", "GPIO2clk", "DDRCclk", "FIC0clk", "FIC1clk", "FIC2clk", "FIC3clk", "ATHENAclk", "CFMclk";
>>> + };
>>> +
H ow about doing something like
> clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", /* 0 -4 */
> "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", /* 5-9 */
this means we can easily work out what clocks are in which index
As per the previos email, I'd leave these all populated as coming back
and adding ones later is just going to be a pain with merge conflicts.
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
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linux-riscv@lists.infradead.org
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-10-30 21:19 ` Ben Dooks
@ 2020-11-03 15:07 ` Atish Patra
2020-11-03 15:19 ` Ben Dooks
2020-11-03 18:10 ` Cyril.Jean
0 siblings, 2 replies; 38+ messages in thread
From: Atish Patra @ 2020-11-03 15:07 UTC (permalink / raw)
To: Ben Dooks
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel@vger.kernel.org List, Atish Patra, Rob Herring,
Alistair Francis, Paul Walmsley, Palmer Dabbelt, linux-riscv,
Padmarao Begari
On Fri, Oct 30, 2020 at 2:20 PM Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>
> On 30/10/2020 07:11, Atish Patra wrote:
> > On Thu, Oct 29, 2020 at 3:24 AM Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> >>
> >> On 28/10/2020 23:27, Atish Patra wrote:
> >>> Add initial DTS for Microchip ICICLE board having only
> >>> essential devcies (clocks, sdhci, ethernet, serial, etc).
> >>>
> >>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> >>> ---
> >>> arch/riscv/boot/dts/Makefile | 1 +
> >>> arch/riscv/boot/dts/microchip/Makefile | 2 +
> >>> .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
> >>> 3 files changed, 316 insertions(+)
> >>> create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> >>> create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >>>
> >>> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> >>> index ca1f8cbd78c0..3ea94ea0a18a 100644
> >>> --- a/arch/riscv/boot/dts/Makefile
> >>> +++ b/arch/riscv/boot/dts/Makefile
> >>> @@ -1,5 +1,6 @@
> >>> # SPDX-License-Identifier: GPL-2.0
> >>> subdir-y += sifive
> >>> subdir-y += kendryte
> >>> +subdir-y += microchip
> >>>
> >>> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> >>> diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
> >>> new file mode 100644
> >>> index 000000000000..55ad77521304
> >>> --- /dev/null
> >>> +++ b/arch/riscv/boot/dts/microchip/Makefile
> >>> @@ -0,0 +1,2 @@
> >>> +# SPDX-License-Identifier: GPL-2.0
> >>> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
> >>> diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >>> new file mode 100644
> >>> index 000000000000..5848920af55c
> >>> --- /dev/null
> >>> +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >>> @@ -0,0 +1,313 @@
> >>> +// SPDX-License-Identifier: GPL-2.0+
> >>> +/* Copyright (c) 2020 Microchip Technology Inc */
> >>> +
> >>> +/dts-v1/;
> >>> +
> >>> +/* Clock frequency (in Hz) of the rtcclk */
> >>> +#define RTCCLK_FREQ 1000000
> >>> +
> >>> +/ {
> >>> + #address-cells = <2>;
> >>> + #size-cells = <2>;
> >>> + model = "Microchip PolarFire-SoC";
> >>> + compatible = "microchip,polarfire-soc";
> >>> +
> >>> + chosen {
> >>> + stdout-path = &serial0;
> >>> + };
> >>> +
> >>> + cpus {
> >>> + #address-cells = <1>;
> >>> + #size-cells = <0>;
> >>> + timebase-frequency = <RTCCLK_FREQ>;
> >>> +
> >>> + cpu@0 {
> >>> + clock-frequency = <0>;
> >>> + compatible = "sifive,rocket0", "riscv";
> >>> + device_type = "cpu";
> >>> + i-cache-block-size = <64>;
> >>> + i-cache-sets = <128>;
> >>> + i-cache-size = <16384>;
> >>> + reg = <0>;
> >>> + riscv,isa = "rv64imac";
> >>> + status = "disabled";
> >>> +
> >>> + cpu0_intc: interrupt-controller {
> >>> + #interrupt-cells = <1>;
> >>> + compatible = "riscv,cpu-intc";
> >>> + interrupt-controller;
> >>> + };
> >>> + };
> >>> +
> >>> + cpu@1 {
> >>> + clock-frequency = <0>;
> >>> + compatible = "sifive,rocket0", "riscv";
> >>> + d-cache-block-size = <64>;
> >>> + d-cache-sets = <64>;
> >>> + d-cache-size = <32768>;
> >>> + d-tlb-sets = <1>;
> >>> + d-tlb-size = <32>;
> >>> + device_type = "cpu";
> >>> + i-cache-block-size = <64>;
> >>> + i-cache-sets = <64>;
> >>> + i-cache-size = <32768>;
> >>> + i-tlb-sets = <1>;
> >>> + i-tlb-size = <32>;
> >>> + mmu-type = "riscv,sv39";
> >>> + reg = <1>;
> >>> + riscv,isa = "rv64imafdc";
> >>> + tlb-split;
> >>> + status = "okay";
> >>> +
> >>> + cpu1_intc: interrupt-controller {
> >>> + #interrupt-cells = <1>;
> >>> + compatible = "riscv,cpu-intc";
> >>> + interrupt-controller;
> >>> + };
> >>> + };
> >>> +
> >>> + cpu@2 {
> >>> + clock-frequency = <0>;
> >>> + compatible = "sifive,rocket0", "riscv";
> >>> + d-cache-block-size = <64>;
> >>> + d-cache-sets = <64>;
> >>> + d-cache-size = <32768>;
> >>> + d-tlb-sets = <1>;
> >>> + d-tlb-size = <32>;
> >>> + device_type = "cpu";
> >>> + i-cache-block-size = <64>;
> >>> + i-cache-sets = <64>;
> >>> + i-cache-size = <32768>;
> >>> + i-tlb-sets = <1>;
> >>> + i-tlb-size = <32>;
> >>> + mmu-type = "riscv,sv39";
> >>> + reg = <2>;
> >>> + riscv,isa = "rv64imafdc";
> >>> + tlb-split;
> >>> + status = "okay";
> >>> +
> >>> + cpu2_intc: interrupt-controller {
> >>> + #interrupt-cells = <1>;
> >>> + compatible = "riscv,cpu-intc";
> >>> + interrupt-controller;
> >>> + };
> >>> + };
> >>> +
> >>> + cpu@3 {
> >>> + clock-frequency = <0>;
> >>> + compatible = "sifive,rocket0", "riscv";
> >>> + d-cache-block-size = <64>;
> >>> + d-cache-sets = <64>;
> >>> + d-cache-size = <32768>;
> >>> + d-tlb-sets = <1>;
> >>> + d-tlb-size = <32>;
> >>> + device_type = "cpu";
> >>> + i-cache-block-size = <64>;
> >>> + i-cache-sets = <64>;
> >>> + i-cache-size = <32768>;
> >>> + i-tlb-sets = <1>;
> >>> + i-tlb-size = <32>;
> >>> + mmu-type = "riscv,sv39";
> >>> + reg = <3>;
> >>> + riscv,isa = "rv64imafdc";
> >>> + tlb-split;
> >>> + status = "okay";
> >>> +
> >>> + cpu3_intc: interrupt-controller {
> >>> + #interrupt-cells = <1>;
> >>> + compatible = "riscv,cpu-intc";
> >>> + interrupt-controller;
> >>> + };
> >>> + };
> >>> +
> >>> + cpu@4 {
> >>> + clock-frequency = <0>;
> >>> + compatible = "sifive,rocket0", "riscv";
> >>> + d-cache-block-size = <64>;
> >>> + d-cache-sets = <64>;
> >>> + d-cache-size = <32768>;
> >>> + d-tlb-sets = <1>;
> >>> + d-tlb-size = <32>;
> >>> + device_type = "cpu";
> >>> + i-cache-block-size = <64>;
> >>> + i-cache-sets = <64>;
> >>> + i-cache-size = <32768>;
> >>> + i-tlb-sets = <1>;
> >>> + i-tlb-size = <32>;
> >>> + mmu-type = "riscv,sv39";
> >>> + reg = <4>;
> >>> + riscv,isa = "rv64imafdc";
> >>> + tlb-split;
> >>> + status = "okay";
> >>> + cpu4_intc: interrupt-controller {
> >>> + #interrupt-cells = <1>;
> >>> + compatible = "riscv,cpu-intc";
> >>> + interrupt-controller;
> >>> + };
> >>> + };
> >>> + };
> >>> +
> >>> + memory@80000000 {
> >>> + device_type = "memory";
> >>> + reg = <0x0 0x80000000 0x0 0x40000000>;
> >>> + clocks = <&clkcfg 26>;
> >>> + };
> >>
> >> U-boot doesn't seem to be updating this properly.
> >>
> >> The board should have 2GiB, confirmed by looking at the device's
> >> chip markings. We only see 1GiB memory. The 0x80000000 bus window
> >> is only capable of dealing with 1GiB memory. The higher 64-bit one
> >> can have 16GiB mapped.
> >>
> >> Do we need a second node for the second GiB of memory?
> >>
> > We could just modify the reg size but to allow more memory. I tried
> > that for Linux but it didn't boot.
> > Probably, DDR init code in HSS only initialized 1GB of memory.
>
> Yes, it is only looking at the low window which is 1GiB max.
> If it used the upper window it would get the 16GiB.
>
> I don't know how no-one noticed this issue before shipping a board
> out with this. I have updated the firmware on my second board but
> this only seems to currently fix a reboot issue with the eMMC.
>
We can't update the DT for Linux until there is a public release of
the updated firmware
with 2GB enabled.
> >>> +
> >>> + soc {
> >>> + #address-cells = <2>;
> >>> + #size-cells = <2>;
> >>> + compatible = "simple-bus";
> >>> + ranges;
> >>> +
> >>> + cache-controller@2010000 {
> >>> + compatible = "sifive,fu540-c000-ccache", "cache";
> >>> + cache-block-size = <64>;
> >>> + cache-level = <2>;
> >>> + cache-sets = <1024>;
> >>> + cache-size = <2097152>;
> >>> + cache-unified;
> >>> + interrupt-parent = <&plic>;
> >>> + interrupts = <1 2 3>;
> >>> + reg = <0x0 0x2010000 0x0 0x1000>;
> >>> + };
> >>> +
> >>> + clint@2000000 {
> >>> + compatible = "riscv,clint0";
> >>> + reg = <0x0 0x2000000 0x0 0xC000>;
> >>> + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
> >>> + &cpu1_intc 3 &cpu1_intc 7
> >>> + &cpu2_intc 3 &cpu2_intc 7
> >>> + &cpu3_intc 3 &cpu3_intc 7
> >>> + &cpu4_intc 3 &cpu4_intc 7>;
> >>> + };
> >>> +
> >>> + plic: interrupt-controller@c000000 {
> >>> + #interrupt-cells = <1>;
> >>> + compatible = "sifive,plic-1.0.0";
> >>> + reg = <0x0 0xc000000 0x0 0x4000000>;
> >>> + riscv,ndev = <53>;
> >>> + interrupt-controller;
> >>> + interrupts-extended = <&cpu0_intc 11
> >>> + &cpu1_intc 11 &cpu1_intc 9
> >>> + &cpu2_intc 11 &cpu2_intc 9
> >>> + &cpu3_intc 11 &cpu3_intc 9
> >>> + &cpu4_intc 11 &cpu4_intc 9>;
> >>> + };
> >>> +
> >>> + dma@3000000 {
> >>> + compatible = "sifive,fu540-c000-pdma";
> >>> + reg = <0x0 0x3000000 0x0 0x8000>;
> >>> + interrupt-parent = <&plic>;
> >>> + interrupts = <23 24 25 26 27 28 29 30>;
> >>> + #dma-cells = <1>;
> >>> + };
> >>> +
> >>> + refclk: refclk {
> >>> + compatible = "fixed-clock";
> >>> + #clock-cells = <0>;
> >>> + clock-frequency = <600000000>;
> >>> + clock-output-names = "msspllclk";
> >>> + };
> >>> +
> >>> + clkcfg: clkcfg@20002000 {
> >>> + compatible = "microchip,pfsoc-clkcfg";
> >>> + reg = <0x0 0x20002000 0x0 0x1000>;
> >>> + reg-names = "mss_sysreg";
> >>> + clocks = <&refclk>;
> >>> + #clock-cells = <1>;
> >>> + clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", "MMUART2clk", "MMUART3clk", "MMUART4clk", "SPI0clk", "SPI1clk", "I2C0clk", "I2C1clk", "CAN0clk", "CAN1clk", "USBclk", "RESERVED", "RTCclk", "QSPIclk", "GPIO0clk", "GPIO1clk", "GPIO2clk", "DDRCclk", "FIC0clk", "FIC1clk", "FIC2clk", "FIC3clk", "ATHENAclk", "CFMclk";
> >>
> >> Any chance of making this list multi-line, it is difficult to read as-is.
> >>
> >
> > Yes. We can also get rid of a few names that are not used. I will fix it in v2.
> >
> >>> + };
> >>> +
> >>> + serial0: serial@20000000 {
> >>> + compatible = "ns16550a";
> >>> + reg = <0x0 0x20000000 0x0 0x400>;
> >>> + reg-io-width = <4>;
> >>> + reg-shift = <2>;
> >>> + interrupt-parent = <&plic>;
> >>> + interrupts = <90>;
> >>> + current-speed = <115200>;
> >>> + clocks = <&clkcfg 8>;
> >>> + status = "okay";
> >>> + };
> >>> +
> >>> + serial1: serial@20100000 {
> >>> + compatible = "ns16550a";
> >>> + reg = <0x0 0x20100000 0x0 0x400>;
> >>> + reg-io-width = <4>;
> >>> + reg-shift = <2>;
> >>> + interrupt-parent = <&plic>;
> >>> + interrupts = <91>;
> >>> + current-speed = <115200>;
> >>> + clocks = <&clkcfg 9>;
> >>> + status = "okay";
> >>> + };
> >>> +
> >>> + serial2: serial@20102000 {
> >>> + compatible = "ns16550a";
> >>> + reg = <0x0 0x20102000 0x0 0x400>;
> >>> + reg-io-width = <4>;
> >>> + reg-shift = <2>;
> >>> + interrupt-parent = <&plic>;
> >>> + interrupts = <92>;
> >>> + current-speed = <115200>;
> >>> + clocks = <&clkcfg 10>;
> >>> + status = "okay";
> >>> + };
> >>> +
> >>> + serial3: serial@20104000 {
> >>> + compatible = "ns16550a";
> >>> + reg = <0x0 0x20104000 0x0 0x400>;
> >>> + reg-io-width = <4>;
> >>> + reg-shift = <2>;
> >>> + interrupt-parent = <&plic>;
> >>> + interrupts = <93>;
> >>> + current-speed = <115200>;
> >>> + clocks = <&clkcfg 11>;
> >>> + status = "okay";
> >>> + };
> >>> +
> >>> + sdcard: sdhc@20008000 {
> >>> + compatible = "cdns,sd4hc";
> >>> + reg = <0x0 0x20008000 0x0 0x1000>;
> >>> + interrupt-parent = <&plic>;
> >>> + interrupts = <88>;
> >>> + pinctrl-names = "default";
> >>> + clocks = <&clkcfg 6>;
> >>> + bus-width = <4>;
> >>> + disable-wp;
> >>> + no-1-8-v;
> >>> + cap-mmc-highspeed;
> >>> + cap-sd-highspeed;
> >>> + card-detect-delay = <200>;
> >>> + sd-uhs-sdr12;
> >>> + sd-uhs-sdr25;
> >>> + sd-uhs-sdr50;
> >>> + sd-uhs-sdr104;
> >>> + max-frequency = <200000000>;
> >>> + status = "okay";
> >>> + };
> >>
> >> Given eMMC is the default device, shouldn't that be default for the
> >> device tree too? Even if not, having the emmc node here would be a
> >> good thing as it is different to the SD node.
> >>
> >
> > I tested this device tree with sdcard. That's why, I just picked the
> > sdcard node.
> > I am not sure if both eMMC & sdcard node can co-exist. The polar fire
> > soc github repo
> > seems to point that both of them have the same address and only 1 can be enabled
> > at that time. That may not be true now as the github repo has not been
> > updated in
> > couple of months.
> >
> > @Cyril : Can we enable both eMMC & sdcard at the same time ?
>
> I would put /both/ in but only enable the one in use for the moment.
> Our boards are booting of eMMC as supplied, so this isn't going to work
> as well. The eMMC is 8bit wide, and thus is only delivering 11MB/sec
> instead of 22MB/sec. This performance is still not great, but losing
> half the data-rate is just not good.
>
I am not sure what should be enabled by default. Updating sdcard is much
easier than eMMC card and we use that approach.
@Cyril: Is there a way that we can enable both ?
> >>> +
> >>> + emac1: ethernet@20112000 {
> >>> + compatible = "cdns,macb";
> >>> + reg = <0x0 0x20112000 0x0 0x2000>;
> >>> + interrupt-parent = <&plic>;
> >>> + interrupts = <70 71 72 73>;
> >>> + mac-address = [56 34 12 00 FC 00];
> >>> + phy-mode = "sgmii";
> >>> + clocks = <&clkcfg 5>, <&clkcfg 2>;
> >>> + clock-names = "pclk", "hclk";
> >>> + #address-cells = <1>;
> >>> + #size-cells = <0>;
> >>> + phy1: ethernet-phy@9 {
> >>> + reg = <9>;
> >>> + ti,fifo-depth = <0x01>;
> >>> + };
> >>> + };
> >>
> >> Aren't there two ethernet ports on the board?
> >>
> >
> > Yes. I hadn't tested that out. I will test it and add the 2nd one as well.
> >
> >> Also, at the moment u-boot is not filling the MAC address parameter
> >> in so we've got at two boards on the network with the same MAC until
> >> we override it in the device tree for the second.
> >>
> >
> > Looking at latest U-Boot patches, it seems it updates the mac address
> > from the serial number.
>
> Ok, the one supplied on the boards does not. And the boards /both/ have
> the same MAC address!
>
Yeah. That one is hard coded. I think that will be fixed with U-Boot patches.
We can just leave them all 0s in Linux DT.
> >>> +
> >>> + uio_axi_lsram@2030000000 {
> >>> + compatible = "generic-uio";
> >>> + reg = <0x20 0x30000000 0 0x80000000 >;
> >>> + status = "okay";
> >>> + };
> >>> + };
> >>> +};
> >>>
> >>
> >>
> >> --
> >> Ben Dooks http://www.codethink.co.uk/
> >> Senior Engineer Codethink - Providing Genius
> >>
> >> https://www.codethink.co.uk/privacy.html
> >>
> >> _______________________________________________
> >> linux-riscv mailing list
> >> linux-riscv@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-riscv
> >
> >
> >
>
>
> --
> Ben Dooks http://www.codethink.co.uk/
> Senior Engineer Codethink - Providing Genius
>
> https://www.codethink.co.uk/privacy.html
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-11-03 10:59 ` Ben Dooks
@ 2020-11-03 15:08 ` Atish Patra
0 siblings, 0 replies; 38+ messages in thread
From: Atish Patra @ 2020-11-03 15:08 UTC (permalink / raw)
To: Ben Dooks
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
Anup Patel, linux-kernel@vger.kernel.org List, Atish Patra,
Rob Herring, Alistair Francis, Paul Walmsley, Palmer Dabbelt,
linux-riscv, Padmarao Begari
On Tue, Nov 3, 2020 at 2:59 AM Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>
> On 30/10/2020 20:27, Atish Patra wrote:
> > On Fri, Oct 30, 2020 at 2:05 AM Anup Patel <anup@brainfault.org> wrote:
> >>
> >> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <atish.patra@wdc.com> wrote:
> >>>
> >>> Add initial DTS for Microchip ICICLE board having only
> >>> essential devcies (clocks, sdhci, ethernet, serial, etc).
> >>>
> >>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> >>> ---
> >>> arch/riscv/boot/dts/Makefile | 1 +
> >>> arch/riscv/boot/dts/microchip/Makefile | 2 +
> >>> .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
> >>
> >> I suggest we split this DTS into two parts:
> >> 1. SOC (microchip-polarfire.dtsi)
> >> 2. Board (microchip-icicle-kit-a000.dts)
> >>
> >> This will be much cleaner and aligned with what is done
> >> on other architectures.
> >>
> >
> > Sure. I will do that in v2.
> >
> >>> 3 files changed, 316 insertions(+)
> >>> create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> >>> create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >>>
> >>> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> >>> index ca1f8cbd78c0..3ea94ea0a18a 100644
> >>> --- a/arch/riscv/boot/dts/Makefile
> >>> +++ b/arch/riscv/boot/dts/Makefile
> >>> @@ -1,5 +1,6 @@
> >>> # SPDX-License-Identifier: GPL-2.0
> >>> subdir-y += sifive
> >>> subdir-y += kendryte
> >>> +subdir-y += microchip
> >>>
> >>> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> >>> diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
> >>> new file mode 100644
> >>> index 000000000000..55ad77521304
> >>> --- /dev/null
> >>> +++ b/arch/riscv/boot/dts/microchip/Makefile
> >>> @@ -0,0 +1,2 @@
> >>> +# SPDX-License-Identifier: GPL-2.0
> >>> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
> >>> diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >>> new file mode 100644
> >>> index 000000000000..5848920af55c
> >>> --- /dev/null
> >>> +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >>> @@ -0,0 +1,313 @@
> >>> +// SPDX-License-Identifier: GPL-2.0+
> >>> +/* Copyright (c) 2020 Microchip Technology Inc */
> >>> +
> >>> +/dts-v1/;
> >>> +
> >>> +/* Clock frequency (in Hz) of the rtcclk */
> >>> +#define RTCCLK_FREQ 1000000
> >>> +
> >>> +/ {
> >>> + #address-cells = <2>;
> >>> + #size-cells = <2>;
> >>> + model = "Microchip PolarFire-SoC";
> >>> + compatible = "microchip,polarfire-soc";
> >>> +
> >>> + chosen {
> >>> + stdout-path = &serial0;
> >>> + };
> >>> +
> >>> + cpus {
> >>> + #address-cells = <1>;
> >>> + #size-cells = <0>;
> >>> + timebase-frequency = <RTCCLK_FREQ>;
> >>> +
> >>> + cpu@0 {
> >>> + clock-frequency = <0>;
> >>> + compatible = "sifive,rocket0", "riscv";
> >>> + device_type = "cpu";
> >>> + i-cache-block-size = <64>;
> >>> + i-cache-sets = <128>;
> >>> + i-cache-size = <16384>;
> >>> + reg = <0>;
> >>> + riscv,isa = "rv64imac";
> >>> + status = "disabled";
> >>> +
> >>> + cpu0_intc: interrupt-controller {
> >>> + #interrupt-cells = <1>;
> >>> + compatible = "riscv,cpu-intc";
> >>> + interrupt-controller;
> >>> + };
> >>> + };
> >>> +
> >>> + cpu@1 {
> >>> + clock-frequency = <0>;
> >>> + compatible = "sifive,rocket0", "riscv";
> >>> + d-cache-block-size = <64>;
> >>> + d-cache-sets = <64>;
> >>> + d-cache-size = <32768>;
> >>> + d-tlb-sets = <1>;
> >>> + d-tlb-size = <32>;
> >>> + device_type = "cpu";
> >>> + i-cache-block-size = <64>;
> >>> + i-cache-sets = <64>;
> >>> + i-cache-size = <32768>;
> >>> + i-tlb-sets = <1>;
> >>> + i-tlb-size = <32>;
> >>> + mmu-type = "riscv,sv39";
> >>> + reg = <1>;
> >>> + riscv,isa = "rv64imafdc";
> >>> + tlb-split;
> >>> + status = "okay";
> >>> +
> >>> + cpu1_intc: interrupt-controller {
> >>> + #interrupt-cells = <1>;
> >>> + compatible = "riscv,cpu-intc";
> >>> + interrupt-controller;
> >>> + };
> >>> + };
> >>> +
> >>> + cpu@2 {
> >>> + clock-frequency = <0>;
> >>> + compatible = "sifive,rocket0", "riscv";
> >>> + d-cache-block-size = <64>;
> >>> + d-cache-sets = <64>;
> >>> + d-cache-size = <32768>;
> >>> + d-tlb-sets = <1>;
> >>> + d-tlb-size = <32>;
> >>> + device_type = "cpu";
> >>> + i-cache-block-size = <64>;
> >>> + i-cache-sets = <64>;
> >>> + i-cache-size = <32768>;
> >>> + i-tlb-sets = <1>;
> >>> + i-tlb-size = <32>;
> >>> + mmu-type = "riscv,sv39";
> >>> + reg = <2>;
> >>> + riscv,isa = "rv64imafdc";
> >>> + tlb-split;
> >>> + status = "okay";
> >>> +
> >>> + cpu2_intc: interrupt-controller {
> >>> + #interrupt-cells = <1>;
> >>> + compatible = "riscv,cpu-intc";
> >>> + interrupt-controller;
> >>> + };
> >>> + };
> >>> +
> >>> + cpu@3 {
> >>> + clock-frequency = <0>;
> >>> + compatible = "sifive,rocket0", "riscv";
> >>> + d-cache-block-size = <64>;
> >>> + d-cache-sets = <64>;
> >>> + d-cache-size = <32768>;
> >>> + d-tlb-sets = <1>;
> >>> + d-tlb-size = <32>;
> >>> + device_type = "cpu";
> >>> + i-cache-block-size = <64>;
> >>> + i-cache-sets = <64>;
> >>> + i-cache-size = <32768>;
> >>> + i-tlb-sets = <1>;
> >>> + i-tlb-size = <32>;
> >>> + mmu-type = "riscv,sv39";
> >>> + reg = <3>;
> >>> + riscv,isa = "rv64imafdc";
> >>> + tlb-split;
> >>> + status = "okay";
> >>> +
> >>> + cpu3_intc: interrupt-controller {
> >>> + #interrupt-cells = <1>;
> >>> + compatible = "riscv,cpu-intc";
> >>> + interrupt-controller;
> >>> + };
> >>> + };
> >>> +
> >>> + cpu@4 {
> >>> + clock-frequency = <0>;
> >>> + compatible = "sifive,rocket0", "riscv";
> >>> + d-cache-block-size = <64>;
> >>> + d-cache-sets = <64>;
> >>> + d-cache-size = <32768>;
> >>> + d-tlb-sets = <1>;
> >>> + d-tlb-size = <32>;
> >>> + device_type = "cpu";
> >>> + i-cache-block-size = <64>;
> >>> + i-cache-sets = <64>;
> >>> + i-cache-size = <32768>;
> >>> + i-tlb-sets = <1>;
> >>> + i-tlb-size = <32>;
> >>> + mmu-type = "riscv,sv39";
> >>> + reg = <4>;
> >>> + riscv,isa = "rv64imafdc";
> >>> + tlb-split;
> >>> + status = "okay";
> >>> + cpu4_intc: interrupt-controller {
> >>> + #interrupt-cells = <1>;
> >>> + compatible = "riscv,cpu-intc";
> >>> + interrupt-controller;
> >>> + };
> >>> + };
> >>> + };
> >>> +
> >>> + memory@80000000 {
> >>> + device_type = "memory";
> >>> + reg = <0x0 0x80000000 0x0 0x40000000>;
> >>> + clocks = <&clkcfg 26>;
> >>> + };
> >>> +
> >>> + soc {
> >>> + #address-cells = <2>;
> >>> + #size-cells = <2>;
> >>> + compatible = "simple-bus";
> >>> + ranges;
> >>> +
> >>> + cache-controller@2010000 {
> >>> + compatible = "sifive,fu540-c000-ccache", "cache";
> >>> + cache-block-size = <64>;
> >>> + cache-level = <2>;
> >>> + cache-sets = <1024>;
> >>> + cache-size = <2097152>;
> >>> + cache-unified;
> >>> + interrupt-parent = <&plic>;
> >>> + interrupts = <1 2 3>;
> >>> + reg = <0x0 0x2010000 0x0 0x1000>;
> >>> + };
> >>> +
> >>> + clint@2000000 {
> >>> + compatible = "riscv,clint0";
> >>> + reg = <0x0 0x2000000 0x0 0xC000>;
> >>> + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
> >>> + &cpu1_intc 3 &cpu1_intc 7
> >>> + &cpu2_intc 3 &cpu2_intc 7
> >>> + &cpu3_intc 3 &cpu3_intc 7
> >>> + &cpu4_intc 3 &cpu4_intc 7>;
> >>> + };
> >>> +
> >>> + plic: interrupt-controller@c000000 {
> >>> + #interrupt-cells = <1>;
> >>> + compatible = "sifive,plic-1.0.0";
> >>> + reg = <0x0 0xc000000 0x0 0x4000000>;
> >>> + riscv,ndev = <53>;
> >>> + interrupt-controller;
> >>> + interrupts-extended = <&cpu0_intc 11
> >>> + &cpu1_intc 11 &cpu1_intc 9
> >>> + &cpu2_intc 11 &cpu2_intc 9
> >>> + &cpu3_intc 11 &cpu3_intc 9
> >>> + &cpu4_intc 11 &cpu4_intc 9>;
> >>> + };
> >>> +
> >>> + dma@3000000 {
> >>> + compatible = "sifive,fu540-c000-pdma";
> >>> + reg = <0x0 0x3000000 0x0 0x8000>;
> >>> + interrupt-parent = <&plic>;
> >>> + interrupts = <23 24 25 26 27 28 29 30>;
> >>> + #dma-cells = <1>;
> >>> + };
> >>> +
> >>> + refclk: refclk {
> >>> + compatible = "fixed-clock";
> >>> + #clock-cells = <0>;
> >>> + clock-frequency = <600000000>;
> >>> + clock-output-names = "msspllclk";
> >>> + };
> >>> +
> >>> + clkcfg: clkcfg@20002000 {
> >>> + compatible = "microchip,pfsoc-clkcfg";
> >>> + reg = <0x0 0x20002000 0x0 0x1000>;
> >>> + reg-names = "mss_sysreg";
> >>> + clocks = <&refclk>;
> >>> + #clock-cells = <1>;
> >>> + clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", "MMUART2clk", "MMUART3clk", "MMUART4clk", "SPI0clk", "SPI1clk", "I2C0clk", "I2C1clk", "CAN0clk", "CAN1clk", "USBclk", "RESERVED", "RTCclk", "QSPIclk", "GPIO0clk", "GPIO1clk", "GPIO2clk", "DDRCclk", "FIC0clk", "FIC1clk", "FIC2clk", "FIC3clk", "ATHENAclk", "CFMclk";
> >>> + };
> >>> +
>
> H ow about doing something like
> > clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", /* 0 -4 */
> > "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", /* 5-9 */
>
> this means we can easily work out what clocks are in which index
>
> As per the previos email, I'd leave these all populated as coming back
> and adding ones later is just going to be a pain with merge conflicts.
>
Sounds good to me.
>
>
> --
> Ben Dooks http://www.codethink.co.uk/
> Senior Engineer Codethink - Providing Genius
>
> https://www.codethink.co.uk/privacy.html
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-11-03 15:07 ` Atish Patra
@ 2020-11-03 15:19 ` Ben Dooks
2020-11-03 18:10 ` Cyril.Jean
1 sibling, 0 replies; 38+ messages in thread
From: Ben Dooks @ 2020-11-03 15:19 UTC (permalink / raw)
To: Atish Patra
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel@vger.kernel.org List, Atish Patra, Rob Herring,
Alistair Francis, Paul Walmsley, Palmer Dabbelt, linux-riscv,
Padmarao Begari
On 03/11/2020 15:07, Atish Patra wrote:
>>> We could just modify the reg size but to allow more memory. I tried
>>> that for Linux but it didn't boot.
>>> Probably, DDR init code in HSS only initialized 1GB of memory.
>> Yes, it is only looking at the low window which is 1GiB max.
>> If it used the upper window it would get the 16GiB.
>>
>> I don't know how no-one noticed this issue before shipping a board
>> out with this. I have updated the firmware on my second board but
>> this only seems to currently fix a reboot issue with the eMMC.
>>
> We can't update the DT for Linux until there is a public release of
> the updated firmware
> with 2GB enabled.
Yeah, it is really annoying the boards turned up with a number of
issues including the half memory.
I assume there will be a new release of HSS and U-boot which at
worse can insert new memory nodes into the device tree.
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-11-03 15:07 ` Atish Patra
2020-11-03 15:19 ` Ben Dooks
@ 2020-11-03 18:10 ` Cyril.Jean
2020-11-03 18:28 ` Ben Dooks
1 sibling, 1 reply; 38+ messages in thread
From: Cyril.Jean @ 2020-11-03 18:10 UTC (permalink / raw)
To: atishp, ben.dooks
Cc: devicetree, aou, Daire.McNamara, anup.patel, linux-kernel,
atish.patra, robh+dt, alistair.francis, paul.walmsley, palmer,
linux-riscv, Padmarao.Begari
On 11/3/20 3:07 PM, Atish Patra wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Fri, Oct 30, 2020 at 2:20 PM Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>> On 30/10/2020 07:11, Atish Patra wrote:
>>> On Thu, Oct 29, 2020 at 3:24 AM Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>>>> On 28/10/2020 23:27, Atish Patra wrote:
>>>>> Add initial DTS for Microchip ICICLE board having only
>>>>> essential devcies (clocks, sdhci, ethernet, serial, etc).
>>>>>
>>>>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
>>>>> ---
>>>>> arch/riscv/boot/dts/Makefile | 1 +
>>>>> arch/riscv/boot/dts/microchip/Makefile | 2 +
>>>>> .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
>>>>> 3 files changed, 316 insertions(+)
>>>>> create mode 100644 arch/riscv/boot/dts/microchip/Makefile
>>>>> create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>>>>>
>>>>> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
>>>>> index ca1f8cbd78c0..3ea94ea0a18a 100644
>>>>> --- a/arch/riscv/boot/dts/Makefile
>>>>> +++ b/arch/riscv/boot/dts/Makefile
>>>>> @@ -1,5 +1,6 @@
>>>>> # SPDX-License-Identifier: GPL-2.0
>>>>> subdir-y += sifive
>>>>> subdir-y += kendryte
>>>>> +subdir-y += microchip
>>>>>
>>>>> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
>>>>> diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
>>>>> new file mode 100644
>>>>> index 000000000000..55ad77521304
>>>>> --- /dev/null
>>>>> +++ b/arch/riscv/boot/dts/microchip/Makefile
>>>>> @@ -0,0 +1,2 @@
>>>>> +# SPDX-License-Identifier: GPL-2.0
>>>>> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
>>>>> diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>>>>> new file mode 100644
>>>>> index 000000000000..5848920af55c
>>>>> --- /dev/null
>>>>> +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>>>>> @@ -0,0 +1,313 @@
>>>>> +// SPDX-License-Identifier: GPL-2.0+
>>>>> +/* Copyright (c) 2020 Microchip Technology Inc */
>>>>> +
>>>>> +/dts-v1/;
>>>>> +
>>>>> +/* Clock frequency (in Hz) of the rtcclk */
>>>>> +#define RTCCLK_FREQ 1000000
>>>>> +
>>>>> +/ {
>>>>> + #address-cells = <2>;
>>>>> + #size-cells = <2>;
>>>>> + model = "Microchip PolarFire-SoC";
>>>>> + compatible = "microchip,polarfire-soc";
>>>>> +
>>>>> + chosen {
>>>>> + stdout-path = &serial0;
>>>>> + };
>>>>> +
>>>>> + cpus {
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> + timebase-frequency = <RTCCLK_FREQ>;
>>>>> +
>>>>> + cpu@0 {
>>>>> + clock-frequency = <0>;
>>>>> + compatible = "sifive,rocket0", "riscv";
>>>>> + device_type = "cpu";
>>>>> + i-cache-block-size = <64>;
>>>>> + i-cache-sets = <128>;
>>>>> + i-cache-size = <16384>;
>>>>> + reg = <0>;
>>>>> + riscv,isa = "rv64imac";
>>>>> + status = "disabled";
>>>>> +
>>>>> + cpu0_intc: interrupt-controller {
>>>>> + #interrupt-cells = <1>;
>>>>> + compatible = "riscv,cpu-intc";
>>>>> + interrupt-controller;
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + cpu@1 {
>>>>> + clock-frequency = <0>;
>>>>> + compatible = "sifive,rocket0", "riscv";
>>>>> + d-cache-block-size = <64>;
>>>>> + d-cache-sets = <64>;
>>>>> + d-cache-size = <32768>;
>>>>> + d-tlb-sets = <1>;
>>>>> + d-tlb-size = <32>;
>>>>> + device_type = "cpu";
>>>>> + i-cache-block-size = <64>;
>>>>> + i-cache-sets = <64>;
>>>>> + i-cache-size = <32768>;
>>>>> + i-tlb-sets = <1>;
>>>>> + i-tlb-size = <32>;
>>>>> + mmu-type = "riscv,sv39";
>>>>> + reg = <1>;
>>>>> + riscv,isa = "rv64imafdc";
>>>>> + tlb-split;
>>>>> + status = "okay";
>>>>> +
>>>>> + cpu1_intc: interrupt-controller {
>>>>> + #interrupt-cells = <1>;
>>>>> + compatible = "riscv,cpu-intc";
>>>>> + interrupt-controller;
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + cpu@2 {
>>>>> + clock-frequency = <0>;
>>>>> + compatible = "sifive,rocket0", "riscv";
>>>>> + d-cache-block-size = <64>;
>>>>> + d-cache-sets = <64>;
>>>>> + d-cache-size = <32768>;
>>>>> + d-tlb-sets = <1>;
>>>>> + d-tlb-size = <32>;
>>>>> + device_type = "cpu";
>>>>> + i-cache-block-size = <64>;
>>>>> + i-cache-sets = <64>;
>>>>> + i-cache-size = <32768>;
>>>>> + i-tlb-sets = <1>;
>>>>> + i-tlb-size = <32>;
>>>>> + mmu-type = "riscv,sv39";
>>>>> + reg = <2>;
>>>>> + riscv,isa = "rv64imafdc";
>>>>> + tlb-split;
>>>>> + status = "okay";
>>>>> +
>>>>> + cpu2_intc: interrupt-controller {
>>>>> + #interrupt-cells = <1>;
>>>>> + compatible = "riscv,cpu-intc";
>>>>> + interrupt-controller;
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + cpu@3 {
>>>>> + clock-frequency = <0>;
>>>>> + compatible = "sifive,rocket0", "riscv";
>>>>> + d-cache-block-size = <64>;
>>>>> + d-cache-sets = <64>;
>>>>> + d-cache-size = <32768>;
>>>>> + d-tlb-sets = <1>;
>>>>> + d-tlb-size = <32>;
>>>>> + device_type = "cpu";
>>>>> + i-cache-block-size = <64>;
>>>>> + i-cache-sets = <64>;
>>>>> + i-cache-size = <32768>;
>>>>> + i-tlb-sets = <1>;
>>>>> + i-tlb-size = <32>;
>>>>> + mmu-type = "riscv,sv39";
>>>>> + reg = <3>;
>>>>> + riscv,isa = "rv64imafdc";
>>>>> + tlb-split;
>>>>> + status = "okay";
>>>>> +
>>>>> + cpu3_intc: interrupt-controller {
>>>>> + #interrupt-cells = <1>;
>>>>> + compatible = "riscv,cpu-intc";
>>>>> + interrupt-controller;
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + cpu@4 {
>>>>> + clock-frequency = <0>;
>>>>> + compatible = "sifive,rocket0", "riscv";
>>>>> + d-cache-block-size = <64>;
>>>>> + d-cache-sets = <64>;
>>>>> + d-cache-size = <32768>;
>>>>> + d-tlb-sets = <1>;
>>>>> + d-tlb-size = <32>;
>>>>> + device_type = "cpu";
>>>>> + i-cache-block-size = <64>;
>>>>> + i-cache-sets = <64>;
>>>>> + i-cache-size = <32768>;
>>>>> + i-tlb-sets = <1>;
>>>>> + i-tlb-size = <32>;
>>>>> + mmu-type = "riscv,sv39";
>>>>> + reg = <4>;
>>>>> + riscv,isa = "rv64imafdc";
>>>>> + tlb-split;
>>>>> + status = "okay";
>>>>> + cpu4_intc: interrupt-controller {
>>>>> + #interrupt-cells = <1>;
>>>>> + compatible = "riscv,cpu-intc";
>>>>> + interrupt-controller;
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + memory@80000000 {
>>>>> + device_type = "memory";
>>>>> + reg = <0x0 0x80000000 0x0 0x40000000>;
>>>>> + clocks = <&clkcfg 26>;
>>>>> + };
>>>> U-boot doesn't seem to be updating this properly.
>>>>
>>>> The board should have 2GiB, confirmed by looking at the device's
>>>> chip markings. We only see 1GiB memory. The 0x80000000 bus window
>>>> is only capable of dealing with 1GiB memory. The higher 64-bit one
>>>> can have 16GiB mapped.
>>>>
>>>> Do we need a second node for the second GiB of memory?
>>>>
>>> We could just modify the reg size but to allow more memory. I tried
>>> that for Linux but it didn't boot.
>>> Probably, DDR init code in HSS only initialized 1GB of memory.
>> Yes, it is only looking at the low window which is 1GiB max.
>> If it used the upper window it would get the 16GiB.
>>
>> I don't know how no-one noticed this issue before shipping a board
>> out with this. I have updated the firmware on my second board but
>> this only seems to currently fix a reboot issue with the eMMC.
>>
> We can't update the DT for Linux until there is a public release of
> the updated firmware
> with 2GB enabled.
>
>>>>> +
>>>>> + soc {
>>>>> + #address-cells = <2>;
>>>>> + #size-cells = <2>;
>>>>> + compatible = "simple-bus";
>>>>> + ranges;
>>>>> +
>>>>> + cache-controller@2010000 {
>>>>> + compatible = "sifive,fu540-c000-ccache", "cache";
>>>>> + cache-block-size = <64>;
>>>>> + cache-level = <2>;
>>>>> + cache-sets = <1024>;
>>>>> + cache-size = <2097152>;
>>>>> + cache-unified;
>>>>> + interrupt-parent = <&plic>;
>>>>> + interrupts = <1 2 3>;
>>>>> + reg = <0x0 0x2010000 0x0 0x1000>;
>>>>> + };
>>>>> +
>>>>> + clint@2000000 {
>>>>> + compatible = "riscv,clint0";
>>>>> + reg = <0x0 0x2000000 0x0 0xC000>;
>>>>> + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
>>>>> + &cpu1_intc 3 &cpu1_intc 7
>>>>> + &cpu2_intc 3 &cpu2_intc 7
>>>>> + &cpu3_intc 3 &cpu3_intc 7
>>>>> + &cpu4_intc 3 &cpu4_intc 7>;
>>>>> + };
>>>>> +
>>>>> + plic: interrupt-controller@c000000 {
>>>>> + #interrupt-cells = <1>;
>>>>> + compatible = "sifive,plic-1.0.0";
>>>>> + reg = <0x0 0xc000000 0x0 0x4000000>;
>>>>> + riscv,ndev = <53>;
>>>>> + interrupt-controller;
>>>>> + interrupts-extended = <&cpu0_intc 11
>>>>> + &cpu1_intc 11 &cpu1_intc 9
>>>>> + &cpu2_intc 11 &cpu2_intc 9
>>>>> + &cpu3_intc 11 &cpu3_intc 9
>>>>> + &cpu4_intc 11 &cpu4_intc 9>;
>>>>> + };
>>>>> +
>>>>> + dma@3000000 {
>>>>> + compatible = "sifive,fu540-c000-pdma";
>>>>> + reg = <0x0 0x3000000 0x0 0x8000>;
>>>>> + interrupt-parent = <&plic>;
>>>>> + interrupts = <23 24 25 26 27 28 29 30>;
>>>>> + #dma-cells = <1>;
>>>>> + };
>>>>> +
>>>>> + refclk: refclk {
>>>>> + compatible = "fixed-clock";
>>>>> + #clock-cells = <0>;
>>>>> + clock-frequency = <600000000>;
>>>>> + clock-output-names = "msspllclk";
>>>>> + };
>>>>> +
>>>>> + clkcfg: clkcfg@20002000 {
>>>>> + compatible = "microchip,pfsoc-clkcfg";
>>>>> + reg = <0x0 0x20002000 0x0 0x1000>;
>>>>> + reg-names = "mss_sysreg";
>>>>> + clocks = <&refclk>;
>>>>> + #clock-cells = <1>;
>>>>> + clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", "MMUART2clk", "MMUART3clk", "MMUART4clk", "SPI0clk", "SPI1clk", "I2C0clk", "I2C1clk", "CAN0clk", "CAN1clk", "USBclk", "RESERVED", "RTCclk", "QSPIclk", "GPIO0clk", "GPIO1clk", "GPIO2clk", "DDRCclk", "FIC0clk", "FIC1clk", "FIC2clk", "FIC3clk", "ATHENAclk", "CFMclk";
>>>> Any chance of making this list multi-line, it is difficult to read as-is.
>>>>
>>> Yes. We can also get rid of a few names that are not used. I will fix it in v2.
>>>
>>>>> + };
>>>>> +
>>>>> + serial0: serial@20000000 {
>>>>> + compatible = "ns16550a";
>>>>> + reg = <0x0 0x20000000 0x0 0x400>;
>>>>> + reg-io-width = <4>;
>>>>> + reg-shift = <2>;
>>>>> + interrupt-parent = <&plic>;
>>>>> + interrupts = <90>;
>>>>> + current-speed = <115200>;
>>>>> + clocks = <&clkcfg 8>;
>>>>> + status = "okay";
>>>>> + };
>>>>> +
>>>>> + serial1: serial@20100000 {
>>>>> + compatible = "ns16550a";
>>>>> + reg = <0x0 0x20100000 0x0 0x400>;
>>>>> + reg-io-width = <4>;
>>>>> + reg-shift = <2>;
>>>>> + interrupt-parent = <&plic>;
>>>>> + interrupts = <91>;
>>>>> + current-speed = <115200>;
>>>>> + clocks = <&clkcfg 9>;
>>>>> + status = "okay";
>>>>> + };
>>>>> +
>>>>> + serial2: serial@20102000 {
>>>>> + compatible = "ns16550a";
>>>>> + reg = <0x0 0x20102000 0x0 0x400>;
>>>>> + reg-io-width = <4>;
>>>>> + reg-shift = <2>;
>>>>> + interrupt-parent = <&plic>;
>>>>> + interrupts = <92>;
>>>>> + current-speed = <115200>;
>>>>> + clocks = <&clkcfg 10>;
>>>>> + status = "okay";
>>>>> + };
>>>>> +
>>>>> + serial3: serial@20104000 {
>>>>> + compatible = "ns16550a";
>>>>> + reg = <0x0 0x20104000 0x0 0x400>;
>>>>> + reg-io-width = <4>;
>>>>> + reg-shift = <2>;
>>>>> + interrupt-parent = <&plic>;
>>>>> + interrupts = <93>;
>>>>> + current-speed = <115200>;
>>>>> + clocks = <&clkcfg 11>;
>>>>> + status = "okay";
>>>>> + };
>>>>> +
>>>>> + sdcard: sdhc@20008000 {
>>>>> + compatible = "cdns,sd4hc";
>>>>> + reg = <0x0 0x20008000 0x0 0x1000>;
>>>>> + interrupt-parent = <&plic>;
>>>>> + interrupts = <88>;
>>>>> + pinctrl-names = "default";
>>>>> + clocks = <&clkcfg 6>;
>>>>> + bus-width = <4>;
>>>>> + disable-wp;
>>>>> + no-1-8-v;
>>>>> + cap-mmc-highspeed;
>>>>> + cap-sd-highspeed;
>>>>> + card-detect-delay = <200>;
>>>>> + sd-uhs-sdr12;
>>>>> + sd-uhs-sdr25;
>>>>> + sd-uhs-sdr50;
>>>>> + sd-uhs-sdr104;
>>>>> + max-frequency = <200000000>;
>>>>> + status = "okay";
>>>>> + };
>>>> Given eMMC is the default device, shouldn't that be default for the
>>>> device tree too? Even if not, having the emmc node here would be a
>>>> good thing as it is different to the SD node.
>>>>
>>> I tested this device tree with sdcard. That's why, I just picked the
>>> sdcard node.
>>> I am not sure if both eMMC & sdcard node can co-exist. The polar fire
>>> soc github repo
>>> seems to point that both of them have the same address and only 1 can be enabled
>>> at that time. That may not be true now as the github repo has not been
>>> updated in
>>> couple of months.
>>>
>>> @Cyril : Can we enable both eMMC & sdcard at the same time ?
>> I would put /both/ in but only enable the one in use for the moment.
>> Our boards are booting of eMMC as supplied, so this isn't going to work
>> as well. The eMMC is 8bit wide, and thus is only delivering 11MB/sec
>> instead of 22MB/sec. This performance is still not great, but losing
>> half the data-rate is just not good.
>>
> I am not sure what should be enabled by default. Updating sdcard is much
> easier than eMMC card and we use that approach.
>
> @Cyril: Is there a way that we can enable both ?
>
Yes, we can enable both but this requires a modification to the FPGA
design. One of the guys prototyped this while I was away. We will move
this along. This will require reprogramming the FPGA with a new design
and HSS version.
Regards,
Cyril.
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-11-03 10:00 ` Bin Meng
@ 2020-11-03 18:19 ` Cyril.Jean
2020-11-03 18:38 ` Atish Patra
0 siblings, 1 reply; 38+ messages in thread
From: Cyril.Jean @ 2020-11-03 18:19 UTC (permalink / raw)
To: bmeng.cn, anup
Cc: devicetree, aou, Daire.McNamara, anup.patel, linux-kernel,
atish.patra, robh+dt, alistair.francis, paul.walmsley, palmer,
linux-riscv, Padmarao.Begari
On 11/3/20 10:00 AM, Bin Meng wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Fri, Oct 30, 2020 at 5:08 PM Anup Patel <anup@brainfault.org> wrote:
>> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <atish.patra@wdc.com> wrote:
>>> Add initial DTS for Microchip ICICLE board having only
>>> essential devcies (clocks, sdhci, ethernet, serial, etc).
>>>
>>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
>>> ---
>>> arch/riscv/boot/dts/Makefile | 1 +
>>> arch/riscv/boot/dts/microchip/Makefile | 2 +
>>> .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
>> I suggest we split this DTS into two parts:
>> 1. SOC (microchip-polarfire.dtsi)
>> 2. Board (microchip-icicle-kit-a000.dts)
> I also doubt what is the correct board name. I suspect the -a000 comes
> from the SiFive board name convention, but does not apply to the
> Icicle Kit board.
>
> @Cyril, please confirm.
>
Correct. Sorry Padmarao, I missed that one.
Regards,
Cyril.
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-11-03 18:10 ` Cyril.Jean
@ 2020-11-03 18:28 ` Ben Dooks
2020-11-03 18:36 ` Atish Patra
2020-11-03 18:40 ` Cyril.Jean
0 siblings, 2 replies; 38+ messages in thread
From: Ben Dooks @ 2020-11-03 18:28 UTC (permalink / raw)
To: Cyril.Jean, atishp
Cc: devicetree, aou, Daire.McNamara, anup.patel, linux-kernel,
atish.patra, robh+dt, alistair.francis, paul.walmsley, palmer,
linux-riscv, Padmarao.Begari
On 03/11/2020 18:10, Cyril.Jean@microchip.com wrote:
> On 11/3/20 3:07 PM, Atish Patra wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On Fri, Oct 30, 2020 at 2:20 PM Ben Dooks <ben.dooks@codethink.co.uk> wrote:
,snip[
>>>> @Cyril : Can we enable both eMMC & sdcard at the same time ?
>>> I would put /both/ in but only enable the one in use for the moment.
>>> Our boards are booting of eMMC as supplied, so this isn't going to work
>>> as well. The eMMC is 8bit wide, and thus is only delivering 11MB/sec
>>> instead of 22MB/sec. This performance is still not great, but losing
>>> half the data-rate is just not good.
>>>
>> I am not sure what should be enabled by default. Updating sdcard is much
>> easier than eMMC card and we use that approach.
>>
>> @Cyril: Is there a way that we can enable both ?
>>
> Yes, we can enable both but this requires a modification to the FPGA
> design. One of the guys prototyped this while I was away. We will move
> this along. This will require reprogramming the FPGA with a new design
> and HSS version.
>
> Regards,
>
> Cyril.
I either missed or couldn't find a way of forcing the boot mode to be
from the SD slot. Have I missed something? At the moment we'd like to
have more storage available as the ~7G free on the eMMC is not enough.
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-11-03 18:28 ` Ben Dooks
@ 2020-11-03 18:36 ` Atish Patra
2020-11-03 18:39 ` Ben Dooks
2020-11-03 18:40 ` Cyril.Jean
1 sibling, 1 reply; 38+ messages in thread
From: Atish Patra @ 2020-11-03 18:36 UTC (permalink / raw)
To: Ben Dooks
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel@vger.kernel.org List, Atish Patra, Rob Herring,
Alistair Francis, Paul Walmsley, Palmer Dabbelt, linux-riscv,
Padmarao Begari
On Tue, Nov 3, 2020 at 10:28 AM Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>
> On 03/11/2020 18:10, Cyril.Jean@microchip.com wrote:
> > On 11/3/20 3:07 PM, Atish Patra wrote:
> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>
> >> On Fri, Oct 30, 2020 at 2:20 PM Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>
> ,snip[
>
> >>>> @Cyril : Can we enable both eMMC & sdcard at the same time ?
> >>> I would put /both/ in but only enable the one in use for the moment.
> >>> Our boards are booting of eMMC as supplied, so this isn't going to work
> >>> as well. The eMMC is 8bit wide, and thus is only delivering 11MB/sec
> >>> instead of 22MB/sec. This performance is still not great, but losing
> >>> half the data-rate is just not good.
> >>>
> >> I am not sure what should be enabled by default. Updating sdcard is much
> >> easier than eMMC card and we use that approach.
> >>
> >> @Cyril: Is there a way that we can enable both ?
> >>
> > Yes, we can enable both but this requires a modification to the FPGA
> > design. One of the guys prototyped this while I was away. We will move
> > this along. This will require reprogramming the FPGA with a new design
> > and HSS version.
> >
> > Regards,
> >
> > Cyril.
>
> I either missed or couldn't find a way of forcing the boot mode to be
> from the SD slot. Have I missed something? At the moment we'd like to
> have more storage available as the ~7G free on the eMMC is not enough.
>
I use tftpboot to load the kernel & DT from the network. SD card is
enabled in this DT and Linux
kernel uses SD slot instead of eMMC.
To summarize, eMMC is used for HSS & U-Boot while SD card is used for
Linux which makes
more storage available to Linux.
IMO, we should enable the sdcard for Linux DT until updated FPGA
design & HSS is available.
> --
> Ben Dooks http://www.codethink.co.uk/
> Senior Engineer Codethink - Providing Genius
>
> https://www.codethink.co.uk/privacy.html
--
Regards,
Atish
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-11-03 18:19 ` Cyril.Jean
@ 2020-11-03 18:38 ` Atish Patra
2020-11-03 18:50 ` Cyril.Jean
0 siblings, 1 reply; 38+ messages in thread
From: Atish Patra @ 2020-11-03 18:38 UTC (permalink / raw)
To: Cyril.Jean
Cc: devicetree, Albert Ou, Daire McNamara, Anup Patel, Anup Patel,
linux-kernel@vger.kernel.org List, Atish Patra, Rob Herring,
Alistair Francis, Paul Walmsley, Palmer Dabbelt, linux-riscv,
Bin Meng, Padmarao Begari
On Tue, Nov 3, 2020 at 10:19 AM <Cyril.Jean@microchip.com> wrote:
>
> On 11/3/20 10:00 AM, Bin Meng wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On Fri, Oct 30, 2020 at 5:08 PM Anup Patel <anup@brainfault.org> wrote:
> >> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <atish.patra@wdc.com> wrote:
> >>> Add initial DTS for Microchip ICICLE board having only
> >>> essential devcies (clocks, sdhci, ethernet, serial, etc).
> >>>
> >>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> >>> ---
> >>> arch/riscv/boot/dts/Makefile | 1 +
> >>> arch/riscv/boot/dts/microchip/Makefile | 2 +
> >>> .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
> >> I suggest we split this DTS into two parts:
> >> 1. SOC (microchip-polarfire.dtsi)
> >> 2. Board (microchip-icicle-kit-a000.dts)
> > I also doubt what is the correct board name. I suspect the -a000 comes
> > from the SiFive board name convention, but does not apply to the
> > Icicle Kit board.
> >
> > @Cyril, please confirm.
> >
> Correct. Sorry Padmarao, I missed that one.
>
Ok. I picked that one from U-Boot. What should be the correct board
name in that case ?
microchip-pfsoc-icicle-kit ?
>
> Regards,
>
> Cyril.
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
--
Regards,
Atish
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-11-03 18:36 ` Atish Patra
@ 2020-11-03 18:39 ` Ben Dooks
2020-11-03 18:45 ` Atish Patra
0 siblings, 1 reply; 38+ messages in thread
From: Ben Dooks @ 2020-11-03 18:39 UTC (permalink / raw)
To: Atish Patra
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel@vger.kernel.org List, Atish Patra, Rob Herring,
Alistair Francis, Paul Walmsley, Palmer Dabbelt, linux-riscv,
Padmarao Begari
On 03/11/2020 18:36, Atish Patra wrote:
> On Tue, Nov 3, 2020 at 10:28 AM Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>>
>> On 03/11/2020 18:10, Cyril.Jean@microchip.com wrote:
>>> On 11/3/20 3:07 PM, Atish Patra wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> On Fri, Oct 30, 2020 at 2:20 PM Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>>
>> ,snip[
>>
>>>>>> @Cyril : Can we enable both eMMC & sdcard at the same time ?
>>>>> I would put /both/ in but only enable the one in use for the moment.
>>>>> Our boards are booting of eMMC as supplied, so this isn't going to work
>>>>> as well. The eMMC is 8bit wide, and thus is only delivering 11MB/sec
>>>>> instead of 22MB/sec. This performance is still not great, but losing
>>>>> half the data-rate is just not good.
>>>>>
>>>> I am not sure what should be enabled by default. Updating sdcard is much
>>>> easier than eMMC card and we use that approach.
>>>>
>>>> @Cyril: Is there a way that we can enable both ?
>>>>
>>> Yes, we can enable both but this requires a modification to the FPGA
>>> design. One of the guys prototyped this while I was away. We will move
>>> this along. This will require reprogramming the FPGA with a new design
>>> and HSS version.
>>>
>>> Regards,
>>>
>>> Cyril.
>>
>> I either missed or couldn't find a way of forcing the boot mode to be
>> from the SD slot. Have I missed something? At the moment we'd like to
>> have more storage available as the ~7G free on the eMMC is not enough.
>>
>
> I use tftpboot to load the kernel & DT from the network. SD card is
> enabled in this DT and Linux
> kernel uses SD slot instead of eMMC.
>
> To summarize, eMMC is used for HSS & U-Boot while SD card is used for
> Linux which makes
> more storage available to Linux.
>
> IMO, we should enable the sdcard for Linux DT until updated FPGA
> design & HSS is available.
Interesting as for me the default is for Linux to use the eMMC as
well. I can't see any way for forcing the selection lines in the
DT to say eMMC vs SD.
If there is a way of controlling the selection lines then it might
be possible to have both cards enabled with a bus selection MUX in
software.
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-11-03 18:28 ` Ben Dooks
2020-11-03 18:36 ` Atish Patra
@ 2020-11-03 18:40 ` Cyril.Jean
2020-11-03 18:46 ` Ben Dooks
1 sibling, 1 reply; 38+ messages in thread
From: Cyril.Jean @ 2020-11-03 18:40 UTC (permalink / raw)
To: ben.dooks, atishp
Cc: devicetree, aou, Daire.McNamara, anup.patel, linux-kernel,
atish.patra, robh+dt, alistair.francis, paul.walmsley, palmer,
linux-riscv, Padmarao.Begari
On 11/3/20 6:28 PM, Ben Dooks wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know
> the content is safe
>
> On 03/11/2020 18:10, Cyril.Jean@microchip.com wrote:
>> On 11/3/20 3:07 PM, Atish Patra wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you
>>> know the content is safe
>>>
>>> On Fri, Oct 30, 2020 at 2:20 PM Ben Dooks
>>> <ben.dooks@codethink.co.uk> wrote:
>
> ,snip[
>
>>>>> @Cyril : Can we enable both eMMC & sdcard at the same time ?
>>>> I would put /both/ in but only enable the one in use for the moment.
>>>> Our boards are booting of eMMC as supplied, so this isn't going to
>>>> work
>>>> as well. The eMMC is 8bit wide, and thus is only delivering 11MB/sec
>>>> instead of 22MB/sec. This performance is still not great, but losing
>>>> half the data-rate is just not good.
>>>>
>>> I am not sure what should be enabled by default. Updating sdcard is
>>> much
>>> easier than eMMC card and we use that approach.
>>>
>>> @Cyril: Is there a way that we can enable both ?
>>>
>> Yes, we can enable both but this requires a modification to the FPGA
>> design. One of the guys prototyped this while I was away. We will move
>> this along. This will require reprogramming the FPGA with a new design
>> and HSS version.
>>
>> Regards,
>>
>> Cyril.
>
> I either missed or couldn't find a way of forcing the boot mode to be
> from the SD slot. Have I missed something? At the moment we'd like to
> have more storage available as the ~7G free on the eMMC is not enough.
>
Currently, you need to program a different FPGA bitstream on the board
to boot from SD-card. The different bitstream configures muxes on the
board to connect the SD slot to the FPGA and the HSS included in the bit
stream configures the FPGA IOs correctly.
Links to the programming files are found in this document:
https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
Regards,
Cyril.
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-11-03 18:39 ` Ben Dooks
@ 2020-11-03 18:45 ` Atish Patra
0 siblings, 0 replies; 38+ messages in thread
From: Atish Patra @ 2020-11-03 18:45 UTC (permalink / raw)
To: Ben Dooks
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel@vger.kernel.org List, Atish Patra, Rob Herring,
Alistair Francis, Paul Walmsley, Palmer Dabbelt, linux-riscv,
Padmarao Begari
On Tue, Nov 3, 2020 at 10:39 AM Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>
> On 03/11/2020 18:36, Atish Patra wrote:
> > On Tue, Nov 3, 2020 at 10:28 AM Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> >>
> >> On 03/11/2020 18:10, Cyril.Jean@microchip.com wrote:
> >>> On 11/3/20 3:07 PM, Atish Patra wrote:
> >>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>>>
> >>>> On Fri, Oct 30, 2020 at 2:20 PM Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> >>
> >> ,snip[
> >>
> >>>>>> @Cyril : Can we enable both eMMC & sdcard at the same time ?
> >>>>> I would put /both/ in but only enable the one in use for the moment.
> >>>>> Our boards are booting of eMMC as supplied, so this isn't going to work
> >>>>> as well. The eMMC is 8bit wide, and thus is only delivering 11MB/sec
> >>>>> instead of 22MB/sec. This performance is still not great, but losing
> >>>>> half the data-rate is just not good.
> >>>>>
> >>>> I am not sure what should be enabled by default. Updating sdcard is much
> >>>> easier than eMMC card and we use that approach.
> >>>>
> >>>> @Cyril: Is there a way that we can enable both ?
> >>>>
> >>> Yes, we can enable both but this requires a modification to the FPGA
> >>> design. One of the guys prototyped this while I was away. We will move
> >>> this along. This will require reprogramming the FPGA with a new design
> >>> and HSS version.
> >>>
> >>> Regards,
> >>>
> >>> Cyril.
> >>
> >> I either missed or couldn't find a way of forcing the boot mode to be
> >> from the SD slot. Have I missed something? At the moment we'd like to
> >> have more storage available as the ~7G free on the eMMC is not enough.
> >>
> >
> > I use tftpboot to load the kernel & DT from the network. SD card is
> > enabled in this DT and Linux
> > kernel uses SD slot instead of eMMC.
> >
> > To summarize, eMMC is used for HSS & U-Boot while SD card is used for
> > Linux which makes
> > more storage available to Linux.
> >
> > IMO, we should enable the sdcard for Linux DT until updated FPGA
> > design & HSS is available.
>
> Interesting as for me the default is for Linux to use the eMMC as
> well. I can't see any way for forcing the selection lines in the
> DT to say eMMC vs SD.
>
because you are probably loading the DT passed by U-boot. I load the DTB
built from the Linux source (the one present in this patch) by
stopping the autoboot in U-Boot.
The DT in U-Boot disables the SD card.
> If there is a way of controlling the selection lines then it might
> be possible to have both cards enabled with a bus selection MUX in
> software.
>
>
> --
> Ben Dooks http://www.codethink.co.uk/
> Senior Engineer Codethink - Providing Genius
>
> https://www.codethink.co.uk/privacy.html
--
Regards,
Atish
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-11-03 18:40 ` Cyril.Jean
@ 2020-11-03 18:46 ` Ben Dooks
0 siblings, 0 replies; 38+ messages in thread
From: Ben Dooks @ 2020-11-03 18:46 UTC (permalink / raw)
To: Cyril.Jean, atishp
Cc: devicetree, aou, Daire.McNamara, anup.patel, linux-kernel,
atish.patra, robh+dt, alistair.francis, paul.walmsley, palmer,
linux-riscv, Padmarao.Begari
On 03/11/2020 18:40, Cyril.Jean@microchip.com wrote:
> On 11/3/20 6:28 PM, Ben Dooks wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know
>> the content is safe
>>
>> On 03/11/2020 18:10, Cyril.Jean@microchip.com wrote:
>>> On 11/3/20 3:07 PM, Atish Patra wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you
>>>> know the content is safe
>>>>
>>>> On Fri, Oct 30, 2020 at 2:20 PM Ben Dooks
>>>> <ben.dooks@codethink.co.uk> wrote:
>>
>> ,snip[
>>
>>>>>> @Cyril : Can we enable both eMMC & sdcard at the same time ?
>>>>> I would put /both/ in but only enable the one in use for the moment.
>>>>> Our boards are booting of eMMC as supplied, so this isn't going to
>>>>> work
>>>>> as well. The eMMC is 8bit wide, and thus is only delivering 11MB/sec
>>>>> instead of 22MB/sec. This performance is still not great, but losing
>>>>> half the data-rate is just not good.
>>>>>
>>>> I am not sure what should be enabled by default. Updating sdcard is
>>>> much
>>>> easier than eMMC card and we use that approach.
>>>>
>>>> @Cyril: Is there a way that we can enable both ?
>>>>
>>> Yes, we can enable both but this requires a modification to the FPGA
>>> design. One of the guys prototyped this while I was away. We will move
>>> this along. This will require reprogramming the FPGA with a new design
>>> and HSS version.
>>>
>>> Regards,
>>>
>>> Cyril.
>>
>> I either missed or couldn't find a way of forcing the boot mode to be
>> from the SD slot. Have I missed something? At the moment we'd like to
>> have more storage available as the ~7G free on the eMMC is not enough.
>>
> Currently, you need to program a different FPGA bitstream on the board
> to boot from SD-card. The different bitstream configures muxes on the
> board to connect the SD slot to the FPGA and the HSS included in the bit
> stream configures the FPGA IOs correctly.
>
> Links to the programming files are found in this document:
> https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
Thanks, but i've no way of remotely re-writing the bitstream
of the FPGA since the tools are x86 only and we're using a Pi3
to connect the boards we have to the network.
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-11-03 18:38 ` Atish Patra
@ 2020-11-03 18:50 ` Cyril.Jean
2020-11-03 19:02 ` Atish Patra
0 siblings, 1 reply; 38+ messages in thread
From: Cyril.Jean @ 2020-11-03 18:50 UTC (permalink / raw)
To: atishp
Cc: devicetree, aou, Daire.McNamara, anup, anup.patel, linux-kernel,
atish.patra, robh+dt, alistair.francis, paul.walmsley, palmer,
linux-riscv, bmeng.cn, Padmarao.Begari
On 11/3/20 6:38 PM, Atish Patra wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Tue, Nov 3, 2020 at 10:19 AM <Cyril.Jean@microchip.com> wrote:
>> On 11/3/20 10:00 AM, Bin Meng wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On Fri, Oct 30, 2020 at 5:08 PM Anup Patel <anup@brainfault.org> wrote:
>>>> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <atish.patra@wdc.com> wrote:
>>>>> Add initial DTS for Microchip ICICLE board having only
>>>>> essential devcies (clocks, sdhci, ethernet, serial, etc).
>>>>>
>>>>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
>>>>> ---
>>>>> arch/riscv/boot/dts/Makefile | 1 +
>>>>> arch/riscv/boot/dts/microchip/Makefile | 2 +
>>>>> .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
>>>> I suggest we split this DTS into two parts:
>>>> 1. SOC (microchip-polarfire.dtsi)
>>>> 2. Board (microchip-icicle-kit-a000.dts)
>>> I also doubt what is the correct board name. I suspect the -a000 comes
>>> from the SiFive board name convention, but does not apply to the
>>> Icicle Kit board.
>>>
>>> @Cyril, please confirm.
>>>
>> Correct. Sorry Padmarao, I missed that one.
>>
> Ok. I picked that one from U-Boot. What should be the correct board
> name in that case ?
>
> microchip-pfsoc-icicle-kit ?
My preference would go for microchip-mpfs-icicle-kit. I prefer "mpfs"
over "pfsoc" as "mpfs" is the part number prefix for the PolarFire SoC
device family.
Regards,
Cyril.
_______________________________________________
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linux-riscv@lists.infradead.org
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-11-03 18:50 ` Cyril.Jean
@ 2020-11-03 19:02 ` Atish Patra
0 siblings, 0 replies; 38+ messages in thread
From: Atish Patra @ 2020-11-03 19:02 UTC (permalink / raw)
To: Cyril.Jean
Cc: devicetree, Albert Ou, Daire McNamara, Anup Patel, Anup Patel,
linux-kernel@vger.kernel.org List, Atish Patra, Rob Herring,
Alistair Francis, Paul Walmsley, Palmer Dabbelt, linux-riscv,
Bin Meng, Padmarao Begari
On Tue, Nov 3, 2020 at 10:50 AM <Cyril.Jean@microchip.com> wrote:
>
> On 11/3/20 6:38 PM, Atish Patra wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On Tue, Nov 3, 2020 at 10:19 AM <Cyril.Jean@microchip.com> wrote:
> >> On 11/3/20 10:00 AM, Bin Meng wrote:
> >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>>
> >>> On Fri, Oct 30, 2020 at 5:08 PM Anup Patel <anup@brainfault.org> wrote:
> >>>> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <atish.patra@wdc.com> wrote:
> >>>>> Add initial DTS for Microchip ICICLE board having only
> >>>>> essential devcies (clocks, sdhci, ethernet, serial, etc).
> >>>>>
> >>>>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> >>>>> ---
> >>>>> arch/riscv/boot/dts/Makefile | 1 +
> >>>>> arch/riscv/boot/dts/microchip/Makefile | 2 +
> >>>>> .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
> >>>> I suggest we split this DTS into two parts:
> >>>> 1. SOC (microchip-polarfire.dtsi)
> >>>> 2. Board (microchip-icicle-kit-a000.dts)
> >>> I also doubt what is the correct board name. I suspect the -a000 comes
> >>> from the SiFive board name convention, but does not apply to the
> >>> Icicle Kit board.
> >>>
> >>> @Cyril, please confirm.
> >>>
> >> Correct. Sorry Padmarao, I missed that one.
> >>
> > Ok. I picked that one from U-Boot. What should be the correct board
> > name in that case ?
> >
> > microchip-pfsoc-icicle-kit ?
>
> My preference would go for microchip-mpfs-icicle-kit. I prefer "mpfs"
> over "pfsoc" as "mpfs" is the part number prefix for the PolarFire SoC
> device family.
>
Sure. I will update accordingly. Thanks for the quick feedback.
>
> Regards,
>
> Cyril.
>
>
--
Regards,
Atish
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-10-29 10:24 ` Ben Dooks
2020-10-30 7:11 ` Atish Patra
@ 2020-11-04 2:41 ` Bin Meng
1 sibling, 0 replies; 38+ messages in thread
From: Bin Meng @ 2020-11-04 2:41 UTC (permalink / raw)
To: Ben Dooks
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel, Atish Patra, Rob Herring, Alistair Francis,
Paul Walmsley, Palmer Dabbelt, linux-riscv, Padmarao Begari
On Thu, Oct 29, 2020 at 6:42 PM Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>
> On 28/10/2020 23:27, Atish Patra wrote:
> > Add initial DTS for Microchip ICICLE board having only
> > essential devcies (clocks, sdhci, ethernet, serial, etc).
> >
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > ---
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/microchip/Makefile | 2 +
> > .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
> > 3 files changed, 316 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> > create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> >
> > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > index ca1f8cbd78c0..3ea94ea0a18a 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -1,5 +1,6 @@
> > # SPDX-License-Identifier: GPL-2.0
> > subdir-y += sifive
> > subdir-y += kendryte
> > +subdir-y += microchip
> >
> > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> > diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
> > new file mode 100644
> > index 000000000000..55ad77521304
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
> > diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> > new file mode 100644
> > index 000000000000..5848920af55c
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> > @@ -0,0 +1,313 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +
> > +/* Clock frequency (in Hz) of the rtcclk */
> > +#define RTCCLK_FREQ 1000000
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + model = "Microchip PolarFire-SoC";
> > + compatible = "microchip,polarfire-soc";
> > +
> > + chosen {
> > + stdout-path = &serial0;
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <RTCCLK_FREQ>;
> > +
> > + cpu@0 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <128>;
> > + i-cache-size = <16384>;
> > + reg = <0>;
> > + riscv,isa = "rv64imac";
> > + status = "disabled";
> > +
> > + cpu0_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > +
> > + cpu@1 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <1>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > +
> > + cpu1_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > +
> > + cpu@2 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <2>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > +
> > + cpu2_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > +
> > + cpu@3 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <3>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > +
> > + cpu3_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > +
> > + cpu@4 {
> > + clock-frequency = <0>;
> > + compatible = "sifive,rocket0", "riscv";
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <32>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <32>;
> > + mmu-type = "riscv,sv39";
> > + reg = <4>;
> > + riscv,isa = "rv64imafdc";
> > + tlb-split;
> > + status = "okay";
> > + cpu4_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + };
> > +
> > + memory@80000000 {
> > + device_type = "memory";
> > + reg = <0x0 0x80000000 0x0 0x40000000>;
> > + clocks = <&clkcfg 26>;
> > + };
>
> U-boot doesn't seem to be updating this properly.
>
> The board should have 2GiB, confirmed by looking at the device's
> chip markings. We only see 1GiB memory. The 0x80000000 bus window
> is only capable of dealing with 1GiB memory. The higher 64-bit one
> can have 16GiB mapped.
>
> Do we need a second node for the second GiB of memory?
>
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + compatible = "simple-bus";
> > + ranges;
> > +
> > + cache-controller@2010000 {
> > + compatible = "sifive,fu540-c000-ccache", "cache";
> > + cache-block-size = <64>;
> > + cache-level = <2>;
> > + cache-sets = <1024>;
> > + cache-size = <2097152>;
> > + cache-unified;
> > + interrupt-parent = <&plic>;
> > + interrupts = <1 2 3>;
> > + reg = <0x0 0x2010000 0x0 0x1000>;
> > + };
> > +
> > + clint@2000000 {
> > + compatible = "riscv,clint0";
> > + reg = <0x0 0x2000000 0x0 0xC000>;
> > + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
> > + &cpu1_intc 3 &cpu1_intc 7
> > + &cpu2_intc 3 &cpu2_intc 7
> > + &cpu3_intc 3 &cpu3_intc 7
> > + &cpu4_intc 3 &cpu4_intc 7>;
> > + };
> > +
> > + plic: interrupt-controller@c000000 {
> > + #interrupt-cells = <1>;
> > + compatible = "sifive,plic-1.0.0";
> > + reg = <0x0 0xc000000 0x0 0x4000000>;
> > + riscv,ndev = <53>;
> > + interrupt-controller;
> > + interrupts-extended = <&cpu0_intc 11
> > + &cpu1_intc 11 &cpu1_intc 9
> > + &cpu2_intc 11 &cpu2_intc 9
> > + &cpu3_intc 11 &cpu3_intc 9
> > + &cpu4_intc 11 &cpu4_intc 9>;
> > + };
> > +
> > + dma@3000000 {
> > + compatible = "sifive,fu540-c000-pdma";
> > + reg = <0x0 0x3000000 0x0 0x8000>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <23 24 25 26 27 28 29 30>;
> > + #dma-cells = <1>;
> > + };
> > +
> > + refclk: refclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <600000000>;
> > + clock-output-names = "msspllclk";
> > + };
> > +
> > + clkcfg: clkcfg@20002000 {
> > + compatible = "microchip,pfsoc-clkcfg";
> > + reg = <0x0 0x20002000 0x0 0x1000>;
> > + reg-names = "mss_sysreg";
> > + clocks = <&refclk>;
> > + #clock-cells = <1>;
> > + clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", "MMUART2clk", "MMUART3clk", "MMUART4clk", "SPI0clk", "SPI1clk", "I2C0clk", "I2C1clk", "CAN0clk", "CAN1clk", "USBclk", "RESERVED", "RTCclk", "QSPIclk", "GPIO0clk", "GPIO1clk", "GPIO2clk", "DDRCclk", "FIC0clk", "FIC1clk", "FIC2clk", "FIC3clk", "ATHENAclk", "CFMclk";
>
> Any chance of making this list multi-line, it is difficult to read as-is.
Besides the multi-line issue, I believe the clock-output-names should
all have lower case names.
>
> > + };
> > +
> > + serial0: serial@20000000 {
> > + compatible = "ns16550a";
> > + reg = <0x0 0x20000000 0x0 0x400>;
> > + reg-io-width = <4>;
> > + reg-shift = <2>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <90>;
> > + current-speed = <115200>;
> > + clocks = <&clkcfg 8>;
> > + status = "okay";
> > + };
> > +
> > + serial1: serial@20100000 {
> > + compatible = "ns16550a";
> > + reg = <0x0 0x20100000 0x0 0x400>;
> > + reg-io-width = <4>;
> > + reg-shift = <2>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <91>;
> > + current-speed = <115200>;
> > + clocks = <&clkcfg 9>;
> > + status = "okay";
> > + };
> > +
> > + serial2: serial@20102000 {
> > + compatible = "ns16550a";
> > + reg = <0x0 0x20102000 0x0 0x400>;
> > + reg-io-width = <4>;
> > + reg-shift = <2>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <92>;
> > + current-speed = <115200>;
> > + clocks = <&clkcfg 10>;
> > + status = "okay";
> > + };
> > +
> > + serial3: serial@20104000 {
> > + compatible = "ns16550a";
> > + reg = <0x0 0x20104000 0x0 0x400>;
> > + reg-io-width = <4>;
> > + reg-shift = <2>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <93>;
> > + current-speed = <115200>;
> > + clocks = <&clkcfg 11>;
> > + status = "okay";
> > + };
> > +
> > + sdcard: sdhc@20008000 {
> > + compatible = "cdns,sd4hc";
> > + reg = <0x0 0x20008000 0x0 0x1000>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <88>;
> > + pinctrl-names = "default";
> > + clocks = <&clkcfg 6>;
> > + bus-width = <4>;
> > + disable-wp;
> > + no-1-8-v;
> > + cap-mmc-highspeed;
> > + cap-sd-highspeed;
> > + card-detect-delay = <200>;
> > + sd-uhs-sdr12;
> > + sd-uhs-sdr25;
> > + sd-uhs-sdr50;
> > + sd-uhs-sdr104;
> > + max-frequency = <200000000>;
> > + status = "okay";
> > + };
>
> Given eMMC is the default device, shouldn't that be default for the
> device tree too? Even if not, having the emmc node here would be a
> good thing as it is different to the SD node.
>
> > +
> > + emac1: ethernet@20112000 {
> > + compatible = "cdns,macb";
> > + reg = <0x0 0x20112000 0x0 0x2000>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <70 71 72 73>;
> > + mac-address = [56 34 12 00 FC 00];
> > + phy-mode = "sgmii";
> > + clocks = <&clkcfg 5>, <&clkcfg 2>;
> > + clock-names = "pclk", "hclk";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + phy1: ethernet-phy@9 {
> > + reg = <9>;
> > + ti,fifo-depth = <0x01>;
> > + };
> > + };
>
> Aren't there two ethernet ports on the board?
>
> Also, at the moment u-boot is not filling the MAC address parameter
> in so we've got at two boards on the network with the same MAC until
> we override it in the device tree for the second.
>
> > +
> > + uio_axi_lsram@2030000000 {
> > + compatible = "generic-uio";
> > + reg = <0x20 0x30000000 0 0x80000000 >;
> > + status = "okay";
> > + };
> > + };
> > +};
Regards,
Bin
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 1/3] RISC-V: Add Microchip PolarFire SoC kconfig option
2020-10-28 23:27 ` [RFC PATCH 1/3] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra
2020-10-30 9:08 ` Anup Patel
2020-11-03 9:55 ` Bin Meng
@ 2020-11-06 7:14 ` Palmer Dabbelt
2 siblings, 0 replies; 38+ messages in thread
From: Palmer Dabbelt @ 2020-11-06 7:14 UTC (permalink / raw)
To: Atish Patra
Cc: devicetree, aou, Cyril.Jean, daire.mcnamara, Anup Patel,
linux-kernel, Atish Patra, robh+dt, Alistair Francis,
Paul Walmsley, linux-riscv, padmarao.begari
On Wed, 28 Oct 2020 16:27:57 PDT (-0700), Atish Patra wrote:
> Add Microchip PolarFire kconfig option which selects SoC specific
> and common drivers that is required for this SoC.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> arch/riscv/Kconfig.socs | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 8a55f6156661..74d07250ecc5 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -22,6 +22,13 @@ config SOC_VIRT
> help
> This enables support for QEMU Virt Machine.
>
> +config SOC_MICROCHIP_POLARFIRE
> + bool "Microchip PolarFire SoCs"
> + select MCHP_CLK_PFSOC
> + select SIFIVE_PLIC
> + help
> + This enables support for Microchip PolarFire SoC platforms.
> +
> config SOC_KENDRYTE
> bool "Kendryte K210 SoC"
> depends on !MMU
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC
2020-10-28 23:27 ` [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra
2020-10-30 9:09 ` Anup Patel
2020-11-03 10:03 ` Bin Meng
@ 2020-11-06 7:14 ` Palmer Dabbelt
2 siblings, 0 replies; 38+ messages in thread
From: Palmer Dabbelt @ 2020-11-06 7:14 UTC (permalink / raw)
To: Atish Patra
Cc: devicetree, aou, Cyril.Jean, daire.mcnamara, Anup Patel,
linux-kernel, Atish Patra, robh+dt, Alistair Francis,
Paul Walmsley, linux-riscv, padmarao.begari
On Wed, 28 Oct 2020 16:27:59 PDT (-0700), Atish Patra wrote:
> Enable Microchip PolarFire ICICLE soc config in defconfig.
> It allows the default upstream kernel to boot on PolarFire ICICLE board.
I don't actually have one of these to test on yet. That said, if it boots for
you then I don't really see any reason to delay this -- maybe there's some
issues floating around, but I don't really see any reason to delay putting this
on for-next. I'd even go so far as to say we should take it during the RCs, as
so far it's just build/DT stuff.
Given that this is currently the only production RISC-V Linux board I don't
really any reason not to add it to the defconfigs.
Is there a reason this is an RFC?
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> arch/riscv/configs/defconfig | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index d222d353d86d..2660fa05451e 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -16,6 +16,7 @@ CONFIG_EXPERT=y
> CONFIG_BPF_SYSCALL=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_VIRT=y
> +CONFIG_SOC_MICROCHIP_POLARFIRE=y
> CONFIG_SMP=y
> CONFIG_JUMP_LABEL=y
> CONFIG_MODULES=y
> @@ -79,6 +80,9 @@ CONFIG_USB_OHCI_HCD=y
> CONFIG_USB_OHCI_HCD_PLATFORM=y
> CONFIG_USB_STORAGE=y
> CONFIG_USB_UAS=y
> +CONFIG_SDHCI=y
> +CONFIG_MMC_SDHCI_PLTFM=y
> +CONFIG_MMC_SDHCI_CADENCE=y
> CONFIG_MMC=y
> CONFIG_MMC_SPI=y
> CONFIG_RTC_CLASS=y
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
2020-10-28 23:27 ` [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra
2020-10-29 10:24 ` Ben Dooks
2020-10-30 9:05 ` Anup Patel
@ 2020-11-06 7:14 ` Palmer Dabbelt
2 siblings, 0 replies; 38+ messages in thread
From: Palmer Dabbelt @ 2020-11-06 7:14 UTC (permalink / raw)
To: Atish Patra, robh+dt
Cc: devicetree, aou, Cyril.Jean, daire.mcnamara, Anup Patel,
linux-kernel, Atish Patra, Alistair Francis, Paul Walmsley,
linux-riscv, padmarao.begari
On Wed, 28 Oct 2020 16:27:58 PDT (-0700), Atish Patra wrote:
> Add initial DTS for Microchip ICICLE board having only
> essential devcies (clocks, sdhci, ethernet, serial, etc).
This fails `make dtbs_check`. The fu540 fails too, so I guess it's not exactly
fair, though.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/microchip/Makefile | 2 +
> .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
> 3 files changed, 316 insertions(+)
> create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ca1f8cbd78c0..3ea94ea0a18a 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> subdir-y += sifive
> subdir-y += kendryte
> +subdir-y += microchip
>
> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
> new file mode 100644
> index 000000000000..55ad77521304
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
> diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> new file mode 100644
> index 000000000000..5848920af55c
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
> @@ -0,0 +1,313 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/* Copyright (c) 2020 Microchip Technology Inc */
> +
> +/dts-v1/;
> +
> +/* Clock frequency (in Hz) of the rtcclk */
> +#define RTCCLK_FREQ 1000000
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + model = "Microchip PolarFire-SoC";
> + compatible = "microchip,polarfire-soc";
> +
> + chosen {
> + stdout-path = &serial0;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <RTCCLK_FREQ>;
> +
> + cpu@0 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <16384>;
> + reg = <0>;
> + riscv,isa = "rv64imac";
> + status = "disabled";
> +
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> +
> + cpu@1 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <1>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + status = "okay";
> +
> + cpu1_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> +
> + cpu@2 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <2>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + status = "okay";
> +
> + cpu2_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> +
> + cpu@3 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <3>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + status = "okay";
> +
> + cpu3_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> +
> + cpu@4 {
> + clock-frequency = <0>;
> + compatible = "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <4>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + status = "okay";
> + cpu4_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0x0 0x40000000>;
> + clocks = <&clkcfg 26>;
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + cache-controller@2010000 {
> + compatible = "sifive,fu540-c000-ccache", "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <1024>;
> + cache-size = <2097152>;
> + cache-unified;
> + interrupt-parent = <&plic>;
> + interrupts = <1 2 3>;
> + reg = <0x0 0x2010000 0x0 0x1000>;
> + };
> +
> + clint@2000000 {
> + compatible = "riscv,clint0";
> + reg = <0x0 0x2000000 0x0 0xC000>;
> + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
> + &cpu1_intc 3 &cpu1_intc 7
> + &cpu2_intc 3 &cpu2_intc 7
> + &cpu3_intc 3 &cpu3_intc 7
> + &cpu4_intc 3 &cpu4_intc 7>;
> + };
> +
> + plic: interrupt-controller@c000000 {
> + #interrupt-cells = <1>;
> + compatible = "sifive,plic-1.0.0";
> + reg = <0x0 0xc000000 0x0 0x4000000>;
> + riscv,ndev = <53>;
> + interrupt-controller;
> + interrupts-extended = <&cpu0_intc 11
> + &cpu1_intc 11 &cpu1_intc 9
> + &cpu2_intc 11 &cpu2_intc 9
> + &cpu3_intc 11 &cpu3_intc 9
> + &cpu4_intc 11 &cpu4_intc 9>;
> + };
> +
> + dma@3000000 {
> + compatible = "sifive,fu540-c000-pdma";
> + reg = <0x0 0x3000000 0x0 0x8000>;
> + interrupt-parent = <&plic>;
> + interrupts = <23 24 25 26 27 28 29 30>;
> + #dma-cells = <1>;
> + };
> +
> + refclk: refclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <600000000>;
> + clock-output-names = "msspllclk";
> + };
> +
> + clkcfg: clkcfg@20002000 {
> + compatible = "microchip,pfsoc-clkcfg";
> + reg = <0x0 0x20002000 0x0 0x1000>;
> + reg-names = "mss_sysreg";
> + clocks = <&refclk>;
> + #clock-cells = <1>;
> + clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", "MMUART2clk", "MMUART3clk", "MMUART4clk", "SPI0clk", "SPI1clk", "I2C0clk", "I2C1clk", "CAN0clk", "CAN1clk", "USBclk", "RESERVED", "RTCclk", "QSPIclk", "GPIO0clk", "GPIO1clk", "GPIO2clk", "DDRCclk", "FIC0clk", "FIC1clk", "FIC2clk", "FIC3clk", "ATHENAclk", "CFMclk";
> + };
> +
> + serial0: serial@20000000 {
> + compatible = "ns16550a";
> + reg = <0x0 0x20000000 0x0 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupt-parent = <&plic>;
> + interrupts = <90>;
> + current-speed = <115200>;
> + clocks = <&clkcfg 8>;
> + status = "okay";
> + };
> +
> + serial1: serial@20100000 {
> + compatible = "ns16550a";
> + reg = <0x0 0x20100000 0x0 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupt-parent = <&plic>;
> + interrupts = <91>;
> + current-speed = <115200>;
> + clocks = <&clkcfg 9>;
> + status = "okay";
> + };
> +
> + serial2: serial@20102000 {
> + compatible = "ns16550a";
> + reg = <0x0 0x20102000 0x0 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupt-parent = <&plic>;
> + interrupts = <92>;
> + current-speed = <115200>;
> + clocks = <&clkcfg 10>;
> + status = "okay";
> + };
> +
> + serial3: serial@20104000 {
> + compatible = "ns16550a";
> + reg = <0x0 0x20104000 0x0 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupt-parent = <&plic>;
> + interrupts = <93>;
> + current-speed = <115200>;
> + clocks = <&clkcfg 11>;
> + status = "okay";
> + };
> +
> + sdcard: sdhc@20008000 {
> + compatible = "cdns,sd4hc";
> + reg = <0x0 0x20008000 0x0 0x1000>;
> + interrupt-parent = <&plic>;
> + interrupts = <88>;
> + pinctrl-names = "default";
> + clocks = <&clkcfg 6>;
> + bus-width = <4>;
> + disable-wp;
> + no-1-8-v;
> + cap-mmc-highspeed;
> + cap-sd-highspeed;
> + card-detect-delay = <200>;
> + sd-uhs-sdr12;
> + sd-uhs-sdr25;
> + sd-uhs-sdr50;
> + sd-uhs-sdr104;
> + max-frequency = <200000000>;
> + status = "okay";
> + };
> +
> + emac1: ethernet@20112000 {
> + compatible = "cdns,macb";
> + reg = <0x0 0x20112000 0x0 0x2000>;
> + interrupt-parent = <&plic>;
> + interrupts = <70 71 72 73>;
> + mac-address = [56 34 12 00 FC 00];
> + phy-mode = "sgmii";
> + clocks = <&clkcfg 5>, <&clkcfg 2>;
> + clock-names = "pclk", "hclk";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + phy1: ethernet-phy@9 {
> + reg = <9>;
> + ti,fifo-depth = <0x01>;
> + };
> + };
> +
> + uio_axi_lsram@2030000000 {
> + compatible = "generic-uio";
> + reg = <0x20 0x30000000 0 0x80000000 >;
> + status = "okay";
> + };
> + };
> +};
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 0/3] Add Microchip PolarFire Soc Support
2020-10-28 23:27 [RFC PATCH 0/3] Add Microchip PolarFire Soc Support Atish Patra
` (2 preceding siblings ...)
2020-10-28 23:27 ` [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra
@ 2020-11-06 7:14 ` Palmer Dabbelt
2020-11-06 7:37 ` Atish Patra
3 siblings, 1 reply; 38+ messages in thread
From: Palmer Dabbelt @ 2020-11-06 7:14 UTC (permalink / raw)
To: Atish Patra
Cc: devicetree, aou, Cyril.Jean, daire.mcnamara, Anup Patel,
linux-kernel, Atish Patra, robh+dt, Alistair Francis,
Paul Walmsley, linux-riscv, padmarao.begari
On Wed, 28 Oct 2020 16:27:56 PDT (-0700), Atish Patra wrote:
> This series adds minimal support for Microchip Polar Fire Soc Icicle kit.
> It is rebased on v5.10-rc1 and depends on clock support.
> Only MMC and ethernet drivers are enabled via this series.
> The idea here is to add the foundational patches so that other drivers
> can be added to on top of this.
>
> This series has been tested on Qemu and Polar Fire Soc Icicle kit.
> The following qemu series is necessary to test it on Qemu.
>
> The series can also be found at the following github repo.
>
> I noticed the latest version of mmc driver[2] hangs on the board with
> the latest clock driver. That's why, I have tested with the old clock
> driver available in the above github repo.
OK, I guess that's why it's an RFC?
> [1] https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg08582.html
> [2] https://www.spinics.net/lists/devicetree/msg383626.html
Looks like this one hasn't been merged yet. IDK if something is broken with my
mail client but I'm not seeing any github repos. If this depends on
not-yet-merged drivers then it's certainly RFC material, but aside from the DT
stuff (which should be straight-forward) it seems fine to me.
Since you posted this an an RFC I'm going to assume you're going to re-spin it.
Thanks!
>
> Atish Patra (3):
> RISC-V: Add Microchip PolarFire SoC kconfig option
> RISC-V: Initial DTS for Microchip ICICLE board
> RISC-V: Enable Microchip PolarFire ICICLE SoC
>
> arch/riscv/Kconfig.socs | 7 +
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/microchip/Makefile | 2 +
> .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
> arch/riscv/configs/defconfig | 4 +
> 5 files changed, 327 insertions(+)
> create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 0/3] Add Microchip PolarFire Soc Support
2020-11-06 7:14 ` [RFC PATCH 0/3] Add Microchip PolarFire Soc Support Palmer Dabbelt
@ 2020-11-06 7:37 ` Atish Patra
2020-11-06 8:11 ` Palmer Dabbelt
0 siblings, 1 reply; 38+ messages in thread
From: Atish Patra @ 2020-11-06 7:37 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: devicetree, Albert Ou, Cyril.Jean, Daire McNamara, Anup Patel,
linux-kernel@vger.kernel.org List, Atish Patra, Rob Herring,
Alistair Francis, Paul Walmsley, linux-riscv, Padmarao Begari
On Thu, Nov 5, 2020 at 11:14 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Wed, 28 Oct 2020 16:27:56 PDT (-0700), Atish Patra wrote:
> > This series adds minimal support for Microchip Polar Fire Soc Icicle kit.
> > It is rebased on v5.10-rc1 and depends on clock support.
> > Only MMC and ethernet drivers are enabled via this series.
> > The idea here is to add the foundational patches so that other drivers
> > can be added to on top of this.
> >
> > This series has been tested on Qemu and Polar Fire Soc Icicle kit.
> > The following qemu series is necessary to test it on Qemu.
> >
> > The series can also be found at the following github repo.
> >
> > I noticed the latest version of mmc driver[2] hangs on the board with
> > the latest clock driver. That's why, I have tested with the old clock
> > driver available in the above github repo.
>
> OK, I guess that's why it's an RFC?
>
Yes. The latest clock/pcie driver did not work for me. I might have
missed something in DT.
The idea for RFC is so that anybody who wants to try the latest kernel
on a polarfire board
has a meaningful way to test it.
> > [1] https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg08582.html
> > [2] https://www.spinics.net/lists/devicetree/msg383626.html
>
> Looks like this one hasn't been merged yet. IDK if something is broken with my
> mail client but I'm not seeing any github repos. If this depends on
> not-yet-merged drivers then it's certainly RFC material, but aside from the DT
> stuff (which should be straight-forward) it seems fine to me.
>
I think it makes sense to take this series once the clock driver is
merged at least.
> Since you posted this an an RFC I'm going to assume you're going to re-spin it.
>
Yes. There are some feedbacks on DT which I will fix in v2.
> Thanks!
>
> >
> > Atish Patra (3):
> > RISC-V: Add Microchip PolarFire SoC kconfig option
> > RISC-V: Initial DTS for Microchip ICICLE board
> > RISC-V: Enable Microchip PolarFire ICICLE SoC
> >
> > arch/riscv/Kconfig.socs | 7 +
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/microchip/Makefile | 2 +
> > .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
> > arch/riscv/configs/defconfig | 4 +
> > 5 files changed, 327 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> > create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
--
Regards,
Atish
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [RFC PATCH 0/3] Add Microchip PolarFire Soc Support
2020-11-06 7:37 ` Atish Patra
@ 2020-11-06 8:11 ` Palmer Dabbelt
0 siblings, 0 replies; 38+ messages in thread
From: Palmer Dabbelt @ 2020-11-06 8:11 UTC (permalink / raw)
To: atishp
Cc: devicetree, aou, Cyril.Jean, daire.mcnamara, Anup Patel,
linux-kernel, Atish Patra, robh+dt, Alistair Francis,
Paul Walmsley, linux-riscv, padmarao.begari
On Thu, 05 Nov 2020 23:37:45 PST (-0800), atishp@atishpatra.org wrote:
> On Thu, Nov 5, 2020 at 11:14 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>>
>> On Wed, 28 Oct 2020 16:27:56 PDT (-0700), Atish Patra wrote:
>> > This series adds minimal support for Microchip Polar Fire Soc Icicle kit.
>> > It is rebased on v5.10-rc1 and depends on clock support.
>> > Only MMC and ethernet drivers are enabled via this series.
>> > The idea here is to add the foundational patches so that other drivers
>> > can be added to on top of this.
>> >
>> > This series has been tested on Qemu and Polar Fire Soc Icicle kit.
>> > The following qemu series is necessary to test it on Qemu.
>> >
>> > The series can also be found at the following github repo.
>> >
>> > I noticed the latest version of mmc driver[2] hangs on the board with
>> > the latest clock driver. That's why, I have tested with the old clock
>> > driver available in the above github repo.
>>
>> OK, I guess that's why it's an RFC?
>>
>
> Yes. The latest clock/pcie driver did not work for me. I might have
> missed something in DT.
> The idea for RFC is so that anybody who wants to try the latest kernel
> on a polarfire board
> has a meaningful way to test it.
>
>> > [1] https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg08582.html
>> > [2] https://www.spinics.net/lists/devicetree/msg383626.html
>>
>> Looks like this one hasn't been merged yet. IDK if something is broken with my
>> mail client but I'm not seeing any github repos. If this depends on
>> not-yet-merged drivers then it's certainly RFC material, but aside from the DT
>> stuff (which should be straight-forward) it seems fine to me.
>>
>
> I think it makes sense to take this series once the clock driver is
> merged at least.
>
>> Since you posted this an an RFC I'm going to assume you're going to re-spin it.
>>
>
> Yes. There are some feedbacks on DT which I will fix in v2.
Thanks!
>
>> Thanks!
>>
>> >
>> > Atish Patra (3):
>> > RISC-V: Add Microchip PolarFire SoC kconfig option
>> > RISC-V: Initial DTS for Microchip ICICLE board
>> > RISC-V: Enable Microchip PolarFire ICICLE SoC
>> >
>> > arch/riscv/Kconfig.socs | 7 +
>> > arch/riscv/boot/dts/Makefile | 1 +
>> > arch/riscv/boot/dts/microchip/Makefile | 2 +
>> > .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
>> > arch/riscv/configs/defconfig | 4 +
>> > 5 files changed, 327 insertions(+)
>> > create mode 100644 arch/riscv/boot/dts/microchip/Makefile
>> > create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
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^ permalink raw reply [flat|nested] 38+ messages in thread
end of thread, other threads:[~2020-11-06 8:12 UTC | newest]
Thread overview: 38+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-28 23:27 [RFC PATCH 0/3] Add Microchip PolarFire Soc Support Atish Patra
2020-10-28 23:27 ` [RFC PATCH 1/3] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra
2020-10-30 9:08 ` Anup Patel
2020-11-03 9:55 ` Bin Meng
2020-11-06 7:14 ` Palmer Dabbelt
2020-10-28 23:27 ` [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra
2020-10-29 10:24 ` Ben Dooks
2020-10-30 7:11 ` Atish Patra
2020-10-30 21:19 ` Ben Dooks
2020-11-03 15:07 ` Atish Patra
2020-11-03 15:19 ` Ben Dooks
2020-11-03 18:10 ` Cyril.Jean
2020-11-03 18:28 ` Ben Dooks
2020-11-03 18:36 ` Atish Patra
2020-11-03 18:39 ` Ben Dooks
2020-11-03 18:45 ` Atish Patra
2020-11-03 18:40 ` Cyril.Jean
2020-11-03 18:46 ` Ben Dooks
2020-11-04 2:41 ` Bin Meng
2020-10-30 9:05 ` Anup Patel
2020-10-30 20:27 ` Atish Patra
2020-11-03 10:59 ` Ben Dooks
2020-11-03 15:08 ` Atish Patra
2020-10-30 21:20 ` Ben Dooks
2020-11-03 10:00 ` Bin Meng
2020-11-03 18:19 ` Cyril.Jean
2020-11-03 18:38 ` Atish Patra
2020-11-03 18:50 ` Cyril.Jean
2020-11-03 19:02 ` Atish Patra
2020-11-06 7:14 ` Palmer Dabbelt
2020-10-28 23:27 ` [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra
2020-10-30 9:09 ` Anup Patel
2020-10-30 21:21 ` Ben Dooks
2020-11-03 10:03 ` Bin Meng
2020-11-06 7:14 ` Palmer Dabbelt
2020-11-06 7:14 ` [RFC PATCH 0/3] Add Microchip PolarFire Soc Support Palmer Dabbelt
2020-11-06 7:37 ` Atish Patra
2020-11-06 8:11 ` Palmer Dabbelt
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