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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id 129sm1890354pfw.86.2020.12.09.01.49.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Dec 2020 01:49:22 -0800 (PST) From: Zong Li To: paul.walmsley@sifive.com, palmer@dabbelt.com, sboyd@kernel.org, schwab@linux-m68k.org, pragnesh.patel@openfive.com, aou@eecs.berkeley.edu, mturquette@baylibre.com, yash.shah@sifive.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v7 0/5] clk: add driver for the SiFive FU740 Date: Wed, 9 Dec 2020 17:49:11 +0800 Message-Id: <20201209094916.17383-1-zong.li@sifive.com> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201209_044927_311939_2394BEF2 X-CRM114-Status: GOOD ( 13.23 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zong Li Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add a driver for the SiFive FU740 PRCI IP block, which handles more clocks than FU540. These patches also refactor the original implementation by spliting the dependent-code of fu540 and fu740 respectively. We also add a separate patch for DT binding documentation of FU740 PRCI: https://patchwork.kernel.org/project/linux-riscv/patch/20201126030043.67390-1-zong.li@sifive.com/ Changed in v7: - Pick changes in v5 back up into this patch series. Changed in v6: - Modify the patch "Add clock enable and disable ops" by Pragnesh. The changes as follows: - Remove spin lock in enable and disable functions - Call enable_bypass() before PLL output disable - Rebase code to Linux v5.10-rc7 Changed in v5: - Fix copyright format - Add a link of documentation in commit message - Modify build dependency for sifive-prci.c - Add enable and disable functions by Pragnesh Patel Changed in v4: - Fix the wrong enable bit field shift for FU540 and FU740. Changed in v3: - Fix the wrong enable bit field shift for FU740. Changed in v2: - Remove the macro definition for __prci_clock_array. - Indicate the functional changes in commit message. - Using option -M and -C to create patches. - Rebase code to kernel v5.10-rc3. Pragnesh Patel (1): clk: sifive: Add clock enable and disable ops Zong Li (4): clk: sifive: Extract prci core to common base clk: sifive: Use common name for prci configuration clk: sifive: Add a driver for the SiFive FU740 PRCI IP block clk: sifive: Fix the wrong bit field shift arch/riscv/Kconfig.socs | 2 +- drivers/clk/sifive/Kconfig | 8 +- drivers/clk/sifive/Makefile | 2 +- drivers/clk/sifive/fu540-prci.c | 598 +----------------- drivers/clk/sifive/fu540-prci.h | 21 + drivers/clk/sifive/fu740-prci.c | 120 ++++ drivers/clk/sifive/fu740-prci.h | 21 + drivers/clk/sifive/sifive-prci.c | 574 +++++++++++++++++ drivers/clk/sifive/sifive-prci.h | 299 +++++++++ include/dt-bindings/clock/sifive-fu740-prci.h | 23 + 10 files changed, 1091 insertions(+), 577 deletions(-) create mode 100644 drivers/clk/sifive/fu540-prci.h create mode 100644 drivers/clk/sifive/fu740-prci.c create mode 100644 drivers/clk/sifive/fu740-prci.h create mode 100644 drivers/clk/sifive/sifive-prci.c create mode 100644 drivers/clk/sifive/sifive-prci.h create mode 100644 include/dt-bindings/clock/sifive-fu740-prci.h -- 2.29.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv