From: Anup Patel <anup.patel@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Rob Herring <robh+dt@kernel.org>
Cc: Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com>
Subject: [RFC PATCH v1 03/10] RISC-V: Allow more details in IPI operations
Date: Sat, 12 Jun 2021 21:34:15 +0530 [thread overview]
Message-ID: <20210612160422.330705-4-anup.patel@wdc.com> (raw)
In-Reply-To: <20210612160422.330705-1-anup.patel@wdc.com>
We extend struct riscv_ipi_ops so that the IPI providers (such as
SBI, CLINT driver, ACLINT SWI driver etc) can specify:
1) Name of the IPI operations
2) Whether IPIs are suitable for doing remote FENCEs
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
arch/riscv/include/asm/smp.h | 15 +++++++++++++++
arch/riscv/kernel/sbi.c | 2 ++
arch/riscv/kernel/smp.c | 25 ++++++++++++++++++++++++-
arch/riscv/mm/cacheflush.c | 2 +-
drivers/clocksource/timer-clint.c | 2 ++
5 files changed, 44 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index a7d2811f3536..4c4f0dde1164 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -16,11 +16,16 @@ struct seq_file;
extern unsigned long boot_cpu_hartid;
struct riscv_ipi_ops {
+ const char *name;
+ bool use_for_rfence;
void (*ipi_inject)(const struct cpumask *target);
void (*ipi_clear)(void);
};
#ifdef CONFIG_SMP
+
+#include <linux/jump_label.h>
+
/*
* Mapping between linux logical cpu index and hartid.
*/
@@ -45,6 +50,11 @@ void arch_send_call_function_single_ipi(int cpu);
int riscv_hartid_to_cpuid(int hartid);
void riscv_cpuid_to_hartid_mask(const struct cpumask *in, struct cpumask *out);
+/* Check if we can use IPIs for remote FENCE */
+extern struct static_key_false riscv_ipi_for_rfence;
+#define riscv_use_ipi_for_rfence() \
+ static_branch_unlikely(&riscv_ipi_for_rfence)
+
/* Set custom IPI operations */
void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops);
@@ -92,6 +102,11 @@ static inline void riscv_cpuid_to_hartid_mask(const struct cpumask *in,
cpumask_set_cpu(boot_cpu_hartid, out);
}
+static inline bool riscv_use_ipi_for_rfence(void)
+{
+ return false;
+}
+
static inline void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops)
{
}
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 8aeca26198f2..be2b7a89ce49 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -604,6 +604,8 @@ static void sbi_ipi_clear(void)
}
static const struct riscv_ipi_ops sbi_ipi_ops = {
+ .name = "SBI",
+ .use_for_rfence = false,
.ipi_inject = sbi_send_cpumask_ipi,
.ipi_clear = sbi_ipi_clear
};
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index eea0c9d11d9f..cffe3247b132 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -90,9 +90,32 @@ static void ipi_stop(void)
static const struct riscv_ipi_ops *ipi_ops __ro_after_init;
+DEFINE_STATIC_KEY_FALSE(riscv_ipi_for_rfence);
+EXPORT_SYMBOL_GPL(riscv_ipi_for_rfence);
+
void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops)
{
- ipi_ops = ops;
+ bool updated = true;
+
+ if (!ops)
+ return;
+
+ if (!ipi_ops) {
+ ipi_ops = ops;
+ } else {
+ if (!ipi_ops->use_for_rfence && ops->use_for_rfence)
+ ipi_ops = ops;
+ else
+ updated = false;
+ }
+
+ if (updated) {
+ if (ipi_ops->use_for_rfence)
+ static_branch_enable(&riscv_ipi_for_rfence);
+ else
+ static_branch_disable(&riscv_ipi_for_rfence);
+ pr_info("switched IPI operations to %s\n", ipi_ops->name);
+ }
}
EXPORT_SYMBOL_GPL(riscv_set_ipi_ops);
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index 094118663285..0ffe7d560dc8 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -16,7 +16,7 @@ static void ipi_remote_fence_i(void *info)
void flush_icache_all(void)
{
- if (IS_ENABLED(CONFIG_RISCV_SBI))
+ if (!riscv_use_ipi_for_rfence())
sbi_remote_fence_i(NULL);
else
on_each_cpu(ipi_remote_fence_i, NULL, 1);
diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
index 6cfe2ab73eb0..dfdcd94c1fd5 100644
--- a/drivers/clocksource/timer-clint.c
+++ b/drivers/clocksource/timer-clint.c
@@ -55,6 +55,8 @@ static void clint_clear_ipi(void)
}
static struct riscv_ipi_ops clint_ipi_ops = {
+ .name = "CLINT",
+ .use_for_rfence = true,
.ipi_inject = clint_send_ipi,
.ipi_clear = clint_clear_ipi,
};
--
2.25.1
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next prev parent reply other threads:[~2021-06-12 16:05 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-12 16:04 [RFC PATCH v1 00/10] RISC-V ACLINT Support Anup Patel
2021-06-12 16:04 ` [RFC PATCH v1 01/10] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel
2021-06-14 13:33 ` Bin Meng
2021-06-12 16:04 ` [RFC PATCH v1 02/10] RISC-V: Use common print prefix in smp.c Anup Patel
2021-06-14 13:33 ` Bin Meng
2021-06-12 16:04 ` Anup Patel [this message]
2021-06-12 16:04 ` [RFC PATCH v1 04/10] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel
2021-06-13 9:33 ` Marc Zyngier
2021-06-13 12:28 ` Anup Patel
2021-06-12 16:04 ` [RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver Anup Patel
2021-06-13 9:41 ` Marc Zyngier
2021-06-13 12:25 ` Anup Patel
2021-06-14 9:38 ` Marc Zyngier
2021-06-14 13:13 ` Anup Patel
2021-06-12 16:04 ` [RFC PATCH v1 06/10] RISC-V: Select ACLINT SWI driver for virt machine Anup Patel
2021-06-14 13:34 ` Bin Meng
2021-06-12 16:04 ` [RFC PATCH v1 07/10] clocksource: clint: Add support for ACLINT MTIMER device Anup Patel
2021-06-14 13:34 ` Bin Meng
2021-06-12 16:04 ` [RFC PATCH v1 08/10] dt-bindings: timer: Add ACLINT MTIMER bindings Anup Patel
2021-06-14 13:34 ` Bin Meng
2021-06-12 16:04 ` [RFC PATCH v1 09/10] dt-bindings: timer: Add ACLINT MSWI and SSWI bindings Anup Patel
2021-06-14 13:34 ` Bin Meng
2021-06-24 19:37 ` Rob Herring
2021-06-12 16:04 ` [RFC PATCH v1 10/10] MAINTAINERS: Add entry for RISC-V ACLINT drivers Anup Patel
2021-06-14 13:34 ` Bin Meng
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