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From: Anup Patel <anup.patel@wdc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Palmer Dabbelt <palmerdabbelt@google.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Rob Herring <robh+dt@kernel.org>
Cc: Atish Patra <atish.patra@wdc.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Anup Patel <anup@brainfault.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com>
Subject: [RFC PATCH v2 04/11] RISC-V: Allow marking IPIs as suitable for remote FENCEs
Date: Fri, 18 Jun 2021 18:08:44 +0530	[thread overview]
Message-ID: <20210618123851.1344518-5-anup.patel@wdc.com> (raw)
In-Reply-To: <20210618123851.1344518-1-anup.patel@wdc.com>

To do remote FENCEs (i.e. remote TLB flushes) using IPI calls on
the RISC-V kernel, we need hardware mechanism to directly inject
IPI from the RISC-V kernel instead of using SBI calls.

The upcoming ACLINT [M|S]SWI devices and AIA IMSIC devices allow
direct IPI injection from the RISC-V kernel. To support this, we
extend the riscv_ipi_set_virq_range() function so that irqchip
drivers can mark IPIs as suitable for remote FENCEs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 arch/riscv/include/asm/smp.h | 18 ++++++++++++++++--
 arch/riscv/kernel/sbi-ipi.c  |  2 +-
 arch/riscv/kernel/smp.c      |  9 ++++++++-
 3 files changed, 25 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 6bdaab122ffa..f4856c911335 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -16,6 +16,9 @@ struct seq_file;
 extern unsigned long boot_cpu_hartid;
 
 #ifdef CONFIG_SMP
+
+#include <linux/jump_label.h>
+
 /*
  * Mapping between linux logical cpu index and hartid.
  */
@@ -47,7 +50,12 @@ void riscv_ipi_disable(void);
 void riscv_ipi_setup(void);
 
 /* Set the IPI interrupt numbers for arch (called by irqchip drivers) */
-void riscv_ipi_set_virq_range(int virq, int nr_irqs);
+void riscv_ipi_set_virq_range(int virq, int nr_irqs, bool use_for_rfence);
+
+/* Check if we can use IPIs for remote FENCEs */
+DECLARE_STATIC_KEY_FALSE(riscv_ipi_for_rfence);
+#define riscv_use_ipi_for_rfence() \
+	static_branch_unlikely(&riscv_ipi_for_rfence)
 
 /* Secondary hart entry */
 asmlinkage void smp_callin(void);
@@ -102,10 +110,16 @@ static inline void riscv_ipi_setup(void)
 {
 }
 
-static inline void riscv_ipi_set_virq_range(int virq, int nr)
+static inline void riscv_ipi_set_virq_range(int virq, int nr,
+					    bool use_for_rfence)
 {
 }
 
+static inline bool riscv_use_ipi_for_rfence(void)
+{
+	return false;
+}
+
 #endif /* CONFIG_SMP */
 
 #if defined(CONFIG_HOTPLUG_CPU) && (CONFIG_SMP)
diff --git a/arch/riscv/kernel/sbi-ipi.c b/arch/riscv/kernel/sbi-ipi.c
index 6cc0ea95e1af..0a06542d2b74 100644
--- a/arch/riscv/kernel/sbi-ipi.c
+++ b/arch/riscv/kernel/sbi-ipi.c
@@ -153,7 +153,7 @@ static int __init sbi_ipi_set_virq(void)
 		return -ENOMEM;
 	}
 
-	riscv_ipi_set_virq_range(virq, BITS_PER_LONG);
+	riscv_ipi_set_virq_range(virq, BITS_PER_LONG, false);
 
 	return 0;
 }
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index 26d563615f53..3905177b6748 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -178,7 +178,10 @@ void riscv_ipi_setup(void)
 	riscv_ipi_enable();
 }
 
-void riscv_ipi_set_virq_range(int virq, int nr)
+DEFINE_STATIC_KEY_FALSE(riscv_ipi_for_rfence);
+EXPORT_SYMBOL_GPL(riscv_ipi_for_rfence);
+
+void riscv_ipi_set_virq_range(int virq, int nr, bool use_for_rfence)
 {
 	if (WARN_ON(ipi_virq_base))
 		return;
@@ -186,6 +189,10 @@ void riscv_ipi_set_virq_range(int virq, int nr)
 	WARN_ON(nr < IPI_MAX);
 	nr_ipi = min(nr, IPI_MAX);
 	ipi_virq_base = virq;
+	if (use_for_rfence)
+		static_branch_enable(&riscv_ipi_for_rfence);
+	else
+		static_branch_disable(&riscv_ipi_for_rfence);
 }
 EXPORT_SYMBOL_GPL(riscv_ipi_set_virq_range);
 
-- 
2.25.1


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  parent reply	other threads:[~2021-06-18 12:39 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-18 12:38 [RFC PATCH v2 00/11] Linux RISC-V ACLINT Support Anup Patel
2021-06-18 12:38 ` [RFC PATCH v2 01/11] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel
2021-06-18 12:38 ` [RFC PATCH v2 02/11] RISC-V: Use common print prefix in smp.c Anup Patel
2021-07-26 13:44   ` Marc Zyngier
2021-07-26 15:22     ` Anup Patel
2021-06-18 12:38 ` [RFC PATCH v2 03/11] RISC-V: Treat IPIs as normal Linux IRQs Anup Patel
2021-06-18 12:38 ` Anup Patel [this message]
2021-06-18 12:38 ` [RFC PATCH v2 05/11] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel
2021-06-18 12:38 ` [RFC PATCH v2 06/11] dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings Anup Patel
2021-07-12 19:22   ` Rob Herring
2021-07-13 15:27     ` Anup Patel
2021-07-27  6:32       ` Sean Anderson
2021-06-18 12:38 ` [RFC PATCH v2 07/11] irqchip: Add ACLINT software interrupt driver Anup Patel
2021-07-26 14:25   ` Marc Zyngier
2021-07-26 16:05     ` Anup Patel
2021-06-18 12:38 ` [RFC PATCH v2 08/11] RISC-V: Select ACLINT SWI driver for virt machine Anup Patel
2021-06-18 12:38 ` [RFC PATCH v2 09/11] dt-bindings: timer: Add ACLINT MTIMER bindings Anup Patel
2021-06-18 12:38 ` [RFC PATCH v2 10/11] clocksource: clint: Add support for ACLINT MTIMER device Anup Patel
2021-06-18 12:38 ` [RFC PATCH v2 11/11] MAINTAINERS: Add entry for RISC-V ACLINT drivers Anup Patel
2021-07-26 12:45 ` [RFC PATCH v2 00/11] Linux RISC-V ACLINT Support Anup Patel
2021-07-26 14:32   ` Marc Zyngier
2021-07-26 13:01     ` Anup Patel
2021-07-29  4:30       ` Palmer Dabbelt
2021-07-29  4:56         ` Anup Patel
2021-07-29  5:36         ` Anup Patel

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