From: Chen Huang <chenhuang5@huawei.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: Chen Huang <chenhuang5@huawei.com>,
Kefeng Wang <wangkefeng.wang@huawei.com>,
Darius Rad <darius@bluespec.com>,
Jisheng Zhang <jszhang3@mail.ustc.edu.cn>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v2 2/2] riscv: Support DCACHE_WORD_ACCESS
Date: Thu, 16 Sep 2021 13:08:55 +0000 [thread overview]
Message-ID: <20210916130855.4054926-3-chenhuang5@huawei.com> (raw)
In-Reply-To: <20210916130855.4054926-1-chenhuang5@huawei.com>
This patch selects DCACHE_WORD_ACCESS on riscv and implements support
for load_unaligned_zeropad.
DCACHE_WORD_ACCESS uses the word-at-a-time API for optimised string
comparisons in the vfs layer.
Signed-off-by: Chen Huang <chenhuang5@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index cd0be39d4c08..4e98ff76977f 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -44,6 +44,7 @@ config RISCV
select CLONE_BACKWARDS
select CLINT_TIMER if !MMU
select COMMON_CLK
+ select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
select EDAC_SUPPORT
select GENERIC_ARCH_TOPOLOGY if SMP
select GENERIC_ATOMIC64 if !64BIT
diff --git a/arch/riscv/include/asm/word-at-a-time.h b/arch/riscv/include/asm/word-at-a-time.h
index 7c086ac6ecd4..8f4ad1ec39fb 100644
--- a/arch/riscv/include/asm/word-at-a-time.h
+++ b/arch/riscv/include/asm/word-at-a-time.h
@@ -45,4 +45,41 @@ static inline unsigned long find_zero(unsigned long mask)
/* The mask we created is directly usable as a bytemask */
#define zero_bytemask(mask) (mask)
+#ifdef CONFIG_DCACHE_WORD_ACCESS
+#include <asm/asm.h>
+
+/*
+ * Load an unaligned word from kernel space.
+ *
+ * In the (very unlikely) case of the word being a page-crosser
+ * and the next page not being mapped, take the exception and
+ * return zeroes in the non-existing part.
+ */
+static inline unsigned long load_unaligned_zeropad(const void *addr)
+{
+ unsigned long ret, tmp;
+
+ /* Load word from unaligned pointer addr */
+ asm(
+ "1: " REG_L " %0, %3\n"
+ "2:\n"
+ " .section .fixup,\"ax\"\n"
+ " .balign 2\n"
+ "3: andi %1, %2, ~0x7\n"
+ " " REG_L " %0, (%1)\n"
+ " andi %1, %2, 0x7\n"
+ " slli %1, %1, 0x3\n"
+ " srl %0, %0, %1\n"
+ " jump 2b, %1\n"
+ " .previous\n"
+ " .section __ex_table,\"a\"\n"
+ " .balign " RISCV_SZPTR "\n"
+ " " RISCV_PTR " 1b, 3b\n"
+ " .previous"
+ : "=&r" (ret), "=&r" (tmp)
+ : "r" (addr), "m" (*(unsigned long *)addr));
+
+ return ret;
+}
+#endif /* DCACHE_WORD_ACCESS */
#endif /* _ASM_RISCV_WORD_AT_A_TIME_H */
--
2.25.1
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next prev parent reply other threads:[~2021-09-16 13:01 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-16 13:08 [PATCH v2 0/2] riscv: improve unaligned memory accesses Chen Huang
2021-09-16 13:08 ` [PATCH v2 1/2] riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS Chen Huang
2021-09-16 13:08 ` Chen Huang [this message]
2021-09-17 14:14 ` [PATCH v2 0/2] riscv: improve unaligned memory accesses Jisheng Zhang
2021-09-18 1:14 ` Kefeng Wang
2021-09-18 14:17 ` Jisheng Zhang
2021-10-05 1:04 ` Palmer Dabbelt
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