From: Rob Herring <robh@kernel.org>
To: Heiko Stuebner <heiko@sntech.de>
Cc: wefu@redhat.com, robh+dt@kernel.org, atishp@atishpatra.org,
krzk+dt@kernel.org, hch@lst.de, devicetree@vger.kernel.org,
palmer@dabbelt.com, cmuellner@linux.com,
paul.walmsley@sifive.com, linux-riscv@lists.infradead.org,
samuel@sholland.org, philipp.tomsich@vrull.eu, mick@ics.forth.gr,
drew@beagleboard.org, guoren@kernel.org,
linux-kernel@vger.kernel.org, anup@brainfault.org
Subject: Re: [PATCH 1/3] dt-bindings: riscv: document cbom-block-size
Date: Fri, 17 Jun 2022 14:37:09 -0600 [thread overview]
Message-ID: <20220617203709.GA2400541-robh@kernel.org> (raw)
In-Reply-To: <20220610004308.1903626-2-heiko@sntech.de>
On Fri, 10 Jun 2022 02:43:06 +0200, Heiko Stuebner wrote:
> The Zicbom operates on a block-size defined for the cpu-core,
> which does not necessarily match other cache-sizes used.
>
> So add the necessary property for the system to know the core's
> block-size.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
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next prev parent reply other threads:[~2022-06-17 21:04 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-10 0:43 [PATCH v3 0/3] riscv: implement Zicbom-based CMO instructions + the t-head variant Heiko Stuebner
2022-06-10 0:43 ` [PATCH 1/3] dt-bindings: riscv: document cbom-block-size Heiko Stuebner
2022-06-17 20:37 ` Rob Herring [this message]
2022-06-10 0:43 ` [PATCH 2/3] riscv: Implement Zicbom-based cache management operations Heiko Stuebner
2022-06-10 3:22 ` Randy Dunlap
2022-06-10 5:56 ` Christoph Hellwig
2022-06-15 16:56 ` Heiko Stübner
2022-06-15 17:49 ` Christoph Hellwig
2022-06-16 9:46 ` Heiko Stübner
2022-06-16 11:53 ` Christoph Hellwig
2022-06-16 12:09 ` Heiko Stübner
2022-06-16 12:11 ` Christoph Hellwig
2022-06-17 8:30 ` Heiko Stübner
2022-06-12 19:15 ` Samuel Holland
2022-06-13 5:50 ` Christoph Hellwig
2022-06-10 0:43 ` [PATCH 3/3] riscv: implement cache-management errata for T-Head SoCs Heiko Stuebner
2022-06-10 1:04 ` Guo Ren
2022-06-12 19:18 ` Samuel Holland
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