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([51.37.234.167]) by smtp.gmail.com with ESMTPSA id d7-20020a5d5387000000b0021d5c52f4b4sm9912961wrv.34.2022.07.05.12.04.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jul 2022 12:04:48 -0700 (PDT) From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Daire McNamara , Conor Dooley , Niklas Cassel , Damien Le Moal , Geert Uytterhoeven , Zong Li , Emil Renner Berthing , Jonas Hahnfeld Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Brice Goglin Subject: [PATCH 0/5] RISC-V: Add cpu-map topology information nodes Date: Tue, 5 Jul 2022 20:04:31 +0100 Message-Id: <20220705190435.1790466-1-mail@conchuod.ie> X-Mailer: git-send-email 2.37.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220705_120450_906138_D2287D66 X-CRM114-Status: UNSURE ( 9.83 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley It was reported to me that the Hive Unmatched incorrectly reports its topology to hwloc, but the StarFive VisionFive did in [0] & a subsequent off-list email from Brice (the hwloc maintainer). This turned out not to be entirely true, the /downstream/ version of the VisionFive does work correctly but not upstream, as the downstream devicetree has a cpu-map node that was added recently. This series adds a cpu-map node to all upstream devicetrees, which I have tested on mpfs & fu540. The first patch is lifted directly from the downstream StarFive devicetree. Thanks, Conor. 0: https://github.com/open-mpi/hwloc/issues/536 Conor Dooley (4): riscv: dts: sifive: Add fu540 topology information riscv: dts: sifive: Add fu740 topology information riscv: dts: microchip: Add mpfs' topology information riscv: dts: canaan: Add k210 topology information Jonas Hahnfeld (1): riscv: dts: starfive: Add JH7100 CPU topology arch/riscv/boot/dts/canaan/k210.dtsi | 12 +++++++++++ arch/riscv/boot/dts/microchip/mpfs.dtsi | 24 ++++++++++++++++++++++ arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 24 ++++++++++++++++++++++ arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 24 ++++++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7100.dtsi | 16 +++++++++++++-- 5 files changed, 98 insertions(+), 2 deletions(-) base-commit: b6f1f2fa2bddd69ff46a190b8120bd440fd50563 -- 2.37.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv