From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>,
Anup Patel <anup@brainfault.org>,
Albert Ou <aou@eecs.berkeley.edu>,
Atish Patra <atishp@atishpatra.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Guo Ren <guoren@kernel.org>, Heiko Stuebner <heiko@sntech.de>,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
linux-riscv@lists.infradead.org,
Palmer Dabbelt <palmer@dabbelt.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Tsukasa OI <research_trasio@irq.a4lg.com>,
Wei Fu <wefu@redhat.com>
Subject: [PATCH v7 2/4] RISC-V: Enable sstc extension parsing from DT
Date: Fri, 22 Jul 2022 09:50:45 -0700 [thread overview]
Message-ID: <20220722165047.519994-3-atishp@rivosinc.com> (raw)
In-Reply-To: <20220722165047.519994-1-atishp@rivosinc.com>
The ISA extension framework now allows parsing any multi-letter
ISA extension.
Enable that for sstc extension.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpu.c | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 4e2486881840..b186fff75198 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -53,6 +53,7 @@ extern unsigned long elf_hwcap;
enum riscv_isa_ext_id {
RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
RISCV_ISA_EXT_SVPBMT,
+ RISCV_ISA_EXT_SSTC,
RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index fba9e9f46a8c..0016d9337fe0 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -89,6 +89,7 @@ int riscv_of_parent_hartid(struct device_node *node)
static struct riscv_isa_ext_data isa_ext_arr[] = {
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
+ __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
};
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 12b05ce164bb..034bdbd189d0 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -199,6 +199,7 @@ void __init riscv_fill_hwcap(void)
} else {
SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
+ SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
}
#undef SET_ISA_EXT_MAP
}
--
2.25.1
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next prev parent reply other threads:[~2022-07-22 18:01 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-22 16:50 [PATCH v7 0/4] Add Sstc extension support Atish Patra
2022-07-22 16:50 ` [PATCH v7 1/4] RISC-V: Add SSTC extension CSR details Atish Patra
2022-07-22 16:50 ` Atish Patra [this message]
2022-07-22 16:50 ` [PATCH v7 3/4] RISC-V: Prefer sstc extension if available Atish Patra
2022-07-26 5:49 ` Atish Patra
2022-08-05 16:17 ` Atish Patra
2022-08-08 8:57 ` Guo Ren
2022-08-09 17:07 ` Atish Patra
2022-07-22 16:50 ` [PATCH v7 4/4] RISC-V: KVM: Support sstc extension Atish Patra
2022-07-23 4:47 ` [PATCH v7 0/4] Add Sstc extension support Anup Patel
2022-08-11 21:49 ` Palmer Dabbelt
2022-08-12 3:28 ` Anup Patel
2022-08-12 16:05 ` Palmer Dabbelt
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